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[/] [dblclockfft/] [trunk/] [bench/] [rtl/] [ifft_tb.v] - Blame information for rev 41

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1 41 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    ifft_tb.v
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//
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// Project:     A General Purpose Pipelined FFT Implementation
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//
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// Purpose:     This file is used to test whether an FFT followed by an
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//              immediate IFFT produces the input again.  It is a test
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//              bench for the composition of the two programs, and specifically
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//              for the IFFT.  As designed and built, this test bench would
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//              be difficult to implement in an FPGA (although I wouldn't
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//              put it past a smart individual), it was designed to be
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//              used within Verilator as part of a C++ simulation.  The
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//              simulation source may be found in this project inside
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//              ifft_tb.cpp.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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module  ifft_tb(i_clk, i_rst, i_ce, i_left, i_right, o_left, o_right, o_sync);
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        parameter       IWIDTH=16, MIDWIDTH=22, OWIDTH=28;
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        input                                   i_clk, i_rst, i_ce;
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        input           [(2*IWIDTH-1):0] i_left, i_right;
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        output  wire    [(2*OWIDTH-1):0] o_left, o_right;
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        output  wire                            o_sync;
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        wire                            m_sync;
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        wire    [(2*MIDWIDTH-1):0]       m_left, m_right;
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        fftmain fft(i_clk, i_rst, i_ce, i_left, i_right,
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                                m_left, m_right, m_sync);
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        wire    w_syncd;
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        reg     r_syncd;
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        always @(posedge i_clk)
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                if (i_rst)
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                        r_syncd <= 1'b0;
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                else
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                        r_syncd <= r_syncd || m_sync;
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        assign  w_syncd = r_syncd || m_sync;
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        ifftmain        ifft(i_clk, i_rst, (i_ce)&&(w_syncd), m_left, m_right,
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                                o_left, o_right, o_sync);
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endmodule

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