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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ../rtl/bimpy.v
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//
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// Project: A General Purpose Pipelined FFT Implementation
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//
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// Purpose: A simple 2-bit multiply based upon the fact that LUT's allow
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// 6-bits of input. In other words, I could build a 3-bit
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// multiply from 6 LUTs (5 actually, since the first could have two
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// outputs). This would allow multiplication of three bit digits, save
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// only for the fact that you would need two bits of carry. The bimpy
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// approach throttles back a bit and does a 2x2 bit multiply in a LUT,
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// guaranteeing that it will never carry more than one bit. While this
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// multiply is hardware independent (and can still run under Verilator
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// therefore), it is really motivated by trying to optimize for a
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// specific piece of hardware (Xilinx-7 series ...) that has at least
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// 4-input LUT's with carry chains.
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module bimpy(i_clk, i_ce, i_a, i_b, o_r);
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parameter BW=18, // Number of bits in i_b
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LUTB=2; // Number of bits in i_a for our LUT multiply
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input i_clk, i_ce;
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input [(LUTB-1):0] i_a;
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input [(BW-1):0] i_b;
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output reg [(BW+LUTB-1):0] o_r;
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wire [(BW+LUTB-2):0] w_r;
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wire [(BW+LUTB-3):1] c;
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assign w_r = { ((i_a[1])?i_b:{(BW){1'b0}}), 1'b0 }
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^ { 1'b0, ((i_a[0])?i_b:{(BW){1'b0}}) };
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assign c = { ((i_a[1])?i_b[(BW-2):0]:{(BW-1){1'b0}}) }
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& ((i_a[0])?i_b[(BW-1):1]:{(BW-1){1'b0}});
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always @(posedge i_clk)
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if (i_ce)
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o_r <= w_r + { c, 2'b0 };
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endmodule
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