URL https://opencores.org/ocsvn/dblclockfft/dblclockfft/trunk

Subversion Repositories dblclockfft

[/] [dblclockfft/] [trunk/] [sw/] [fftgen.cpp] - Blame information for rev 16

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////////////
//
// Filename:    fftgen.v
//
// Project:     A Doubletime Pipelined FFT
//
// Purpose:     This is the core generator for the project.  Every part
//              and piece of this project begins and ends in this program.
//              Once built, this program will build an FFT (or IFFT) core
//              of arbitrary width, precision, etc., that will run at
//              two samples per clock.  (Incidentally, I didn't pick two
//              samples per clock because it was easier, but rather because
//              there weren't any two-sample per clock FFT's posted on 
//              opencores.com.  Further, FFT's running at one sample per
//              clock aren't that hard to find.)
//
//              You can find the documentation for this program in two places.
//              One is in the usage() function below.  The second is in the
//              'doc'uments directory that comes with this package, 
//              specifically in the spec.pdf file.  If it's not there, type
//              make in the documents directory to build it.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/stat.h>
#include <string.h>
#include <string>
#include <math.h>
#include <ctype.h>
#include <assert.h>
 
#define COREDIR "fft-core"
 
const char      cpyleft[] =
"///////////////////////////////////////////////////////////////////////////\n"
"//\n"
"// Copyright (C) 2015, Gisselquist Technology, LLC\n"
"//\n"
"// This program is free software (firmware): you can redistribute it and/or\n"
"// modify it under the terms of  the GNU General Public License as published\n"
"// by the Free Software Foundation, either version 3 of the License, or (at\n"
"// your option) any later version.\n"
"//\n"
"// This program is distributed in the hope that it will be useful, but WITHOUT\n"
"// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n"
"// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License\n"
"// for more details.\n"
"//\n"
"// You should have received a copy of the GNU General Public License along\n"
"// with this program.  (It's in the $(ROOT)/doc directory, run make with no\n"
"// target there if the PDF file isn\'t present.)  If not, see\n"
"// <http://www.gnu.org/licenses/> for a copy.\n"
"//\n"
"// License:    GPL, v3, as defined and found on www.gnu.org,\n"
"//             http://www.gnu.org/licenses/gpl.html\n"
"//\n"
"//\n"
"///////////////////////////////////////////////////////////////////////////\n";
const char      prjname[] = "A Doubletime Pipelined FFT";
const char      creator[] =     "// Creator:    Dan Gisselquist, Ph.D.\n"
                                "//             Gisselquist Tecnology, LLC\n";
 
int     lgval(int vl) {
        int     lg;
 
        for(lg=1; (1<<lg) < vl; lg++)
                ;
        return lg;
}
 
int     nextlg(int vl) {
        int     r;
 
        for(r=1; r<vl; r<<=1)
                ;
        return r;
}
 
int     bflydelay(int nbits, int xtra) {
        int     cbits = nbits + xtra;
        int     delay;
        if (nbits+1<cbits)
                delay = nbits+4;
        else
                delay = cbits+3;
        return delay;
}
 
int     lgdelay(int nbits, int xtra) {
        // The butterfly code needs to compare a valid address, of this
        // many bits, with an address two greater.  This guarantees we
        // have enough bits for that comparison.  We'll also end up with
        // more storage space to look for these values, but without a 
        // redesign that's just what we'll deal with.
        return lgval(bflydelay(nbits, xtra)+3);
}
 
void    build_quarters(const char *fname) {
        FILE    *fp = fopen(fname, "w");
        if (NULL == fp) {
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
                perror("O/S Err was:");
                return;
        }
 
        fprintf(fp,
"///////////////////////////////////////////////////////////////////////////\n"
"//\n"
"// Filename:   qtrstage.v\n"
"//             \n"
"// Project:    %s\n"
"//\n"
"// Purpose:    This file encapsulates the 4 point stage of a decimation in\n"
"//             frequency FFT.  This particular implementation is optimized\n"
"//             so that all of the multiplies are accomplished by additions\n"
"//             and multiplexers only.\n"
"//\n"
"//\n%s"
"//\n",
                prjname, creator);
        fprintf(fp, "%s", cpyleft);
 
        fprintf(fp,
"module\tqtrstage(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync);\n"
        "\tparameter    IWIDTH=16, OWIDTH=IWIDTH+1;\n"
        "\t// Parameters specific to the core that should be changed when this\n"
        "\t// core is built ... Note that the minimum LGSPAN is 2.  Smaller \n"
        "\t// spans must use the fftdoubles stage.\n"
        "\tparameter\tLGWIDTH=8, ODD=0, INVERSE=0,SHIFT=0,ROUND=1;\n"
        "\tinput\t                              i_clk, i_rst, i_ce, i_sync;\n"
        "\tinput\t      [(2*IWIDTH-1):0]        i_data;\n"
        "\toutput\treg  [(2*OWIDTH-1):0]        o_data;\n"
        "\toutput\treg                          o_sync;\n"
        "\t\n");
        fprintf(fp,
        "\treg\t        wait_for_sync;\n"
        "\treg\t[2:0]   pipeline;\n"
"\n"
        "\treg\t[(IWIDTH):0]    sum_r, sum_i, diff_r, diff_i;\n"
        "\twire\t[(IWIDTH):0]   n_diff_r, n_diff_i;\n"
        "\tassign n_diff_r = -diff_r;\n"
        "\tassign n_diff_i = -diff_i;\n"
"\n"
        "\treg\t[(2*OWIDTH-1):0]        ob_a;\n"
        "\twire\t[(2*OWIDTH-1):0]       ob_b;\n"
        "\treg\t[(OWIDTH-1):0]          ob_b_r, ob_b_i;\n"
        "\tassign       ob_b = { ob_b_r, ob_b_i };\n"
"\n"
        "\treg\t[(LGWIDTH-1):0]         iaddr;\n"
        "\treg\t[(2*IWIDTH-1):0]        imem;\n"
"\n"
        "\twire\tsigned\t[(IWIDTH-1):0]\timem_r, imem_i;\n"
        "\tassign\timem_r = imem[(2*IWIDTH-1):(IWIDTH)];\n"
        "\tassign\timem_i = imem[(IWIDTH-1):0];\n"
"\n"
        "\twire\tsigned\t[(IWIDTH-1):0]\ti_data_r, i_data_i;\n"
        "\tassign\ti_data_r = i_data[(2*IWIDTH-1):(IWIDTH)];\n"
        "\tassign\ti_data_i = i_data[(IWIDTH-1):0];\n"
"\n"
        "\treg  [(2*OWIDTH-1):0]        omem;\n"
"\n");
        fprintf(fp,
        "\twire [(IWIDTH-1):0]  rnd;\n"
        "\tgenerate\n"
        "\tif ((ROUND)&&((IWIDTH+1-OWIDTH-SHIFT)>0))\n"
                "\t\tassign rnd = { {(IWIDTH-1){1'b0}}, 1'b1 };\n"
        "\telse\n"
                "\t\tassign rnd = { {(IWIDTH){1'b0}}};\n"
        "\tendgenerate\n"
"\n"
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_rst)\n"
                "\t\tbegin\n"
                        "\t\t\twait_for_sync <= 1'b1;\n"
                        "\t\t\tiaddr <= 0;\n"
                        "\t\t\tpipeline <= 3'b000;\n"
                "\t\tend\n"
                "\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
                "\t\tbegin\n"
                        "\t\t\t// Always\n"
                        "\t\t\timem <= i_data;\n"
                        "\t\t\tiaddr <= iaddr + 1;\n"
                        "\t\t\twait_for_sync <= 1'b0;\n"
"\n"
                        "\t\t\t// In sequence, clock = 0\n"
                        "\t\t\tif (iaddr[0])\n"
                        "\t\t\tbegin\n"
                                "\t\t\t\tsum_r  <= imem_r + i_data_r + rnd;\n"
                                "\t\t\t\tsum_i  <= imem_i + i_data_i + rnd;\n"
                                "\t\t\t\tdiff_r <= imem_r - i_data_r + rnd;\n"
                                "\t\t\t\tdiff_i <= imem_i - i_data_i + rnd;\n"
"\n"
                        "\t\t\t\tpipeline[2:0] <= { pipeline[1:0], 1'b1 };\n"
                        "\t\t\tend else\n"
                        "\t\t\t\tpipeline[2:0] <= { pipeline[1:0], 1'b0 };\n"
"\n"
                        "\t\t\t// In sequence, clock = 1\n"
                        "\t\t\tif (pipeline[1])\n"
                        "\t\t\tbegin\n"
"\t\t\t\tob_a <= { sum_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)],\n"
        "\t\t\t\t\t\tsum_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)] };\n"
                                "\t\t\t\t// on Even, W = e^{-j2pi 1/4 0} = 1\n"
                                "\t\t\t\tif (ODD == 0)\n"
                                "\t\t\t\tbegin\n"
"\t\t\t\t\tob_b_r <= diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
"\t\t\t\t\tob_b_i <= diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
// "\t\t\t\t\tob_b_r <=   { (OWIDTH) {1'b0} };\n"
// "\t\t\t\t\tob_b_i <=   { (OWIDTH) {1'b0} };\n"
                                "\t\t\t\tend else if (INVERSE==0) begin\n"
"\t\t\t\t\t// on Odd, W = e^{-j2pi 1/4} = -j\n"
"\t\t\t\t\tob_b_r <=   diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
"\t\t\t\t\tob_b_i <= n_diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
// "\t\t\t\t\tob_b_r <=   { (OWIDTH) {1'b0} };\n"
// "\t\t\t\t\tob_b_i <=   { (OWIDTH) {1'b0} };\n"
                                "\t\t\t\tend else begin\n"
"\t\t\t\t\t// on Odd, W = e^{j2pi 1/4} = j\n"
"\t\t\t\t\tob_b_r <= n_diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
"\t\t\t\t\tob_b_i <=   diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
// "\t\t\t\t\tob_b_r <=   { (OWIDTH) {1'b0} };\n"
// "\t\t\t\t\tob_b_i <=   { (OWIDTH) {1'b0} };\n"
 
                                "\t\t\t\tend\n"
                                "\t\t\t\t// (wire) ob_b <= { ob_b_r, ob_b_i };\n"
                        "\t\t\tend\n"
                        "\t\t\t// In sequence, clock = 2\n"
                        "\t\t\tif (pipeline[2])\n"
                        "\t\t\tbegin\n"
                                "\t\t\t\tomem <= ob_b;\n"
                                "\t\t\t\to_data <= ob_a;\n"
                        "\t\t\tend else\n"
                                "\t\t\t\to_data <= omem;\n"
                        "\t\t\t// Don\'t forget in the sync check that we are running\n"
                        "\t\t\t// at two clocks per sample.  Thus we need to\n"
                        "\t\t\t// produce a sync every 2^(LGWIDTH-1) clocks.\n"
                        "\t\t\to_sync <= &(~iaddr[(LGWIDTH-2):3]) && (iaddr[2:0] == 3'b100);\n"
                "\t\tend\n"
"endmodule\n");
}
 
void    build_dblstage(const char *fname) {
        FILE    *fp = fopen(fname, "w");
        if (NULL == fp) {
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
                perror("O/S Err was:");
                return;
        }
 
        fprintf(fp,
"///////////////////////////////////////////////////////////////////////////\n"
"//\n"
"// Filename:   dblstage.v\n"
"//\n"
"// Project:    %s\n"
"//\n"
"// Purpose:    This is part of an FPGA implementation that will process\n"
"//             the final stage of a decimate-in-frequency FFT, running\n"
"//             through the data at two samples per clock.  If you notice\n"
"//             from the derivation of an FFT, the only time both even and\n"
"//             odd samples are used at the same time is in this stage.\n"
"//             Therefore, other than this stage and these twiddles, all of\n"
"//             the other stages can run two stages at a time at one sample\n"
"//             per clock.\n"
"//\n"
"//             In this implementation, the output is valid one clock after\n"
"//             the input is valid.  The output also accumulates one bit\n"
"//             above and beyond the number of bits in the input.\n"
"//             \n"
"//             i_clk   A system clock\n"
"//             i_rst   A synchronous reset\n"
"//             i_ce    Circuit enable--nothing happens unless this line is high\n"
"//             i_sync  A synchronization signal, high once per FFT at the start\n"
"//             i_left  The first (even) complex sample input.  The higher order\n"
"//                     bits contain the real portion, low order bits the\n"
"//                     imaginary portion, all in two\'s complement.\n"
"//             i_right The next (odd) complex sample input, same format as\n"
"//                     i_left.\n"
"//             o_left  The first (even) complex output.\n"
"//             o_right The next (odd) complex output.\n"
"//             o_sync  Output synchronization signal.\n"
"//\n%s"
"//\n", prjname, creator);
 
        fprintf(fp, "%s", cpyleft);
        fprintf(fp,
"module\tdblstage(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync);\n"
        "\tparameter\tIWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;\n" //  ROUND=1
        "\tinput\t\ti_clk, i_rst, i_ce, i_sync;\n"
        "\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"
        "\toutput\twire\t[(2*OWIDTH-1):0]\to_left, o_right;\n"
        "\toutput\treg\t\t\to_sync;\n"
"\n"
        "\twire\tsigned\t[(IWIDTH-1):0]\ti_in_0r, i_in_0i, i_in_1r, i_in_1i;\n"
        "\tassign\ti_in_0r = i_left[(2*IWIDTH-1):(IWIDTH)]; \n"
        "\tassign\ti_in_0i = i_left[(IWIDTH-1):0]; \n"
        "\tassign\ti_in_1r = i_right[(2*IWIDTH-1):(IWIDTH)]; \n"
        "\tassign\ti_in_1i = i_right[(IWIDTH-1):0]; \n"
        "\twire\t[(OWIDTH-1):0]\t\to_out_0r, o_out_0i,\n"
                                "\t\t\t\t\to_out_1r, o_out_1i;\n"
"\n"
"\n"
//      "\t// Handle a potential rounding situation, when IWIDTH=OWIDTH.\n"
//"\n"
//      "\twire\tsigned\t[(IWIDTH-1):0]\trnd;\n"
//"\n"
//      "\tgenerate\n"
//      "\tif ((ROUND==1)&&(IWIDTH==OWIDTH))\n"
//              "\t\tassign rnd = { {(IWIDTH-1){1'b0}}, 1'b1 };\n"
//      "\telse\n"
//              "\t\tassign rnd = { {(IWIDTH){1'b0}} };\n"
//      "\tendgenerate\n"
"\n"
        "\t// Don't forget that we accumulate a bit by adding two values\n"
        "\t// together. Therefore our intermediate value must have one more\n"
        "\t// bit than the two originals.\n"
        "\treg\t[IWIDTH:0]\tout_0r, out_0i, out_1r, out_1i;\n"
"\n"
        "\treg\twait_for_sync;\n"
"\n"
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_rst)\n"
                        "\t\t\twait_for_sync <= 1'b1;\n"
                "\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
                "\t\tbegin\n"
                        "\t\t\twait_for_sync <= 1'b0;\n"
                        "\t\t\t//\n"
                        "\t\t\tout_0r <= i_in_0r + i_in_1r;\n"  // + rnd
                        "\t\t\tout_0i <= i_in_0i + i_in_1i;\n"  // + rnd
                        "\t\t\t//\n"
                        "\t\t\tout_1r <= i_in_0r - i_in_1r;\n"  // + rnd
                        "\t\t\tout_1i <= i_in_0i - i_in_1i;\n"  // + rnd
                        "\t\t\t//\n"
                        "\t\t\to_sync <= i_sync;\n"
                "\t\tend\n"
"\n"
        "\t// Now, if the master control program doesn't want to keep all of\n"
        "\t// our bits, we can shift down to OWIDTH bits here.\n"
        "\tassign\to_out_0r = out_0r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
        "\tassign\to_out_0i = out_0i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
        "\tassign\to_out_1r = out_1r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
        "\tassign\to_out_1i = out_1i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
"\n"
        "\tassign\to_left  = { o_out_0r, o_out_0i };\n"
        "\tassign\to_right = { o_out_1r, o_out_1i };\n"
"\n"
"endmodule\n");
        fclose(fp);
}
 
void    build_multiply(const char *fname) {
        FILE    *fp = fopen(fname, "w");
        if (NULL == fp) {
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
                perror("O/S Err was:");
                return;
        }
 
        fprintf(fp,
"///////////////////////////////////////////////////////////////////////////\n"
"//\n"
"// Filename:   shiftaddmpy.v\n"
"//\n"
"// Project:    %s\n"
"//\n"
"// Purpose:    A portable shift and add multiply.\n"
"//\n"
"//             While both Xilinx and Altera will offer single clock \n"
"//             multiplies, this simple approach will multiply two numbers\n"
"//             on any architecture.  The result maintains the full width\n"
"//             of the multiply, there are no extra stuff bits, no rounding,\n"
"//             no shifted bits, etc.\n"
"//\n"
"//             Further, for those applications that can support it, this\n"
"//             multiply is pipelined and will produce one answer per clock.\n"
"//\n"
"//             For minimal processing delay, make the first parameter\n"
"//             the one with the least bits, so that AWIDTH <= BWIDTH.\n"
"//\n"
"//             The processing delay in this multiply is (AWIDTH+1) cycles.\n"
"//             That is, if the data is present on the input at clock t=0,\n"
"//             the result will be present on the output at time t=AWIDTH+1;\n"
"//\n"
"//\n%s"
"//\n", prjname, creator);
 
        fprintf(fp, "%s", cpyleft);
        fprintf(fp,
"module shiftaddmpy(i_clk, i_ce, i_a, i_b, o_r);\n"
        "\tparameter\tAWIDTH=16,BWIDTH=AWIDTH;\n"
        "\tinput\t\t\t\t\ti_clk, i_ce;\n"
        "\tinput\t\t[(AWIDTH-1):0]\t\ti_a;\n"
        "\tinput\t\t[(BWIDTH-1):0]\t\ti_b;\n"
        "\toutput\treg\t[(AWIDTH+BWIDTH-1):0]\to_r;\n"
"\n"
        "\treg\t[(AWIDTH-1):0]\tu_a;\n"
        "\treg\t[(BWIDTH-1):0]\tu_b;\n"
        "\treg\t\t\tsgn;\n"
"\n"
        "\treg\t[(AWIDTH-2):0]\t\tr_a[0:(AWIDTH-1)];\n"
        "\treg\t[(AWIDTH+BWIDTH-2):0]\tr_b[0:(AWIDTH-1)];\n"
        "\treg\t\t\t\tr_s[0:(AWIDTH-1)];\n"
        "\treg\t[(AWIDTH+BWIDTH-1):0]\tacc[0:(AWIDTH-1)];\n"
        "\tgenvar k;\n"
"\n"
        "\t// If we were forced to stay within two\'s complement arithmetic,\n"
        "\t// taking the absolute value here would require an additional bit.\n"
        "\t// However, because our results are now unsigned, we can stay\n"
        "\t// within the number of bits given (for now).\n"
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_ce)\n"
                "\t\tbegin\n"
                        "\t\t\tu_a <= (i_a[AWIDTH-1])?(-i_a):(i_a);\n"
                        "\t\t\tu_b <= (i_b[BWIDTH-1])?(-i_b):(i_b);\n"
                        "\t\t\tsgn <= i_a[AWIDTH-1] ^ i_b[BWIDTH-1];\n"
                "\t\tend\n"
"\n"
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_ce)\n"
                "\t\tbegin\n"
                        "\t\t\tacc[0] <= (u_a[0]) ? { {(AWIDTH){1'b0}}, u_b }\n"
                        "\t\t\t\t\t: {(AWIDTH+BWIDTH){1'b0}};\n"
                        "\t\t\tr_a[0] <= { u_a[(AWIDTH-1):1] };\n"
                        "\t\t\tr_b[0] <= { {(AWIDTH-1){1'b0}}, u_b };\n"
                        "\t\t\tr_s[0] <= sgn; // The final sign, needs to be preserved\n"
                "\t\tend\n"
"\n"
        "\tgenerate\n"
        "\talways @(posedge i_clk)\n"
        "\tif (i_ce)\n"
        "\tbegin\n"
                "\t\tfor(k=0; k<AWIDTH-1; k++)\n"
                "\t\tbegin\n"
                        "\t\t\tacc[k+1] <= acc[k] + ((r_a[k][0]) ? {r_b[k],1'b0}:0);\n"
                        "\t\t\tr_a[k+1] <= { 1'b0, r_a[k][(AWIDTH-2):1] };\n"
                        "\t\t\tr_b[k+1] <= { r_b[k][(AWIDTH+BWIDTH-3):0], 1'b0};\n"
                        "\t\t\tr_s[k+1] <= r_s[k];\n"
                "\t\tend\n"
        "\tend\n"
        "\tendgenerate\n"
"\n"
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_ce)\n"
                        "\t\t\to_r <= (r_s[AWIDTH-1]) ? (-acc[AWIDTH-1]) : acc[AWIDTH-1];\n"
"\n"
"endmodule\n");
 
        fclose(fp);
}
 
void    build_dblreverse(const char *fname) {
        FILE    *fp = fopen(fname, "w");
        if (NULL == fp) {
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
                perror("O/S Err was:");
                return;
        }
 
        fprintf(fp,
"///////////////////////////////////////////////////////////////////////////\n"
"//\n"
"// Filename:   dblreverse.v\n"
"//\n"
"// Project:    %s\n"
"//\n"
"// Purpose:    This module bitreverses a pipelined FFT input.  Operation is\n"
"//             expected as follows:\n"
"//\n"
"//             i_clk   A running clock at whatever system speed is offered.\n"
"//             i_rst   A synchronous reset signal, that resets all internals\n"
"//             i_ce    If this is one, one input is consumed and an output\n"
"//                     is produced.\n"
"//             i_in_0, i_in_1\n"
"//                     Two inputs to be consumed, each of width WIDTH.\n"
"//             o_out_0, o_out_1\n"
"//                     Two of the bitreversed outputs, also of the same\n"
"//                     width, WIDTH.  Of course, there is a delay from the\n"
"//                     first input to the first output.  For this purpose,\n"
"//                     o_sync is present.\n"
"//             o_sync  This will be a 1'b1 for the first value in any block.\n"
"//                     Following a reset, this will only become 1'b1 once\n"
"//                     the data has been loaded and is now valid.  After that,\n"
"//                     all outputs will be valid.\n"
"//\n%s"
"//\n", prjname, creator);
        fprintf(fp, "%s", cpyleft);
        fprintf(fp,
"\n\n"
"//\n"
"// How do we do bit reversing at two smples per clock?  Can we separate out\n"
"// our work into eight memory banks, writing two banks at once and reading\n"
"// another two banks in the same clock?\n"
"//\n"
"//     mem[00xxx0] = s_0[n]\n"
"//     mem[00xxx1] = s_1[n]\n"
"//     o_0[n] = mem[10xxx0]\n"
"//     o_1[n] = mem[11xxx0]\n"
"//     ...\n"
"//     mem[01xxx0] = s_0[m]\n"
"//     mem[01xxx1] = s_1[m]\n"
"//     o_0[m] = mem[10xxx1]\n"
"//     o_1[m] = mem[11xxx1]\n"
"//     ...\n"
"//     mem[10xxx0] = s_0[n]\n"
"//     mem[10xxx1] = s_1[n]\n"
"//     o_0[n] = mem[00xxx0]\n"
"//     o_1[n] = mem[01xxx0]\n"
"//     ...\n"
"//     mem[11xxx0] = s_0[m]\n"
"//     mem[11xxx1] = s_1[m]\n"
"//     o_0[m] = mem[00xxx1]\n"
"//     o_1[m] = mem[01xxx1]\n"
"//     ...\n"
"//\n"
"//     The answer is that, yes we can but: we need to use four memory banks\n"
"//     to do it properly.  These four banks are defined by the two bits\n"
"//     that determine the top and bottom of the correct address.  Larger\n"
"//     FFT\'s would require more memories.\n"
"//\n"
"//\n");
        fprintf(fp,
"module dblreverse(i_clk, i_rst, i_ce, i_in_0, i_in_1,\n"
        "\t\to_out_0, o_out_1, o_sync);\n"
        "\tparameter\t\t\tLGSIZE=4, WIDTH=24;\n"
        "\tinput\t\t\t\ti_clk, i_rst, i_ce;\n"
        "\tinput\t\t[(2*WIDTH-1):0]\ti_in_0, i_in_1;\n"
        "\toutput\treg\t[(2*WIDTH-1):0]\to_out_0, o_out_1;\n"
        "\toutput\treg\t\t\to_sync;\n"
"\n"
        "\treg\tin_reset;\n"
        "\treg\t[(LGSIZE):0]\tiaddr;\n"
        "\treg\t[(2*WIDTH-1):0]\tmem_0e [0:((1<<(LGSIZE-1))-1)];\n"
        "\treg\t[(2*WIDTH-1):0]\tmem_0o [0:((1<<(LGSIZE-1))-1)];\n"
        "\treg\t[(2*WIDTH-1):0]\tmem_1e [0:((1<<(LGSIZE-1))-1)];\n"
        "\treg\t[(2*WIDTH-1):0]\tmem_1o [0:((1<<(LGSIZE-1))-1)];\n"
"\n"
        "\twire\t[(2*LGSIZE-1):0]       braddr;\n"
        "\tgenvar\tk;\n"
        "\tgenerate for(k=0; k<LGSIZE; k++)\n"
                "\t\tassign braddr[k] = iaddr[LGSIZE-1-k];\n"
        "\tendgenerate\n"
"\n"
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_rst)\n"
                "\t\tbegin\n"
                        "\t\t\tiaddr <= 0;\n"
                        "\t\t\tin_reset <= 1'b1;\n"
                "\t\tend else if (i_ce)\n"
                "\t\tbegin\n"
                        "\t\t\tif (iaddr[(LGSIZE-1)])\n"
                        "\t\t\tbegin\n"
                                "\t\t\t\tmem_1e[{iaddr[LGSIZE],iaddr[(LGSIZE-2):1]}] <= i_in_0;\n"
                                "\t\t\t\tmem_1o[{iaddr[LGSIZE],iaddr[(LGSIZE-2):1]}] <= i_in_1;\n"
                        "\t\t\tend else begin\n"
                                "\t\t\t\tmem_0e[{iaddr[LGSIZE],iaddr[(LGSIZE-2):1]}] <= i_in_0;\n"
                                "\t\t\t\tmem_0o[{iaddr[LGSIZE],iaddr[(LGSIZE-2):1]}] <= i_in_1;\n"
                        "\t\t\tend\n"
                        "\t\t\tiaddr <= iaddr + 2;\n"
                        "\t\t\tif (&iaddr[(LGSIZE-1):1])\n"
                                "\t\t\t\tin_reset <= 1'b0;\n"
                        "\t\t\tif (in_reset)\n"
                        "\t\t\tbegin\n"
                                "\t\t\t\to_out_0 <= {(2*WIDTH){1'b0}};\n"
                                "\t\t\t\to_out_1 <= {(2*WIDTH){1'b0}};\n"
                                "\t\t\t\to_sync <= 1'b0;\n"
                        "\t\t\tend else\n"
                        "\t\t\tbegin\n"
                                "\t\t\t\tif (braddr[0])\n"
                                "\t\t\t\tbegin\n"
"\t\t\t\t\to_out_0 <= mem_0o[{~iaddr[LGSIZE],braddr[(LGSIZE-2):1]}];\n"
"\t\t\t\t\to_out_1 <= mem_1o[{~iaddr[LGSIZE],braddr[(LGSIZE-2):1]}];\n"
                                "\t\t\t\tend else begin\n"
"\t\t\t\t\to_out_0 <= mem_0e[{~iaddr[LGSIZE],braddr[(LGSIZE-2):1]}];\n"
"\t\t\t\t\to_out_1 <= mem_1e[{~iaddr[LGSIZE],braddr[(LGSIZE-2):1]}];\n"
                                "\t\t\t\tend\n"
                                "\t\t\t\to_sync <= ~(|iaddr[(LGSIZE-1):0]);\n"
                        "\t\t\tend\n"
                "\t\tend\n"
"\n"
"endmodule;\n");
 
        fclose(fp);
}
 
void    build_butterfly(const char *fname, int xtracbits) {
        FILE    *fp = fopen(fname, "w");
        if (NULL == fp) {
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
                perror("O/S Err was:");
                return;
        }
 
        fprintf(fp,
"///////////////////////////////////////////////////////////////////////////\n"
"//\n"
"// Filename:   butterfly.v\n"
"//\n"
"// Project:    %s\n"
"//\n"
"// Purpose:    This routine caculates a butterfly for a decimation\n"
"//             in frequency version of an FFT.  Specifically, given\n"
"//             complex Left and Right values together with a \n"
"//             coefficient, the output of this routine is given\n"
"//             by:\n"
"//\n"
"//             L' = L + R\n"
"//             R' = (L - R)*C\n"
"//\n"
"//             The rest of the junk below handles timing (mostly),\n"
"//             to make certain that L' and R' reach the output at\n"
"//             the same clock.  Further, just to make certain\n"
"//             that is the case, an 'aux' input exists.  This\n"
"//             aux value will come out of this routine synchronized\n"
"//             to the values it came in with.  (i.e., both L', R',\n"
"//             and aux all have the same delay.)  Hence, a caller\n"
"//             of this routine may set aux on the first input with\n"
"//             valid data, and then wait to see aux set on the output\n"
"//             to know when to find the first output with valid data.\n"
"//\n"
"//             All bits are preserved until the very last clock,\n"
"//             where any more bits than OWIDTH will be quietly\n"
"//             discarded.\n"
"//\n"
"//             This design features no overflow checking.\n"
"// \n"
"// Notes:\n"
"//             CORDIC:\n"
"//             Much as we would like, we can't use a cordic here.\n"
"//             The goal is to accomplish an FFT, as defined, and a\n"
"//             CORDIC places a scale factor onto the data.  Removing\n"
"//             the scale factor would cost a two multiplies, which\n"
"//             is precisely what we are trying to avoid.\n"
"//\n"
"//\n"
"//             3-MULTIPLIES:\n"
"//             It should also be possible to do this with three \n"
"//             multiplies and an extra two addition cycles.  \n"
"//\n"
"//             We want\n"
"//                     R+I = (a + jb) * (c + jd)\n"
"//                     R+I = (ac-bd) + j(ad+bc)\n"
"//             We multiply\n"
"//                     P1 = ac\n"
"//                     P2 = bd\n"
"//                     P3 = (a+b)(c+d)\n"
"//             Then \n"
"//                     R+I=(P1-P2)+j(P3-P2-P1)\n"
"//\n"
"//             WIDTHS:\n"
"//             On multiplying an X width number by an\n"
"//             Y width number, X>Y, the result should be (X+Y)\n"
"//             bits, right?\n"
"//             -2^(X-1) <= a <= 2^(X-1) - 1\n"
"//             -2^(Y-1) <= b <= 2^(Y-1) - 1\n"
"//             (2^(Y-1)-1)*(-2^(X-1)) <= ab <= 2^(X-1)2^(Y-1)\n"
"//             -2^(X+Y-2)+2^(X-1) <= ab <= 2^(X+Y-2) <= 2^(X+Y-1) - 1\n"
"//             -2^(X+Y-1) <= ab <= 2^(X+Y-1)-1\n"
"//             YUP!  But just barely.  Do this and you'll really want\n"
"//             to drop a bit, although you will risk overflow in so\n"
"//             doing.\n"
"//\n%s"
"//\n", prjname, creator);
        fprintf(fp, "%s", cpyleft);
 
        fprintf(fp,
"module\tbutterfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
                "\t\to_left, o_right, o_aux);\n"
        "\t// Public changeable parameters ...\n"
        "\tparameter IWIDTH=%d,CWIDTH=IWIDTH+%d,OWIDTH=IWIDTH+1;\n"
        "\t// Parameters specific to the core that should not be changed.\n"
        "\tparameter    MPYDELAY=%d'd%d, // (IWIDTH+1 < CWIDTH)?(IWIDTH+4):(CWIDTH+3),\n"
                        "\t\t\tSHIFT=0, ROUND=1;\n"
        "\t// The LGDELAY should be the base two log of the MPYDELAY.  If\n"
        "\t// this value is fractional, then round up to the nearest\n"
        "\t// integer: LGDELAY=ceil(log(MPYDELAY)/log(2));\n"
        "\tparameter\tLGDELAY=%d;\n"
        "\tinput\t\ti_clk, i_rst, i_ce;\n"
        "\tinput\t\t[(2*CWIDTH-1):0] i_coef;\n"
        "\tinput\t\t[(2*IWIDTH-1):0] i_left, i_right;\n"
        "\tinput\t\ti_aux;\n"
        "\toutput\twire [(2*OWIDTH-1):0] o_left, o_right;\n"
        "\toutput\twire o_aux;\n"
        "\n", 16, xtracbits, lgdelay(16,xtracbits),
        bflydelay(16, xtracbits), lgdelay(16,xtracbits));
        fprintf(fp,
        "\twire\t[(OWIDTH-1):0] o_left_r, o_left_i, o_right_r, o_right_i;\n"
"\n"
        "\treg\t[(2*IWIDTH-1):0]\tr_left, r_right;\n"
        "\treg\t\t\t\tr_aux, r_aux_2;\n"
        "\treg\t[(2*CWIDTH-1):0]\tr_coef, r_coef_2;\n"
        "\twire\tsigned\t[(CWIDTH-1):0]\tr_coef_r, r_coef_i;\n"
        "\tassign\tr_coef_r  = r_coef_2[ (2*CWIDTH-1):(CWIDTH)];\n"
        "\tassign\tr_coef_i  = r_coef_2[ (  CWIDTH-1):0];\n"
        "\twire\tsigned\t[(IWIDTH-1):0]\tr_left_r, r_left_i, r_right_r, r_right_i;\n"
        "\tassign\tr_left_r  = r_left[ (2*IWIDTH-1):(IWIDTH)];\n"
        "\tassign\tr_left_i  = r_left[ (IWIDTH-1):0];\n"
        "\tassign\tr_right_r = r_right[(2*IWIDTH-1):(IWIDTH)];\n"
        "\tassign\tr_right_i = r_right[(IWIDTH-1):0];\n"
"\n"
        "\treg\tsigned\t[(IWIDTH):0]\tr_sum_r, r_sum_i, r_dif_r, r_dif_i;\n"
"\n"
        "\treg  [(LGDELAY-1):0] fifo_addr;\n"
        "\twire [(LGDELAY-1):0] fifo_read_addr;\n"
        "\tassign\tfifo_read_addr = fifo_addr - MPYDELAY;\n"
        "\treg  [(2*IWIDTH+2):0]        fifo_left [ 0:((1<<LGDELAY)-1)];\n"
        "\treg\t\t\t\tovalid;\n"
"\n");
        fprintf(fp,
        "\t// Set up the input to the multiply\n"
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_ce)\n"
                "\t\tbegin\n"
                        "\t\t\t// One clock just latches the inputs\n"
                        "\t\t\tr_left <= i_left;        // No change in # of bits\n"
                        "\t\t\tr_right <= i_right;\n"
                        "\t\t\tr_aux <= i_aux;\n"
                        "\t\t\tr_coef  <= i_coef;\n"
                        "\t\t\t// Next clock adds/subtracts\n"
                        "\t\t\tr_sum_r <= r_left_r + r_right_r; // Now IWIDTH+1 bits\n"
                        "\t\t\tr_sum_i <= r_left_i + r_right_i;\n"
                        "\t\t\tr_dif_r <= r_left_r - r_right_r;\n"
                        "\t\t\tr_dif_i <= r_left_i - r_right_i;\n"
                        "\t\t\t// Other inputs are simply delayed on second clock\n"
                        "\t\t\tr_aux_2 <= r_aux;\n"
                        "\t\t\tr_coef_2<= r_coef;\n"
        "\t\tend\n"
"\n");
        fprintf(fp,
        "\t// Don\'t forget to record the even side, since it doesn\'t need\n"
        "\t// to be multiplied, but yet we still need the results in sync\n"
        "\t// with the answer when it is ready.\n"
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_rst)\n"
                "\t\tbegin\n"
                        "\t\t\tfifo_addr <= 0;\n"
                        "\t\t\tovalid <= 1'b0;\n"
                "\t\tend else if (i_ce)\n"
                "\t\tbegin\n"
                        "\t\t\t// Need to delay the sum side--nothing else happens\n"
                        "\t\t\t// to it, but it needs to stay synchronized with the\n"
                        "\t\t\t// right side.\n"
                        "\t\t\tfifo_left[fifo_addr] <= { r_aux_2, r_sum_r, r_sum_i };\n"
                        "\t\t\tfifo_addr <= fifo_addr + 1;\n"
"\n"
                        "\t\t\tovalid <= (ovalid) || (fifo_addr > (MPYDELAY+1));\n"
                "\t\tend\n"
"\n"
        "\twire\tsigned\t[(CWIDTH-1):0] ir_coef_r, ir_coef_i;\n"
        "\tassign\tir_coef_r = r_coef_2[(2*CWIDTH-1):CWIDTH];\n"
        "\tassign\tir_coef_i = r_coef_2[(CWIDTH-1):0];\n"
        "\twire\tsigned\t[((IWIDTH+2)+(CWIDTH+1)-1):0]\tp_one, p_two, p_three;\n"
"\n"
"\n");
        fprintf(fp,
        "\t// Multiply output is always a width of the sum of the widths of\n"
        "\t// the two inputs.  ALWAYS.  This is independent of the number of\n"
        "\t// bits in p_one, p_two, or p_three.  These values needed to \n"
        "\t// accumulate a bit (or two) each.  However, this approach to a\n"
        "\t// three multiply complex multiply cannot increase the total\n"
        "\t// number of bits in our final output.  We\'ll take care of\n"
        "\t// dropping back down to the proper width, OWIDTH, in our routine\n"
        "\t// below.\n"
"\n"
"\n");
        fprintf(fp,
        "\t// We accomplish here \"Karatsuba\" multiplication.  That is,\n"
        "\t// by doing three multiplies we accomplish the work of four.\n"
        "\t// Let\'s prove to ourselves that this works ... We wish to\n"
        "\t// multiply: (a+jb) * (c+jd), where a+jb is given by\n"
        "\t//\ta + jb = r_dif_r + j r_dif_i, and\n"
        "\t//\tc + jd = ir_coef_r + j ir_coef_i.\n"
        "\t// We do this by calculating the intermediate products P1, P2,\n"
        "\t// and P3 as\n"
        "\t//\tP1 = ac\n"
        "\t//\tP2 = bd\n"
        "\t//\tP3 = (a + b) * (c + d)\n"
        "\t// and then complete our final answer with\n"
        "\t//\tac - bd = P1 - P2 (this checks)\n"
        "\t//\tad + bc = P3 - P2 - P1\n"
        "\t//\t        = (ac + bc + ad + bd) - bd - ac\n"
        "\t//\t        = bc + ad (this checks)\n"
"\n"
"\n");
        fprintf(fp,
        "\t// This should really be based upon an IF, such as in\n"
        "\t// if (IWIDTH < CWIDTH) then ...\n"
        "\t// However, this is the only (other) way I know to do it.\n"
        "\tgenerate\n"
        "\tif (CWIDTH < IWIDTH+1)\n"
        "\tbegin\n"
                "\t\t// We need to pad these first two multiplies by an extra\n"
                "\t\t// bit just to keep them aligned with the third,\n"
                "\t\t// simpler, multiply.\n"
                "\t\tshiftaddmpy #(CWIDTH+1,IWIDTH+2) p1(i_clk, i_ce,\n"
                                "\t\t\t\t{ir_coef_r[CWIDTH-1],ir_coef_r},\n"
                                "\t\t\t\t{r_dif_r[IWIDTH],r_dif_r}, p_one);\n"
                "\t\tshiftaddmpy #(CWIDTH+1,IWIDTH+2) p2(i_clk, i_ce,\n"
                                "\t\t\t\t{ir_coef_i[CWIDTH-1],ir_coef_i},\n"
                                "\t\t\t\t{r_dif_i[IWIDTH],r_dif_i}, p_two);\n"
                "\t\tshiftaddmpy #(CWIDTH+1,IWIDTH+2) p3(i_clk, i_ce,\n"
                        "\t\t\t\tir_coef_i+ir_coef_r,\n"
                        "\t\t\t\tr_dif_r + r_dif_i,\n"
                        "\t\t\t\tp_three);\n"
        "\tend else begin\n"
                "\t\tshiftaddmpy #(IWIDTH+2,CWIDTH+1) p1a(i_clk, i_ce,\n"
                                "\t\t\t\t{r_dif_r[IWIDTH],r_dif_r},\n"
                                "\t\t\t\t{ir_coef_r[CWIDTH-1],ir_coef_r}, p_one);\n"
                "\t\tshiftaddmpy #(IWIDTH+2,CWIDTH+1) p2a(i_clk, i_ce,\n"
                                "\t\t\t\t{r_dif_i[IWIDTH], r_dif_i},\n"
                                "\t\t\t\t{ir_coef_i[CWIDTH-1],ir_coef_i}, p_two);\n"
                "\t\tshiftaddmpy #(IWIDTH+2,CWIDTH+1) p3a(i_clk, i_ce,\n"
                                "\t\t\t\tr_dif_r+r_dif_i,\n"
                                "\t\t\t\tir_coef_i+ir_coef_r,\n"
                                "\t\t\t\tp_three);\n"
        "\tend\n"
        "\tendgenerate\n"
"\n");
        fprintf(fp,
        "\t// These values are held in memory and delayed during the\n"
        "\t// multiply.  Here, we recover them.  During the multiply,\n"
        "\t// values were multiplied by 2^(CWIDTH-2)*exp{-j*2*pi*...},\n"
        "\t// therefore, the left_x values need to be right shifted by\n"
        "\t// CWIDTH-2 as well.  The additional bits come from a sign\n"
        "\t// extension.\n"
        "\twire aux;\n"
        "\twire\tsigned\t[(IWIDTH+CWIDTH):0]    fifo_i, fifo_r;\n"
        "\treg\t\t[(2*IWIDTH+2):0]      fifo_read;\n"
        "\tassign\tfifo_r = { {2{fifo_read[2*(IWIDTH+1)-1]}}, fifo_read[(2*(IWIDTH+1)-1):(IWIDTH+1)], {(CWIDTH-2){1'b0}} };\n"
        "\tassign\tfifo_i = { {2{fifo_read[(IWIDTH+1)-1]}}, fifo_read[((IWIDTH+1)-1):0], {(CWIDTH-2){1'b0}} };\n"
        "\tassign\taux = fifo_read[2*IWIDTH+2];\n"
"\n"
"\n"
        "\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] b_left_r, b_left_i,\n"
                        "\t\t\t\t\t\tb_right_r, b_right_i;\n"
        "\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] mpy_r, mpy_i;\n"
        "\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] rnd;\n"
        "\tgenerate\n"
        "\tif ((ROUND==0)||(CWIDTH+IWIDTH-OWIDTH-SHIFT<2))\n"
                "\t\tassign rnd = ({(CWIDTH+IWIDTH+3){1'b0}});\n"
        "\telse if ((IWIDTH+CWIDTH)-(OWIDTH+SHIFT) == 2)\n"
                "\t\tassign rnd = ({ {(OWIDTH+4+SHIFT){1'b0}},1'b1 });\n"
        "\telse\n"
                "\t\tassign rnd = ({ {(OWIDTH+4+SHIFT){1'b0}},1'b1,\n"
                "\t\t\t\t{((IWIDTH+CWIDTH+3)-(OWIDTH+SHIFT+5)){1'b0}} });\n"
        "\tendgenerate\n"
"\n");
        fprintf(fp,
        "\talways @(posedge i_clk)\n"
                "\t\tif (i_ce)\n"
                "\t\tbegin\n"
                        "\t\t\t// First clock, recover all values\n"
                        "\t\t\tfifo_read <= fifo_left[fifo_read_addr];\n"
                        "\t\t\t// These values are IWIDTH+CWIDTH+3 bits wide\n"
                        "\t\t\t// although they only need to be (IWIDTH+1)\n"
                        "\t\t\t// + (CWIDTH) bits wide.  (We\'ve got two\n"
                        "\t\t\t// extra bits we need to get rid of.)\n"
                        "\t\t\tmpy_r <= p_one - p_two;\n"
                        "\t\t\tmpy_i <= p_three - p_one - p_two;\n"
"\n"
                        "\t\t\t// Second clock, round and latch for final clock\n"
                        "\t\t\tb_right_r <= mpy_r + rnd;\n"
                        "\t\t\tb_right_i <= mpy_i + rnd;\n"
                        "\t\t\tb_left_r <= { {2{fifo_r[(IWIDTH+CWIDTH)]}},fifo_r } + rnd;\n"
                        "\t\t\tb_left_i <= { {2{fifo_i[(IWIDTH+CWIDTH)]}},fifo_i } + rnd;\n"
                        "\t\t\to_aux <= aux & ovalid;\n"
                "\t\tend\n"
"\n");
        fprintf(fp,
        "\t// Final clock--clock and remove unnecessary bits.\n"
        "\t// We have (IWIDTH+CWIDTH+3) bits here, we need to drop down to\n"
        "\t// OWIDTH, and SHIFT by SHIFT bits in the process.  The trick is\n"
        "\t// that we don\'t need (IWIDTH+CWIDTH+3) bits.  We\'ve accumulated\n"
        "\t// them, but the actual values will never fill all these bits.\n"
        "\t// In particular, we only need:\n"
        "\t//\t IWIDTH bits for the input\n"
        "\t//\t     +1 bit for the add/subtract\n"
        "\t//\t+CWIDTH bits for the coefficient multiply\n"
        "\t//\t     +1 bit for the add/subtract in the complex multiply\n"
        "\t//\t ------\n"
        "\t//\t (IWIDTH+CWIDTH+2) bits at full precision.\n"
        "\t//\n"
        "\t// However, the coefficient multiply multiplied by a maximum value\n"
        "\t// of 2^(CWIDTH-2).  Thus, we only have\n"
        "\t//\t   IWIDTH bits for the input\n"
        "\t//\t       +1 bit for the add/subtract\n"
        "\t//\t+CWIDTH-2 bits for the coefficient multiply\n"
        "\t//\t       +1 (optional) bit for the add/subtract in the cpx mpy.\n"
        "\t//\t -------- ... multiply.  (This last bit may be shifted out.)\n"
        "\t//\t (IWIDTH+CWIDTH) valid output bits. \n"
        "\t// Now, if the user wants to keep any extras of these (via OWIDTH),\n"
        "\t// or if he wishes to arbitrarily shift some of these off (via\n"
        "\t// SHIFT) we accomplish that here.\n"
        "\tassign o_left_r  = b_left_r[ (CWIDTH+IWIDTH-1-SHIFT-1):(CWIDTH+IWIDTH-OWIDTH-SHIFT-1)];\n"
        "\tassign o_left_i  = b_left_i[ (CWIDTH+IWIDTH-1-SHIFT-1):(CWIDTH+IWIDTH-OWIDTH-SHIFT-1)];\n"
        "\tassign o_right_r = b_right_r[(CWIDTH+IWIDTH-1-SHIFT-1):(CWIDTH+IWIDTH-OWIDTH-SHIFT-1)];\n"
        "\tassign o_right_i = b_right_i[(CWIDTH+IWIDTH-1-SHIFT-1):(CWIDTH+IWIDTH-OWIDTH-SHIFT-1)];\n"
"\n"
        "\t// As a final step, we pack our outputs into two packed two\'s\n"
        "\t// complement numbers per output word, so that each output word\n"
        "\t// has (2*OWIDTH) bits in it, with the top half being the real\n"
        "\t// portion and the bottom half being the imaginary portion.\n"
        "\tassign       o_left = { o_left_r, o_left_i };\n"
        "\tassign       o_right= { o_right_r,o_right_i};\n"
"\n"
"endmodule\n");
        fclose(fp);
}
 
void    build_stage(const char *fname, int stage, bool odd, int nbits, bool inv, int xtra) {
        FILE    *fstage = fopen(fname, "w");
        int     cbits = nbits + xtra;
 
        if ((cbits * 2) >= sizeof(long long)*8) {
                fprintf(stderr, "ERROR: CMEM Coefficient precision requested overflows long long data type.\n");
                exit(-1);
        }
 
        if (fstage == NULL) {
                fprintf(stderr, "ERROR: Could not open %s for writing!\n", fname);
                perror("O/S Err was:");
                fprintf(stderr, "Attempting to continue, but this file will be missing.\n");
                return;
        }
 
        fprintf(fstage,
"////////////////////////////////////////////////////////////////////////////\n"
"//\n"
"// Filename:   %sfftstage_%c%d.v\n"
"//\n"
"// Project:    %s\n"
"//\n"
"// Purpose:    This file is (almost) a Verilog source file.  It is meant to\n"
"//             be used by a FFT core compiler to generate FFTs which may be\n"
"//             used as part of an FFT core.  Specifically, this file \n"
"//             encapsulates the options of an FFT-stage.  For any 2^N length\n"
"//             FFT, there shall be (N-1) of these stages.  \n"
"//\n%s"
"//\n",
                (inv)?"i":"", (odd)?'o':'e', stage*2, prjname, creator);
        fprintf(fstage, "%s", cpyleft);
        fprintf(fstage, "module\t%sfftstage_%c%d(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync);\n",
                (inv)?"i":"", (odd)?'o':'e', stage*2);
        // These parameter values are useless at this point--they are to be
        // replaced by the parameter values in the calling program.  Only
        // problem is, the CWIDTH needs to match exactly!
        fprintf(fstage, "\tparameter\tIWIDTH=%d,CWIDTH=%d,OWIDTH=%d;\n",
                nbits, cbits, nbits+1);
        fprintf(fstage,
"\t// Parameters specific to the core that should be changed when this\n"
"\t// core is built ... Note that the minimum LGSPAN (the base two log\n"
"\t// of the span, or the base two log of the current FFT size) is 3.\n"
"\t// Smaller spans (i.e. the span of 2) must use the dblstage module.\n"
"\tparameter\tLGWIDTH=11, LGSPAN=9, LGBDLY=5, BFLYSHIFT=0;\n");
        fprintf(fstage,
"\tinput                                        i_clk, i_rst, i_ce, i_sync;\n"
"\tinput                [(2*IWIDTH-1):0]        i_data;\n"
"\toutput       reg     [(2*OWIDTH-1):0]        o_data;\n"
"\toutput       reg                             o_sync;\n"
"\n"
"\treg  wait_for_sync;\n"
"\treg  [(2*IWIDTH-1):0]        ib_a, ib_b;\n"
"\treg  [(2*CWIDTH-1):0]        ib_c;\n"
"\treg  ib_sync;\n"
"\n"
"\treg  b_started;\n"
"\twire ob_sync;\n"
"\twire [(2*OWIDTH-1):0]        ob_a, ob_b;\n");
        fprintf(fstage,
"\n"
"\t// %scmem is defined as an array of real and complex values,\n"
"\t// where the top CWIDTH bits are the real value and the bottom\n"
"\t// CWIDTH bits are the imaginary value.\n"
"\t//\n"
"\t// cmem[i] = { (2^(CWIDTH-2)) * cos(2*pi*i/(2^LGWIDTH)),\n"
"\t//           (2^(CWIDTH-2)) * sin(2*pi*i/(2^LGWIDTH)) };\n"
"\t//\n"
"\treg  [(2*CWIDTH-1):0]        %scmem [0:((1<<LGSPAN)-1)];\n"
"\tinitial\t$readmemh(\"%scmem_%c%d.hex\",%scmem);\n\n",
                (inv)?"i":"", (inv)?"i":"",
                (inv)?"i":"", (odd)?'o':'e',stage<<1,
                (inv)?"i":"");
        {
                FILE    *cmem;
 
                {
                        char    *memfile, *ptr;
 
                        memfile = new char[strlen(fname)+128];
                        strcpy(memfile, fname);
                        if ((NULL != (ptr = strrchr(memfile, '/')))&&(ptr>memfile)) {
                                ptr++;
                                sprintf(ptr, "%scmem_%c%d.hex", (inv)?"i":"", (odd)?'o':'e', stage*2);
                        } else {
                                sprintf(memfile, "%s/%scmem_%c%d.hex",
                                        COREDIR, (inv)?"i":"",
                                        (odd)?'o':'e', stage*2);
                        }
                        // strcpy(&memfile[strlen(memfile)-2], ".hex");
                        cmem = fopen(memfile, "w");
                        if (NULL == cmem) {
                                fprintf(stderr, "Could not open/write \'%s\' with FFT coefficients.\n", memfile);
                                perror("Err from O/S:");
                                exit(-2);
                        }
 
                        delete[] memfile;
                }
                // fprintf(cmem, "// CBITS = %d, inv = %s\n", cbits, (inv)?"true":"false");
                for(int i=0; i<stage/2; i++) {
                        int k = 2*i+odd;
                        double  W = ((inv)?1:-1)*2.0*M_PI*k/(double)(2*stage);
                        double  c, s;
                        long long ic, is, vl;
 
                        c = cos(W); s = sin(W);
                        ic = (long long)((double)((1ll<<(cbits-2)) * c + 0.5));
                        is = (long long)((double)((1ll<<(cbits-2)) * s + 0.5));
                        vl = (ic & (~(-1ll << (cbits))));
                        vl <<= (cbits);
                        vl |= (is & (~(-1ll << (cbits))));
                        fprintf(cmem, "%0*llx\n", ((cbits*2+3)/4), vl);
                        /*
                        fprintf(cmem, "%0*llx\t\t// %f+j%f -> %llx +j%llx\n",
                                ((cbits*2+3)/4), vl, c, s,
                                ic & (~(-1ll<<(((cbits+3)/4)*4))),
                                is & (~(-1ll<<(((cbits+3)/4)*4))));
                        */
                } fclose(cmem);
        }
 
        fprintf(fstage,
"\treg  [(LGWIDTH-2):0]         iaddr;\n"
"\treg  [(2*IWIDTH-1):0]        imem    [0:((1<<LGSPAN)-1)];\n"
"\n"
"\treg  [LGSPAN:0]              oB;\n"
"\treg  [(2*OWIDTH-1):0]        omem    [0:((1<<LGSPAN)-1)];\n"
"\n"
"\talways @(posedge i_clk)\n"
        "\t\tif (i_rst)\n"
        "\t\tbegin\n"
                "\t\t\twait_for_sync <= 1'b1;\n"
                "\t\t\tiaddr <= 0;\n"
                "\t\t\toB <= 0;\n"
                "\t\t\tib_sync   <= 1'b0;\n"
                "\t\t\to_sync    <= 1'b0;\n"
                "\t\t\tb_started <= 1'b0;\n"
        "\t\tend\n"
        "\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
        "\t\tbegin\n"
                "\t\t\t//\n"
                "\t\t\t// First step: Record what we\'re not ready to use yet\n"
                "\t\t\t//\n"
                "\t\t\timem[iaddr[(LGSPAN-1):0]] <= i_data;\n"
                "\t\t\tiaddr <= iaddr + 1;\n"
                "\t\t\twait_for_sync <= 1'b0;\n"
"\n"
                "\t\t\t//\n"
                "\t\t\t// Now, we have all the inputs, so let\'s feed the\n"
                "\t\t\t// butterfly\n"
                "\t\t\t//\n"
                "\t\t\tif (iaddr[LGSPAN])\n"
                "\t\t\tbegin\n"
                        "\t\t\t\t// One input from memory, ...\n"
                        "\t\t\t\tib_a <= imem[iaddr[(LGSPAN-1):0]];\n"
                        "\t\t\t\t// One input clocked in from the top\n"
                        "\t\t\t\tib_b <= i_data;\n"
                        "\t\t\t\t// Set the sync to true on the very first\n"
                        "\t\t\t\t// valid input in, and hence on the very\n"
                        "\t\t\t\t// first valid data out per FFT.\n"
                        "\t\t\t\tib_sync <= (iaddr==(1<<(LGSPAN)));\n"
                        "\t\t\t\tib_c <= %scmem[iaddr[(LGSPAN-1):0]];\n"
                "\t\t\tend else begin\n"
                        "\t\t\t\t// Just to make debugging easier, let\'s\n"
                        "\t\t\t\t// clear these registers.  That\'ll make\n"
                        "\t\t\t\t// the transition easier to watch.\n"
                        "\t\t\t\tib_a <= {(2*IWIDTH){1'b0}};\n"
                        "\t\t\t\tib_b <= {(2*IWIDTH){1'b0}};\n"
                        "\t\t\t\tib_sync <= 1'b0;\n"
                "\t\t\tend\n"
"\n"
                "\t\t\t//\n"
                "\t\t\t// Next step: recover the outputs from the butterfly\n"
                "\t\t\t//\n"
                "\t\t\tif ((ob_sync||b_started)&&(~oB[LGSPAN]))\n"
                "\t\t\tbegin // A butterfly output is available\n"
                        "\t\t\t\tb_started <= 1'b1;\n"
                        "\t\t\t\tomem[oB[(LGSPAN-1):0]] <= ob_b;\n"
                        "\t\t\t\toB <= oB+1;\n"
"\n"
                        "\t\t\t\to_sync <= (ob_sync);\n"
                        "\t\t\t\to_data <= ob_a;\n"
                "\t\t\tend else if (b_started)\n"
                "\t\t\tbegin // and keep outputting once you start--at a rate\n"
                "\t\t\t// of one guaranteed output per clock that has i_ce set.\n"
                        "\t\t\t\to_data <= omem[oB[(LGSPAN-1):0]];\n"
                        "\t\t\t\toB <= oB + 1;\n"
                        "\t\t\t\to_sync <= 1'b0;\n"
                "\t\t\tend else\n"
                        "\t\t\t\to_sync <= 1'b0;\n"
        "\t\tend\n"
"\n", (inv)?"i":"");
        fprintf(fstage,
"\tbutterfly #(.IWIDTH(IWIDTH),.CWIDTH(CWIDTH),.OWIDTH(OWIDTH),\n"
"\t\t\t.MPYDELAY(%d\'d%d),.LGDELAY(LGBDLY),.SHIFT(BFLYSHIFT))\n"
"\t\tbfly(i_clk, i_rst, i_ce, ib_c,\n"
"\t\t\tib_a, ib_b, ib_sync, ob_a, ob_b, ob_sync);\n"
"endmodule;\n",
        lgdelay(nbits, xtra), bflydelay(nbits, xtra));
}
 
void    usage(void) {
        fprintf(stderr,
"USAGE:\tfftgen [-f <size>] [-d dir] [-c cbits] [-n nbits] [-m mxbits] [-s01]\n"
// "\tfftgen -i\n"
"\t-c <cbits>\tCauses all internal complex coefficients to be\n"
"\t\tlonger than the corresponding data bits, to help avoid\n"
"\t\tcoefficient truncation errors.\n"
"\t-d <dir>\tPlaces all of the generated verilog files into <dir>.\n"
"\t-f <size>\tSets the size of the FFT as the number of complex\n"
"\t\tsamples input to the transform.\n"
"\t-n <nbits>\tSets the number of bits in the twos complement input\n"
"\t\tto the FFT routine.\n"
"\t-m <mxbits>\tSets the maximum bit width that the FFT should ever\n"
"\t\tproduce.  Internal values greater than this value will be\n"
"\t\ttruncated to this value.\n"
"\t-s\tSkip the final bit reversal stage.  This is useful in\n"
"\t\talgorithms that need to apply a filter without needing to do\n"
"\t\tbin shifting, as these algorithms can, with this option, just\n"
"\t\tmultiply by a bit reversed correlation sequence and then\n"
"\t\tinverse FFT the (still bit reversed) result.\n"
"\t-S\tInclude the final bit reversal stage (default).\n"
"\t-0\tA forward FFT (default), meaning that the coefficients are\n"
"\t\tgiven by e^{-j 2 pi k/N n }.\n"
"\t-1\tAn inverse FFT, meaning that the coefficients are\n"
"\t\tgiven by e^{ j 2 pi k/N n }.\n");
}
 
// Features still needed:
//      Interactivity.
//      Some number of maximum bits, beyond which we won't accumulate any more.
//      Obviously, the build_stage above.
//      Copying the files of interest into the fft-core directory, from
//              whatever directory this file is run out of.
int main(int argc, char **argv) {
        int     fftsize = -1, lgsize = -1;
        int     nbitsin = 16, xtracbits = 4;
        int     nbitsout, maxbitsout = -1;
        bool    bitreverse = true, inverse=false, interactive = false,
                verbose_flag = false;
        FILE    *vmain;
        std::string     coredir = "fft-core", cmdline = "";
 
        if (argc <= 1)
                usage();
 
        cmdline = argv[0];
        for(int argn=1; argn<argc; argn++) {
                cmdline += " ";
                cmdline += argv[argn];
        }
 
        for(int argn=1; argn<argc; argn++) {
                if ('-' == argv[argn][0]) {
                        for(int j=1; (argv[argn][j])&&(j<100); j++) {
                                switch(argv[argn][j]) {
                                        case '0':
                                                inverse = false;
                                                break;
                                        case '1':
                                                inverse = true;
                                                break;
                                        case 'c':
                                                if (argn+1 >= argc) {
                                                        printf("No extra number of coefficient bits given\n");
                                                        usage(); exit(-1);
                                                }
                                                xtracbits = atoi(argv[++argn]);
                                                j+= 200;
                                                break;
                                        case 'd':
                                                if (argn+1 >= argc) {
                                                        printf("No extra number of coefficient bits given\n");
                                                        usage(); exit(-1);
                                                }
                                                coredir = argv[++argn];
                                                j += 200;
                                                break;
                                        case 'f':
                                                if (argn+1 >= argc) {
                                                        printf("No FFT Size given\n");
                                                        usage(); exit(-1);
                                                }
                                                fftsize = atoi(argv[++argn]);
                                                { int sln = strlen(argv[argn]);
                                                if (!isdigit(argv[argn][sln-1])){
                                                        switch(argv[argn][sln-1]) {
                                                        case 'k': case 'K':
                                                                fftsize <<= 10;
                                                                break;
                                                        case 'm': case 'M':
                                                                fftsize <<= 20;
                                                                break;
                                                        case 'g': case 'G':
                                                                fftsize <<= 30;
                                                                break;
                                                        default:
                                                                printf("Unknown FFT size, %s\n", argv[argn]);
                                                                exit(-1);
                                                        }
                                                }}
                                                j += 200;
                                                break;
                                        case 'h':
                                                usage();
                                                exit(0);
                                                break;
                                        case 'i':
                                                interactive = true;
                                                break;
                                        case 'm':
                                                if (argn+1 >= argc) {
                                                        printf("No maximum output bit value given\n");
                                                        exit(-1);
                                                }
                                                maxbitsout = atoi(argv[++argn]);
                                                j += 200;
                                                break;
                                        case 'n':
                                                if (argn+1 >= argc) {
                                                        printf("No input bit size given\n");
                                                        exit(-1);
                                                }
                                                nbitsin = atoi(argv[++argn]);
                                                j += 200;
                                                break;
                                        case 'S':
                                                bitreverse = true;
                                                break;
                                        case 's':
                                                bitreverse = false;
                                                break;
                                        case 'v':
                                                verbose_flag = true;
                                                break;
                                        default:
                                                printf("Unknown argument, -%c\n", argv[argn][j]);
                                                usage();
                                                exit(-1);
                                }
                        }
                } else {
                        printf("Unrecognized argument, %s\n", argv[argn]);
                        usage();
                        exit(-1);
                }
        }
 
        if ((lgsize < 0)&&(fftsize > 1)) {
                for(lgsize=1; (1<<lgsize) < fftsize; lgsize++)
                        ;
        }
 
        if ((fftsize <= 0)||(nbitsin < 1)||(nbitsin>48)) {
                printf("INVALID PARAMETERS!!!!\n");
                exit(-1);
        }
 
 
        if (nextlg(fftsize) != fftsize) {
                fprintf(stderr, "ERR: FFTSize (%d) *must* be a power of two\n",
                                fftsize);
                exit(-1);
        } else if (fftsize < 2) {
                fprintf(stderr, "ERR: Minimum FFTSize is 2, not %d\n",
                                fftsize);
                if (fftsize == 1) {
                        fprintf(stderr, "You do realize that a 1 point FFT makes very little sense\n");
                        fprintf(stderr, "in an FFT operation that handles two samples per clock?\n");
                        fprintf(stderr, "If you really need to do an FFT of this size, the output\n");
                        fprintf(stderr, "can be connected straight to the input.\n");
                } else {
                        fprintf(stderr, "Indeed, a size of %d doesn\'t make much sense to me at all.\n", fftsize);
                        fprintf(stderr, "Is such an operation even defined?\n");
                }
                exit(-1);
        }
 
        // Calculate how many output bits we'll have, and what the log
        // based two size of our FFT is.
        {
                int     tmp_size = fftsize;
 
                // The first stage always accumulates one bit, regardless
                // of whether you need to or not.
                nbitsout = nbitsin + 1;
                tmp_size >>= 1;
 
                while(tmp_size > 4) {
                        nbitsout += 1;
                        tmp_size >>= 2;
                }
 
                if (tmp_size > 1)
                        nbitsout ++;
 
                if (fftsize <= 2)
                        bitreverse = false;
        } if ((maxbitsout > 0)&&(nbitsout > maxbitsout))
                nbitsout = maxbitsout;
 
 
        {
                struct stat     sbuf;
                if (lstat(coredir.c_str(), &sbuf)==0) {
                        if (!S_ISDIR(sbuf.st_mode)) {
                                fprintf(stderr, "\'%s\' already exists, and is not a directory!\n", coredir.c_str());
                                fprintf(stderr, "I will stop now, lest I overwrite something you care about.\n");
                                fprintf(stderr, "To try again, please remove this file.\n");
                                exit(-1);
                        }
                } else
                        mkdir(coredir.c_str(), 0755);
                if (access(coredir.c_str(), X_OK|W_OK) != 0) {
                        fprintf(stderr, "I have no access to the directory \'%s\'.\n", coredir.c_str());
                        exit(-1);
                }
        }
 
        {
                std::string     fname_string;
 
                fname_string = coredir;
                fname_string += "/";
                if (inverse) fname_string += "i";
                fname_string += "fftmain.v";
 
                vmain = fopen(fname_string.c_str(), "w");
                if (NULL == vmain) {
                        fprintf(stderr, "Could not open \'%s\' for writing\n", fname_string.c_str());
                        perror("Err from O/S:");
                        exit(-1);
                }
        }
 
        fprintf(vmain, "/////////////////////////////////////////////////////////////////////////////\n");
        fprintf(vmain, "//\n");
        fprintf(vmain, "// Filename:    %sfftmain.v\n", (inverse)?"i":"");
        fprintf(vmain, "//\n");
        fprintf(vmain, "// Project:     %s\n", prjname);
        fprintf(vmain, "//\n");
        fprintf(vmain, "// Purpose:     This is the main module in the Doubletime FPGA FFT project.\n");
        fprintf(vmain, "//              As such, all other modules are subordinate to this one.\n");
        fprintf(vmain, "//              (I have been reading too much legalese this week ...)\n");
        fprintf(vmain, "//              This module accomplish a fixed size Complex FFT on %d data\n", fftsize);
        fprintf(vmain, "//              points.  The FFT is fully pipelined, and accepts as inputs\n");
        fprintf(vmain, "//              two complex two\'s complement samples per clock.\n");
        fprintf(vmain, "//\n");
        fprintf(vmain, "// Parameters:\n");
        fprintf(vmain, "//      i_clk\tThe clock.  All operations are synchronous with this clock.\n");
        fprintf(vmain, "//\ti_rst\tSynchronous reset, active high.  Setting this line will\n");
        fprintf(vmain, "//\t\t\tforce the reset of all of the internals to this routine.\n");
        fprintf(vmain, "//\t\t\tFurther, following a reset, the o_sync line will go\n");
        fprintf(vmain, "//\t\t\thigh the same time the first output sample is valid.\n");
        fprintf(vmain, "//      i_ce\tA clock enable line.  If this line is set, this module\n");
        fprintf(vmain, "//\t\t\twill accept two complex values as inputs, and produce\n");
        fprintf(vmain, "//\t\t\ttwo (possibly empty) complex values as outputs.\n");
        fprintf(vmain, "//\t\ti_left\tThe first of two complex input samples.  This value\n");
        fprintf(vmain, "//\t\t\tis split into two two\'s complement numbers, of \n");
        fprintf(vmain, "//\t\t\t%d bits each, with the real portion in the high\n", nbitsin);
        fprintf(vmain, "//\t\t\torder bits, and the imaginary portion taking the\n");
        fprintf(vmain, "//\t\t\tbottom %d bits.\n", nbitsin);
        fprintf(vmain, "//\t\ti_right\tThis is the same thing as i_left, only this is the\n");
        fprintf(vmain, "//\t\t\tsecond of two such samples.  Hence, i_left would\n");
        fprintf(vmain, "//\t\t\tcontain input sample zero, i_right would contain\n");
        fprintf(vmain, "//\t\t\tsample one.  On the next clock i_left would contain\n");
        fprintf(vmain, "//\t\t\tinput sample two, i_right number three and so forth.\n");
        fprintf(vmain, "//\t\to_left\tThe first of two output samples, of the same\n");
        fprintf(vmain, "//\t\t\tformat as i_left, only having %d bits for each of\n", nbitsout);
        fprintf(vmain, "//\t\t\tthe real and imaginary components, leading to %d\n", nbitsout*2);
        fprintf(vmain, "//\t\t\tbits total.\n");
        fprintf(vmain, "//\t\to_right\tThe second of two output samples produced each clock.\n");
        fprintf(vmain, "//\t\t\tThis has the same format as o_left.\n");
        fprintf(vmain, "//\t\to_sync\tA one bit output indicating the first valid sample\n");
        fprintf(vmain, "//\t\t\tproduced by this FFT following a reset.  Ever after,\n");
        fprintf(vmain, "//\t\t\tthis will indicate the first sample of an FFT frame.\n");
        fprintf(vmain, "//\n");
        fprintf(vmain, "// Arguments:\tThis file was computer generated using the\n");
        fprintf(vmain, "//\t\tfollowing command line:\n");
        fprintf(vmain, "//\n");
        fprintf(vmain, "//\t\t%% %s\n", cmdline.c_str());
        fprintf(vmain, "//\n");
        fprintf(vmain, "%s", creator);
        fprintf(vmain, "//\n");
        fprintf(vmain, "%s", cpyleft);
 
 
        fprintf(vmain, "//\n");
        fprintf(vmain, "//\n");
        fprintf(vmain, "module %sfftmain(i_clk, i_rst, i_ce,\n", (inverse)?"i":"");
        fprintf(vmain, "\t\ti_left, i_right,\n");
        fprintf(vmain, "\t\to_left, o_right, o_sync);\n");
        fprintf(vmain, "\tparameter\tIWIDTH=%d, OWIDTH=%d, LGWIDTH=%d;\n", nbitsin, nbitsout, lgsize);
        assert(lgsize > 0);
        fprintf(vmain, "\tinput\t\ti_clk, i_rst, i_ce;\n");
        fprintf(vmain, "\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n");
        fprintf(vmain, "\toutput\treg\t[(2*OWIDTH-1):0]\to_left, o_right;\n");
        fprintf(vmain, "\toutput\treg\t\t\to_sync;\n");
        fprintf(vmain, "\n\n");
 
        fprintf(vmain, "\t// Outputs of the FFT, ready for bit reversal.\n");
        fprintf(vmain, "\twire\t[(2*OWIDTH-1):0]\tbr_left, br_right;\n");
        fprintf(vmain, "\n\n");
 
        int     tmp_size = fftsize, lgtmp = lgsize;
        if (fftsize == 2) {
                if (bitreverse) {
                        fprintf(vmain, "\treg\tbr_start;\n");
                        fprintf(vmain, "\talways @(posedge i_clk)\n");
                        fprintf(vmain, "\t\tif (i_rst)\n");
                        fprintf(vmain, "\t\t\tbr_start <= 1'b0;\n");
                        fprintf(vmain, "\t\telse if (i_ce)\n");
                        fprintf(vmain, "\t\t\tbr_start <= 1'b1;\n");
                }
                fprintf(vmain, "\n\n");
                fprintf(vmain, "\tdblstage\t#(IWIDTH)\tstage_2(i_clk, i_rst, i_ce,\n");
                fprintf(vmain, "\t\t\t(~i_rst), i_left, i_right, br_left, br_right);\n");
                fprintf(vmain, "\n\n");
        } else {
                int     nbits = nbitsin, dropbit=0;
                // Always do a first stage
                fprintf(vmain, "\n\n");
                fprintf(vmain, "\twire\t\tw_s%d, w_os%d;\n", fftsize, fftsize);
                fprintf(vmain, "\twire\t[(2*IWIDTH+1):0]\tw_e%d, w_o%d;\n", fftsize, fftsize);
                fprintf(vmain, "\t%sfftstage_e%d\t#(IWIDTH,IWIDTH+%d,IWIDTH+1,%d,%d,%d,0)\tstage_e%d(i_clk, i_rst, i_ce,\n",
                        (inverse)?"i":"", fftsize,
                        xtracbits,
                        lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
                        fftsize);
                fprintf(vmain, "\t\t\t(~i_rst), i_left, w_e%d, w_s%d);\n", fftsize, fftsize);
                fprintf(vmain, "\t%sfftstage_o%d\t#(IWIDTH,IWIDTH+%d,IWIDTH+1,%d,%d,%d,0)\tstage_o%d(i_clk, i_rst, i_ce,\n",
                        (inverse)?"i":"", fftsize,
                        xtracbits,
                        lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
                        fftsize);
                fprintf(vmain, "\t\t\t(~i_rst), i_right, w_o%d, w_os%d);\n", fftsize, fftsize);
                fprintf(vmain, "\n\n");
 
                {
                        std::string     fname;
                        char    numstr[12];
 
                        fname = coredir + "/";
                        if (inverse) fname += "i";
                        fname += "fftstage_e";
                        sprintf(numstr, "%d", fftsize);
                        fname += numstr;
                        fname += ".v";
                        build_stage(fname.c_str(), fftsize/2, 0, nbits, inverse, xtracbits);     // Even stage
 
                        fname = coredir + "/";
                        if (inverse) fname += "i";
                        fname += "fftstage_o";
                        sprintf(numstr, "%d", fftsize);
                        fname += numstr;
                        fname += ".v";
                        build_stage(fname.c_str(), fftsize/2, 1, nbits, inverse, xtracbits);    // Odd  stage
                }
 
                nbits += 1;     // New number of input bits
                tmp_size >>= 1; lgtmp--;
                dropbit = 0;
                fprintf(vmain, "\n\n");
                while(tmp_size >= 8) {
                        int     obits = nbits+((dropbit)?0:1);
 
                        if ((maxbitsout > 0)&&(obits > maxbitsout))
                                obits = maxbitsout;
 
                        fprintf(vmain, "\twire\t\tw_s%d, w_os%d;\n", tmp_size, tmp_size);
                        fprintf(vmain, "\twire\t[%d:0]\tw_e%d, w_o%d;\n", 2*obits-1, tmp_size, tmp_size);
                        fprintf(vmain, "\t%sfftstage_e%d\t#(%d,%d,%d,%d,%d,%d,%d)\tstage_e%d(i_clk, i_rst, i_ce,\n",
                                (inverse)?"i":"", tmp_size,
                                nbits, nbits+xtracbits, obits,
                                lgsize, lgtmp-2, lgdelay(nbits,xtracbits), (dropbit)?0:0,
                                tmp_size);
                        fprintf(vmain, "\t\t\t\t\t\tw_s%d, w_e%d, w_e%d, w_s%d);\n", tmp_size<<1, tmp_size<<1, tmp_size, tmp_size);
                        fprintf(vmain, "\t%sfftstage_o%d\t#(%d,%d,%d,%d,%d,%d,%d)\tstage_o%d(i_clk, i_rst, i_ce,\n",
                                (inverse)?"i":"", tmp_size,
                                nbits, nbits+xtracbits, obits,
                                lgsize, lgtmp-2, lgdelay(nbits,xtracbits), (dropbit)?0:0,
                                tmp_size);
                        fprintf(vmain, "\t\t\t\t\t\tw_s%d, w_o%d, w_o%d, w_os%d);\n", tmp_size<<1, tmp_size<<1, tmp_size, tmp_size);
                        fprintf(vmain, "\n\n");
 
                        {
                                std::string     fname;
                                char            numstr[12];
 
                                fname = coredir + "/";
                                if (inverse) fname += "i";
                                fname += "fftstage_e";
                                sprintf(numstr, "%d", tmp_size);
                                fname += numstr;
                                fname += ".v";
                                build_stage(fname.c_str(), tmp_size/2, 0, nbits, inverse, xtracbits);    // Even stage
 
                                fname = coredir + "/";
                                if (inverse) fname += "i";
                                fname += "fftstage_o";
                                sprintf(numstr, "%d", tmp_size);
                                fname += numstr;
                                fname += ".v";
                                build_stage(fname.c_str(), tmp_size/2, 1, nbits, inverse, xtracbits);   // Odd  stage
                        }
 
 
                        dropbit ^= 1;
                        nbits = obits;
                        tmp_size >>= 1; lgtmp--;
                }
 
                if (tmp_size == 4) {
                        int     obits = nbits+((dropbit)?0:1);
 
                        if ((maxbitsout > 0)&&(obits > maxbitsout))
                                obits = maxbitsout;
 
                        fprintf(vmain, "\twire\t\tw_s4, w_os4;\n");
                        fprintf(vmain, "\twire\t[%d:0]\tw_e4, w_o4;\n", 2*obits-1);
                        fprintf(vmain, "\tqtrstage\t#(%d,%d,%d,0,%d,%d)\tstage_e4(i_clk, i_rst, i_ce,\n",
                                nbits, obits, lgsize, (inverse)?1:0, (dropbit)?0:0);
                        fprintf(vmain, "\t\t\t\t\t\tw_s8, w_e8, w_e4, w_s4);\n");
                        fprintf(vmain, "\tqtrstage\t#(%d,%d,%d,1,%d,%d)\tstage_o4(i_clk, i_rst, i_ce,\n",
                                nbits, obits, lgsize, (inverse)?1:0, (dropbit)?0:0);
                        fprintf(vmain, "\t\t\t\t\t\tw_s8, w_o8, w_o4, w_os4);\n");
                        dropbit ^= 1;
                        nbits = obits;
                        tmp_size >>= 1; lgtmp--;
                }
 
                {
                        int obits = nbits+((dropbit)?0:1);
                        if (obits > nbitsout)
                                obits = nbitsout;
                        if ((maxbitsout>0)&&(obits > maxbitsout))
                                obits = maxbitsout;
                        fprintf(vmain, "\twire\t\tw_s2;\n");
                        fprintf(vmain, "\twire\t[%d:0]\tw_e2, w_o2;\n", 2*obits-1);
                        fprintf(vmain, "\tdblstage\t#(%d,%d,%d)\tstage_2(i_clk, i_rst, i_ce,\n", nbits, obits,(dropbit)?0:1);
                        fprintf(vmain, "\t\t\t\t\tw_s4, w_e4, w_o4, w_e2, w_o2, w_s2);\n");
 
                        fprintf(vmain, "\n\n");
                        nbits = obits;
                }
 
                fprintf(vmain, "\t// Prepare for a (potential) bit-reverse stage.\n");
                fprintf(vmain, "\tassign\tbr_left  = w_e2;\n");
                fprintf(vmain, "\tassign\tbr_right = w_o2;\n");
                fprintf(vmain, "\n");
                if (bitreverse) {
                        fprintf(vmain, "\twire\tbr_start;\n");
                        fprintf(vmain, "\treg\tr_br_started;\n");
                        fprintf(vmain, "\t// A delay of one clock here is perfect, as it matches the delay in\n");
                        fprintf(vmain, "\t// our dblstage.\n");
                        fprintf(vmain, "\talways @(posedge i_clk)\n");
                        fprintf(vmain, "\t\tif (i_rst)\n");
                        fprintf(vmain, "\t\t\tr_br_started <= 1'b0;\n");
                        fprintf(vmain, "\t\telse\n");
                        fprintf(vmain, "\t\t\tr_br_started <= r_br_started || w_s4;\n");
                        fprintf(vmain, "\tassign\tbr_start = r_br_started;\n");
                }
        }
 
        fprintf(vmain, "\n");
        fprintf(vmain, "\t// Now for the bit-reversal stage.\n");
        fprintf(vmain, "\twire\tbr_sync;\n");
        fprintf(vmain, "\twire\t[(2*OWIDTH-1):0]\tbr_o_left, br_o_right;\n");
        if (bitreverse) {
                fprintf(vmain, "\tdblreverse\t#(%d,%d)\trevstage(i_clk, i_rst,\n", lgsize, nbitsout);
                fprintf(vmain, "\t\t\t(i_ce & br_start), br_left, br_right,\n");
                fprintf(vmain, "\t\t\tbr_o_left, br_o_right, br_sync);\n");
        } else {
                fprintf(vmain, "\tassign\tbr_o_left  = br_left;\n");
                fprintf(vmain, "\tassign\tbr_o_right = br_right;\n");
                fprintf(vmain, "\tassign\tbr_sync    = w_s2;\n");
        }
 
        fprintf(vmain, "\n\n");
        fprintf(vmain, "\t// Last clock: Register our outputs, we\'re done.\n");
        fprintf(vmain, "\talways @(posedge i_clk)\n");
        fprintf(vmain, "\t\tbegin\n");
        fprintf(vmain, "\t\t\to_left  <= br_o_left;\n");
        fprintf(vmain, "\t\t\to_right <= br_o_right;\n");
        fprintf(vmain, "\t\t\to_sync  <= br_sync;\n");
        fprintf(vmain, "\t\tend\n");
        fprintf(vmain, "\n\n");
        fprintf(vmain, "endmodule\n");
        fclose(vmain);
 
        {
                std::string     fname;
 
                fname = coredir + "/butterfly.v";
                build_butterfly(fname.c_str(), xtracbits);
 
                fname = coredir + "/shiftaddmpy.v";
                build_multiply(fname.c_str());
 
                fname = coredir + "/qtrstage.v";
                build_quarters(fname.c_str());
 
                fname = coredir + "/dblstage.v";
                build_dblstage(fname.c_str());
 
                if (bitreverse) {
                        fname = coredir + "/dblreverse.v";
                        build_dblreverse(fname.c_str());
                }
        }
}
 
 

Line No.	Rev	Author	Line
1	16	dgisselq	`/////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: fftgen.v`
4			`//`
5			`// Project: A Doubletime Pipelined FFT`
6			`//`
7			`// Purpose: This is the core generator for the project. Every part`
8			`// and piece of this project begins and ends in this program.`
9			`// Once built, this program will build an FFT (or IFFT) core`
10			`// of arbitrary width, precision, etc., that will run at`
11			`// two samples per clock. (Incidentally, I didn't pick two`
12			`// samples per clock because it was easier, but rather because`
13			`// there weren't any two-sample per clock FFT's posted on`
14			`// opencores.com. Further, FFT's running at one sample per`
15			`// clock aren't that hard to find.)`
16			`//`
17			`// You can find the documentation for this program in two places.`
18			`// One is in the usage() function below. The second is in the`
19			`// 'doc'uments directory that comes with this package,`
20			`// specifically in the spec.pdf file. If it's not there, type`
21			`// make in the documents directory to build it.`
22			`//`
23			`// Creator: Dan Gisselquist, Ph.D.`
24			`// Gisselquist Tecnology, LLC`
25			`//`
26			`///////////////////////////////////////////////////////////////////////////`
27			`//`
28			`// Copyright (C) 2015, Gisselquist Technology, LLC`
29			`//`
30			`// This program is free software (firmware): you can redistribute it and/or`
31			`// modify it under the terms of the GNU General Public License as published`
32			`// by the Free Software Foundation, either version 3 of the License, or (at`
33			`// your option) any later version.`
34			`//`
35			`// This program is distributed in the hope that it will be useful, but WITHOUT`
36			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
37			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
38			`// for more details.`
39			`//`
40			`// You should have received a copy of the GNU General Public License along`
41			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
42			`// target there if the PDF file isn't present.) If not, see`
43			`// <http://www.gnu.org/licenses/> for a copy.`
44			`//`
45			`// License: GPL, v3, as defined and found on www.gnu.org,`
46			`// http://www.gnu.org/licenses/gpl.html`
47			`//`
48			`//`
49			`///////////////////////////////////////////////////////////////////////////`
50			`//`
51			`//`
52	2	dgisselq	`#include <stdio.h>`
53			`#include <stdlib.h>`
54			`#include <unistd.h>`
55			`#include <sys/stat.h>`
56			`#include <string.h>`
57	14	dgisselq	`#include <string>`
58	2	dgisselq	`#include <math.h>`
59			`#include <ctype.h>`
60			`#include <assert.h>`
61
62			`#define COREDIR "fft-core"`
63
64			`const char cpyleft[] =`
65			`"///////////////////////////////////////////////////////////////////////////\n"`
66			`"//\n"`
67			`"// Copyright (C) 2015, Gisselquist Technology, LLC\n"`
68			`"//\n"`
69			`"// This program is free software (firmware): you can redistribute it and/or\n"`
70			`"// modify it under the terms of the GNU General Public License as published\n"`
71			`"// by the Free Software Foundation, either version 3 of the License, or (at\n"`
72			`"// your option) any later version.\n"`
73			`"//\n"`
74			`"// This program is distributed in the hope that it will be useful, but WITHOUT\n"`
75			`"// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n"`
76			`"// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\n"`
77			`"// for more details.\n"`
78			`"//\n"`
79			`"// You should have received a copy of the GNU General Public License along\n"`
80	5	dgisselq	`"// with this program. (It's in the $(ROOT)/doc directory, run make with no\n"`
81			`"// target there if the PDF file isn\'t present.) If not, see\n"`
82			`"// <http://www.gnu.org/licenses/> for a copy.\n"`
83			`"//\n"`
84	2	dgisselq	`"// License: GPL, v3, as defined and found on www.gnu.org,\n"`
85			`"// http://www.gnu.org/licenses/gpl.html\n"`
86			`"//\n"`
87			`"//\n"`
88			`"///////////////////////////////////////////////////////////////////////////\n";`
89	14	dgisselq	`const char prjname[] = "A Doubletime Pipelined FFT";`
90	2	dgisselq	`const char creator[] = "// Creator: Dan Gisselquist, Ph.D.\n"`
91			`"// Gisselquist Tecnology, LLC\n";`
92
93			`int lgval(int vl) {`
94			`int lg;`
95
96			`for(lg=1; (1<<lg) < vl; lg++)`
97			`;`
98			`return lg;`
99			`}`
100
101			`int nextlg(int vl) {`
102			`int r;`
103
104			`for(r=1; r<vl; r<<=1)`
105			`;`
106			`return r;`
107			`}`
108
109	14	dgisselq	`int bflydelay(int nbits, int xtra) {`
110	2	dgisselq	`int cbits = nbits + xtra;`
111	14	dgisselq	`int delay;`
112	2	dgisselq	`if (nbits+1<cbits)`
113	5	dgisselq	`delay = nbits+4;`
114	2	dgisselq	`else`
115	5	dgisselq	`delay = cbits+3;`
116	14	dgisselq	`return delay;`
117	2	dgisselq	`}`
118
119	14	dgisselq	`int lgdelay(int nbits, int xtra) {`
120			`// The butterfly code needs to compare a valid address, of this`
121			`// many bits, with an address two greater. This guarantees we`
122			`// have enough bits for that comparison. We'll also end up with`
123			`// more storage space to look for these values, but without a`
124			`// redesign that's just what we'll deal with.`
125			`return lgval(bflydelay(nbits, xtra)+3);`
126			`}`
127
128	2	dgisselq	`void build_quarters(const char *fname) {`
129			`FILE *fp = fopen(fname, "w");`
130			`if (NULL == fp) {`
131			`fprintf(stderr, "Could not open \'%s\' for writing\n", fname);`
132			`perror("O/S Err was:");`
133			`return;`
134			`}`
135
136			`fprintf(fp,`
137			`"///////////////////////////////////////////////////////////////////////////\n"`
138			`"//\n"`
139			`"// Filename: qtrstage.v\n"`
140			`"// \n"`
141			`"// Project: %s\n"`
142			`"//\n"`
143	5	dgisselq	`"// Purpose: This file encapsulates the 4 point stage of a decimation in\n"`
144			`"// frequency FFT. This particular implementation is optimized\n"`
145			`"// so that all of the multiplies are accomplished by additions\n"`
146			`"// and multiplexers only.\n"`
147			`"//\n"`
148	2	dgisselq	`"//\n%s"`
149			`"//\n",`
150			`prjname, creator);`
151			`fprintf(fp, "%s", cpyleft);`
152
153			`fprintf(fp,`
154			`"module\tqtrstage(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync);\n"`
155	5	dgisselq	`"\tparameter IWIDTH=16, OWIDTH=IWIDTH+1;\n"`
156			`"\t// Parameters specific to the core that should be changed when this\n"`
157			`"\t// core is built ... Note that the minimum LGSPAN is 2. Smaller \n"`
158			`"\t// spans must use the fftdoubles stage.\n"`
159	15	dgisselq	`"\tparameter\tLGWIDTH=8, ODD=0, INVERSE=0,SHIFT=0,ROUND=1;\n"`
160	5	dgisselq	`"\tinput\t i_clk, i_rst, i_ce, i_sync;\n"`
161			`"\tinput\t [(2*IWIDTH-1):0] i_data;\n"`
162			`"\toutput\treg [(2*OWIDTH-1):0] o_data;\n"`
163			`"\toutput\treg o_sync;\n"`
164	14	dgisselq	`"\t\n");`
165			`fprintf(fp,`
166	5	dgisselq	`"\treg\t wait_for_sync;\n"`
167			`"\treg\t[2:0] pipeline;\n"`
168	2	dgisselq	`"\n"`
169	5	dgisselq	`"\treg\t[(IWIDTH):0] sum_r, sum_i, diff_r, diff_i;\n"`
170	14	dgisselq	`"\twire\t[(IWIDTH):0] n_diff_r, n_diff_i;\n"`
171			`"\tassign n_diff_r = -diff_r;\n"`
172	5	dgisselq	`"\tassign n_diff_i = -diff_i;\n"`
173	2	dgisselq	`"\n"`
174	5	dgisselq	`"\treg\t[(2*OWIDTH-1):0] ob_a;\n"`
175			`"\twire\t[(2*OWIDTH-1):0] ob_b;\n"`
176			`"\treg\t[(OWIDTH-1):0] ob_b_r, ob_b_i;\n"`
177			`"\tassign ob_b = { ob_b_r, ob_b_i };\n"`
178	2	dgisselq	`"\n"`
179	5	dgisselq	`"\treg\t[(LGWIDTH-1):0] iaddr;\n"`
180			`"\treg\t[(2*IWIDTH-1):0] imem;\n"`
181	2	dgisselq	`"\n"`
182	5	dgisselq	`"\twire\tsigned\t[(IWIDTH-1):0]\timem_r, imem_i;\n"`
183			`"\tassign\timem_r = imem[(2*IWIDTH-1):(IWIDTH)];\n"`
184			`"\tassign\timem_i = imem[(IWIDTH-1):0];\n"`
185	2	dgisselq	`"\n"`
186	5	dgisselq	`"\twire\tsigned\t[(IWIDTH-1):0]\ti_data_r, i_data_i;\n"`
187			`"\tassign\ti_data_r = i_data[(2*IWIDTH-1):(IWIDTH)];\n"`
188			`"\tassign\ti_data_i = i_data[(IWIDTH-1):0];\n"`
189	2	dgisselq	`"\n"`
190	5	dgisselq	`"\treg [(2*OWIDTH-1):0] omem;\n"`
191	14	dgisselq	`"\n");`
192			`fprintf(fp,`
193	5	dgisselq	`"\twire [(IWIDTH-1):0] rnd;\n"`
194	9	dgisselq	`"\tgenerate\n"`
195			`"\tif ((ROUND)&&((IWIDTH+1-OWIDTH-SHIFT)>0))\n"`
196			`"\t\tassign rnd = { {(IWIDTH-1){1'b0}}, 1'b1 };\n"`
197			`"\telse\n"`
198			`"\t\tassign rnd = { {(IWIDTH){1'b0}}};\n"`
199			`"\tendgenerate\n"`
200	2	dgisselq	`"\n"`
201	5	dgisselq	`"\talways @(posedge i_clk)\n"`
202			`"\t\tif (i_rst)\n"`
203			`"\t\tbegin\n"`
204			`"\t\t\twait_for_sync <= 1'b1;\n"`
205			`"\t\t\tiaddr <= 0;\n"`
206			`"\t\t\tpipeline <= 3'b000;\n"`
207			`"\t\tend\n"`
208			`"\t\telse if ((i_ce)&&((~wait_for_sync)\|\|(i_sync)))\n"`
209			`"\t\tbegin\n"`
210			`"\t\t\t// Always\n"`
211			`"\t\t\timem <= i_data;\n"`
212			`"\t\t\tiaddr <= iaddr + 1;\n"`
213			`"\t\t\twait_for_sync <= 1'b0;\n"`
214	2	dgisselq	`"\n"`
215	5	dgisselq	`"\t\t\t// In sequence, clock = 0\n"`
216			`"\t\t\tif (iaddr[0])\n"`
217			`"\t\t\tbegin\n"`
218			`"\t\t\t\tsum_r <= imem_r + i_data_r + rnd;\n"`
219			`"\t\t\t\tsum_i <= imem_i + i_data_i + rnd;\n"`
220			`"\t\t\t\tdiff_r <= imem_r - i_data_r + rnd;\n"`
221			`"\t\t\t\tdiff_i <= imem_i - i_data_i + rnd;\n"`
222	2	dgisselq	`"\n"`
223	5	dgisselq	`"\t\t\t\tpipeline[2:0] <= { pipeline[1:0], 1'b1 };\n"`
224			`"\t\t\tend else\n"`
225			`"\t\t\t\tpipeline[2:0] <= { pipeline[1:0], 1'b0 };\n"`
226	2	dgisselq	`"\n"`
227	5	dgisselq	`"\t\t\t// In sequence, clock = 1\n"`
228			`"\t\t\tif (pipeline[1])\n"`
229			`"\t\t\tbegin\n"`
230	9	dgisselq	`"\t\t\t\tob_a <= { sum_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)],\n"`
231			`"\t\t\t\t\t\tsum_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)] };\n"`
232	5	dgisselq	`"\t\t\t\t// on Even, W = e^{-j2pi 1/4 0} = 1\n"`
233	9	dgisselq	`"\t\t\t\tif (ODD == 0)\n"`
234	5	dgisselq	`"\t\t\t\tbegin\n"`
235	2	dgisselq	`"\t\t\t\t\tob_b_r <= diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
236			`"\t\t\t\t\tob_b_i <= diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
237	9	dgisselq	`// "\t\t\t\t\tob_b_r <= { (OWIDTH) {1'b0} };\n"`
238			`// "\t\t\t\t\tob_b_i <= { (OWIDTH) {1'b0} };\n"`
239	14	dgisselq	`"\t\t\t\tend else if (INVERSE==0) begin\n"`
240	2	dgisselq	`"\t\t\t\t\t// on Odd, W = e^{-j2pi 1/4} = -j\n"`
241			`"\t\t\t\t\tob_b_r <= diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
242	14	dgisselq	`"\t\t\t\t\tob_b_i <= n_diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
243	9	dgisselq	`// "\t\t\t\t\tob_b_r <= { (OWIDTH) {1'b0} };\n"`
244			`// "\t\t\t\t\tob_b_i <= { (OWIDTH) {1'b0} };\n"`
245	5	dgisselq	`"\t\t\t\tend else begin\n"`
246	2	dgisselq	`"\t\t\t\t\t// on Odd, W = e^{j2pi 1/4} = j\n"`
247			`"\t\t\t\t\tob_b_r <= n_diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
248			`"\t\t\t\t\tob_b_i <= diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
249	9	dgisselq	`// "\t\t\t\t\tob_b_r <= { (OWIDTH) {1'b0} };\n"`
250			`// "\t\t\t\t\tob_b_i <= { (OWIDTH) {1'b0} };\n"`
251
252	5	dgisselq	`"\t\t\t\tend\n"`
253			`"\t\t\t\t// (wire) ob_b <= { ob_b_r, ob_b_i };\n"`
254			`"\t\t\tend\n"`
255			`"\t\t\t// In sequence, clock = 2\n"`
256			`"\t\t\tif (pipeline[2])\n"`
257			`"\t\t\tbegin\n"`
258			`"\t\t\t\tomem <= ob_b;\n"`
259			`"\t\t\t\to_data <= ob_a;\n"`
260			`"\t\t\tend else\n"`
261			`"\t\t\t\to_data <= omem;\n"`
262	6	dgisselq	`"\t\t\t// Don\'t forget in the sync check that we are running\n"`
263			`"\t\t\t// at two clocks per sample. Thus we need to\n"`
264			`"\t\t\t// produce a sync every 2^(LGWIDTH-1) clocks.\n"`
265			`"\t\t\to_sync <= &(~iaddr[(LGWIDTH-2):3]) && (iaddr[2:0] == 3'b100);\n"`
266	5	dgisselq	`"\t\tend\n"`
267	2	dgisselq	`"endmodule\n");`
268			`}`
269
270			`void build_dblstage(const char *fname) {`
271			`FILE *fp = fopen(fname, "w");`
272			`if (NULL == fp) {`
273			`fprintf(stderr, "Could not open \'%s\' for writing\n", fname);`
274			`perror("O/S Err was:");`
275			`return;`
276			`}`
277
278			`fprintf(fp,`
279			`"///////////////////////////////////////////////////////////////////////////\n"`
280			`"//\n"`
281			`"// Filename: dblstage.v\n"`
282			`"//\n"`
283			`"// Project: %s\n"`
284			`"//\n"`
285			`"// Purpose: This is part of an FPGA implementation that will process\n"`
286	5	dgisselq	`"// the final stage of a decimate-in-frequency FFT, running\n"`
287			`"// through the data at two samples per clock. If you notice\n"`
288			`"// from the derivation of an FFT, the only time both even and\n"`
289			`"// odd samples are used at the same time is in this stage.\n"`
290			`"// Therefore, other than this stage and these twiddles, all of\n"`
291			`"// the other stages can run two stages at a time at one sample\n"`
292			`"// per clock.\n"`
293	2	dgisselq	`"//\n"`
294			`"// In this implementation, the output is valid one clock after\n"`
295			`"// the input is valid. The output also accumulates one bit\n"`
296			`"// above and beyond the number of bits in the input.\n"`
297			`"// \n"`
298			`"// i_clk A system clock\n"`
299	6	dgisselq	`"// i_rst A synchronous reset\n"`
300	2	dgisselq	`"// i_ce Circuit enable--nothing happens unless this line is high\n"`
301	6	dgisselq	`"// i_sync A synchronization signal, high once per FFT at the start\n"`
302	2	dgisselq	`"// i_left The first (even) complex sample input. The higher order\n"`
303			`"// bits contain the real portion, low order bits the\n"`
304			`"// imaginary portion, all in two\'s complement.\n"`
305			`"// i_right The next (odd) complex sample input, same format as\n"`
306			`"// i_left.\n"`
307			`"// o_left The first (even) complex output.\n"`
308			`"// o_right The next (odd) complex output.\n"`
309	6	dgisselq	`"// o_sync Output synchronization signal.\n"`
310	2	dgisselq	`"//\n%s"`
311			`"//\n", prjname, creator);`
312
313			`fprintf(fp, "%s", cpyleft);`
314			`fprintf(fp,`
315	9	dgisselq	`"module\tdblstage(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync);\n"`
316	15	dgisselq	`"\tparameter\tIWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;\n" // ROUND=1`
317	6	dgisselq	`"\tinput\t\ti_clk, i_rst, i_ce, i_sync;\n"`
318	5	dgisselq	`"\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"`
319	6	dgisselq	`"\toutput\twire\t[(2*OWIDTH-1):0]\to_left, o_right;\n"`
320			`"\toutput\treg\t\t\to_sync;\n"`
321	2	dgisselq	`"\n"`
322	5	dgisselq	`"\twire\tsigned\t[(IWIDTH-1):0]\ti_in_0r, i_in_0i, i_in_1r, i_in_1i;\n"`
323			`"\tassign\ti_in_0r = i_left[(2*IWIDTH-1):(IWIDTH)]; \n"`
324			`"\tassign\ti_in_0i = i_left[(IWIDTH-1):0]; \n"`
325			`"\tassign\ti_in_1r = i_right[(2*IWIDTH-1):(IWIDTH)]; \n"`
326			`"\tassign\ti_in_1i = i_right[(IWIDTH-1):0]; \n"`
327			`"\twire\t[(OWIDTH-1):0]\t\to_out_0r, o_out_0i,\n"`
328			`"\t\t\t\t\to_out_1r, o_out_1i;\n"`
329	2	dgisselq	`"\n"`
330	15	dgisselq	`"\n"`
331			`// "\t// Handle a potential rounding situation, when IWIDTH=OWIDTH.\n"`
332			`//"\n"`
333			`// "\twire\tsigned\t[(IWIDTH-1):0]\trnd;\n"`
334			`//"\n"`
335			`// "\tgenerate\n"`
336			`// "\tif ((ROUND==1)&&(IWIDTH==OWIDTH))\n"`
337			`// "\t\tassign rnd = { {(IWIDTH-1){1'b0}}, 1'b1 };\n"`
338			`// "\telse\n"`
339			`// "\t\tassign rnd = { {(IWIDTH){1'b0}} };\n"`
340			`// "\tendgenerate\n"`
341			`"\n"`
342	5	dgisselq	`"\t// Don't forget that we accumulate a bit by adding two values\n"`
343			`"\t// together. Therefore our intermediate value must have one more\n"`
344			`"\t// bit than the two originals.\n"`
345			`"\treg\t[IWIDTH:0]\tout_0r, out_0i, out_1r, out_1i;\n"`
346	2	dgisselq	`"\n"`
347	6	dgisselq	`"\treg\twait_for_sync;\n"`
348			`"\n"`
349	5	dgisselq	`"\talways @(posedge i_clk)\n"`
350	6	dgisselq	`"\t\tif (i_rst)\n"`
351			`"\t\t\twait_for_sync <= 1'b1;\n"`
352			`"\t\telse if ((i_ce)&&((~wait_for_sync)\|\|(i_sync)))\n"`
353	5	dgisselq	`"\t\tbegin\n"`
354	6	dgisselq	`"\t\t\twait_for_sync <= 1'b0;\n"`
355			`"\t\t\t//\n"`
356	15	dgisselq	`"\t\t\tout_0r <= i_in_0r + i_in_1r;\n" // + rnd`
357			`"\t\t\tout_0i <= i_in_0i + i_in_1i;\n" // + rnd`
358	5	dgisselq	`"\t\t\t//\n"`
359	15	dgisselq	`"\t\t\tout_1r <= i_in_0r - i_in_1r;\n" // + rnd`
360			`"\t\t\tout_1i <= i_in_0i - i_in_1i;\n" // + rnd`
361	6	dgisselq	`"\t\t\t//\n"`
362			`"\t\t\to_sync <= i_sync;\n"`
363	5	dgisselq	`"\t\tend\n"`
364	2	dgisselq	`"\n"`
365	5	dgisselq	`"\t// Now, if the master control program doesn't want to keep all of\n"`
366			`"\t// our bits, we can shift down to OWIDTH bits here.\n"`
367			`"\tassign\to_out_0r = out_0r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
368			`"\tassign\to_out_0i = out_0i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
369			`"\tassign\to_out_1r = out_1r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
370			`"\tassign\to_out_1i = out_1i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"`
371	2	dgisselq	`"\n"`
372	5	dgisselq	`"\tassign\to_left = { o_out_0r, o_out_0i };\n"`
373			`"\tassign\to_right = { o_out_1r, o_out_1i };\n"`
374	2	dgisselq	`"\n"`
375			`"endmodule\n");`
376			`fclose(fp);`
377			`}`
378
379			`void build_multiply(const char *fname) {`
380			`FILE *fp = fopen(fname, "w");`
381			`if (NULL == fp) {`
382			`fprintf(stderr, "Could not open \'%s\' for writing\n", fname);`
383			`perror("O/S Err was:");`
384			`return;`
385			`}`
386
387			`fprintf(fp,`
388			`"///////////////////////////////////////////////////////////////////////////\n"`
389			`"//\n"`
390			`"// Filename: shiftaddmpy.v\n"`
391			`"//\n"`
392			`"// Project: %s\n"`
393			`"//\n"`
394			`"// Purpose: A portable shift and add multiply.\n"`
395			`"//\n"`
396			`"// While both Xilinx and Altera will offer single clock \n"`
397			`"// multiplies, this simple approach will multiply two numbers\n"`
398			`"// on any architecture. The result maintains the full width\n"`
399			`"// of the multiply, there are no extra stuff bits, no rounding,\n"`
400			`"// no shifted bits, etc.\n"`
401			`"//\n"`
402			`"// Further, for those applications that can support it, this\n"`
403			`"// multiply is pipelined and will produce one answer per clock.\n"`
404			`"//\n"`
405			`"// For minimal processing delay, make the first parameter\n"`
406			`"// the one with the least bits, so that AWIDTH <= BWIDTH.\n"`
407			`"//\n"`
408			`"// The processing delay in this multiply is (AWIDTH+1) cycles.\n"`
409			`"// That is, if the data is present on the input at clock t=0,\n"`
410			`"// the result will be present on the output at time t=AWIDTH+1;\n"`
411			`"//\n"`
412			`"//\n%s"`
413			`"//\n", prjname, creator);`
414
415			`fprintf(fp, "%s", cpyleft);`
416			`fprintf(fp,`
417			`"module shiftaddmpy(i_clk, i_ce, i_a, i_b, o_r);\n"`
418			`"\tparameter\tAWIDTH=16,BWIDTH=AWIDTH;\n"`
419			`"\tinput\t\t\t\t\ti_clk, i_ce;\n"`
420			`"\tinput\t\t[(AWIDTH-1):0]\t\ti_a;\n"`
421			`"\tinput\t\t[(BWIDTH-1):0]\t\ti_b;\n"`
422			`"\toutput\treg\t[(AWIDTH+BWIDTH-1):0]\to_r;\n"`
423			`"\n"`
424			`"\treg\t[(AWIDTH-1):0]\tu_a;\n"`
425			`"\treg\t[(BWIDTH-1):0]\tu_b;\n"`
426			`"\treg\t\t\tsgn;\n"`
427			`"\n"`
428			`"\treg\t[(AWIDTH-2):0]\t\tr_a[0:(AWIDTH-1)];\n"`
429			`"\treg\t[(AWIDTH+BWIDTH-2):0]\tr_b[0:(AWIDTH-1)];\n"`
430			`"\treg\t\t\t\tr_s[0:(AWIDTH-1)];\n"`
431			`"\treg\t[(AWIDTH+BWIDTH-1):0]\tacc[0:(AWIDTH-1)];\n"`
432			`"\tgenvar k;\n"`
433			`"\n"`
434	5	dgisselq	`"\t// If we were forced to stay within two\'s complement arithmetic,\n"`
435			`"\t// taking the absolute value here would require an additional bit.\n"`
436			`"\t// However, because our results are now unsigned, we can stay\n"`
437			`"\t// within the number of bits given (for now).\n"`
438	2	dgisselq	`"\talways @(posedge i_clk)\n"`
439			`"\t\tif (i_ce)\n"`
440			`"\t\tbegin\n"`
441			`"\t\t\tu_a <= (i_a[AWIDTH-1])?(-i_a):(i_a);\n"`
442			`"\t\t\tu_b <= (i_b[BWIDTH-1])?(-i_b):(i_b);\n"`
443			`"\t\t\tsgn <= i_a[AWIDTH-1] ^ i_b[BWIDTH-1];\n"`
444			`"\t\tend\n"`
445			`"\n"`
446			`"\talways @(posedge i_clk)\n"`
447			`"\t\tif (i_ce)\n"`
448			`"\t\tbegin\n"`
449			`"\t\t\tacc[0] <= (u_a[0]) ? { {(AWIDTH){1'b0}}, u_b }\n"`
450			`"\t\t\t\t\t: {(AWIDTH+BWIDTH){1'b0}};\n"`
451			`"\t\t\tr_a[0] <= { u_a[(AWIDTH-1):1] };\n"`
452			`"\t\t\tr_b[0] <= { {(AWIDTH-1){1'b0}}, u_b };\n"`
453			`"\t\t\tr_s[0] <= sgn; // The final sign, needs to be preserved\n"`
454			`"\t\tend\n"`
455			`"\n"`
456			`"\tgenerate\n"`
457			`"\talways @(posedge i_clk)\n"`
458			`"\tif (i_ce)\n"`
459			`"\tbegin\n"`
460			`"\t\tfor(k=0; k<AWIDTH-1; k++)\n"`
461			`"\t\tbegin\n"`
462			`"\t\t\tacc[k+1] <= acc[k] + ((r_a[k][0]) ? {r_b[k],1'b0}:0);\n"`
463			`"\t\t\tr_a[k+1] <= { 1'b0, r_a[k][(AWIDTH-2):1] };\n"`
464			`"\t\t\tr_b[k+1] <= { r_b[k][(AWIDTH+BWIDTH-3):0], 1'b0};\n"`
465			`"\t\t\tr_s[k+1] <= r_s[k];\n"`
466			`"\t\tend\n"`
467			`"\tend\n"`
468			`"\tendgenerate\n"`
469			`"\n"`
470			`"\talways @(posedge i_clk)\n"`
471			`"\t\tif (i_ce)\n"`
472			`"\t\t\to_r <= (r_s[AWIDTH-1]) ? (-acc[AWIDTH-1]) : acc[AWIDTH-1];\n"`
473			`"\n"`
474			`"endmodule\n");`
475
476			`fclose(fp);`
477			`}`
478
479			`void build_dblreverse(const char *fname) {`
480			`FILE *fp = fopen(fname, "w");`
481			`if (NULL == fp) {`
482			`fprintf(stderr, "Could not open \'%s\' for writing\n", fname);`
483			`perror("O/S Err was:");`
484			`return;`
485			`}`
486
487			`fprintf(fp,`
488			`"///////////////////////////////////////////////////////////////////////////\n"`
489			`"//\n"`
490			`"// Filename: dblreverse.v\n"`
491			`"//\n"`
492			`"// Project: %s\n"`
493			`"//\n"`
494			`"// Purpose: This module bitreverses a pipelined FFT input. Operation is\n"`
495			`"// expected as follows:\n"`
496			`"//\n"`
497			`"// i_clk A running clock at whatever system speed is offered.\n"`
498			`"// i_rst A synchronous reset signal, that resets all internals\n"`
499			`"// i_ce If this is one, one input is consumed and an output\n"`
500			`"// is produced.\n"`

Browse

Tools

Subversion Repositories dblclockfft

[/] [dblclockfft/] [trunk/] [sw/] [fftgen.cpp] - Blame information for rev 16