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[/] [dblclockfft/] [trunk/] [sw/] [fftgen.cpp] - Blame information for rev 6

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1 2 dgisselq 
#include <stdio.h>
2 
#include <stdlib.h>
3 
#include <unistd.h>
4 
#include <sys/stat.h>
5 
#include <string.h>
6 
#include <math.h>
7 
#include <ctype.h>
8 
#include <assert.h>
9 
 
10 
#define COREDIR "fft-core"
11 
 
12 
const char      cpyleft[] =
13 
"///////////////////////////////////////////////////////////////////////////\n"
14 
"//\n"
15 
"// Copyright (C) 2015, Gisselquist Technology, LLC\n"
16 
"//\n"
17 
"// This program is free software (firmware): you can redistribute it and/or\n"
18 
"// modify it under the terms of  the GNU General Public License as published\n"
19 
"// by the Free Software Foundation, either version 3 of the License, or (at\n"
20 
"// your option) any later version.\n"
21 
"//\n"
22 
"// This program is distributed in the hope that it will be useful, but WITHOUT\n"
23 
"// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n"
24 
"// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License\n"
25 
"// for more details.\n"
26 
"//\n"
27 
"// You should have received a copy of the GNU General Public License along\n"
28 5 dgisselq 
"// with this program.  (It's in the $(ROOT)/doc directory, run make with no\n"
29 
"// target there if the PDF file isn\'t present.)  If not, see\n"
30 
"// <http://www.gnu.org/licenses/> for a copy.\n"
31 
"//\n"
32 2 dgisselq 
"// License:    GPL, v3, as defined and found on www.gnu.org,\n"
33 
"//             http://www.gnu.org/licenses/gpl.html\n"
34 
"//\n"
35 
"//\n"
36 
"///////////////////////////////////////////////////////////////////////////\n";
37 
const char      prjname[] = "A Doubletime Pipelined FFT\n";
38 
const char      creator[] =     "// Creator:    Dan Gisselquist, Ph.D.\n"
39 
                                "//             Gisselquist Tecnology, LLC\n";
40 
 
41 
int     lgval(int vl) {
42 
        int     lg;
43 
 
44 
        for(lg=1; (1<<lg) < vl; lg++)
45 
                ;
46 
        return lg;
47 
}
48 
 
49 
int     nextlg(int vl) {
50 
        int     r;
51 
 
52 
        for(r=1; r<vl; r<<=1)
53 
                ;
54 
        return r;
55 
}
56 
 
57 
int     lgdelay(int nbits, int xtra) {
58 
        int     cbits = nbits + xtra;
59 
        int     delay = nbits + 2;
60 
        if (nbits+1<cbits)
61 5 dgisselq 
                delay = nbits+4;
62 2 dgisselq 
        else
63 5 dgisselq 
                delay = cbits+3;
64 2 dgisselq 
        return lgval(delay);
65 
}
66 
 
67 
void    build_quarters(const char *fname) {
68 
        FILE    *fp = fopen(fname, "w");
69 
        if (NULL == fp) {
70 
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
71 
                perror("O/S Err was:");
72 
                return;
73 
        }
74 
 
75 
        fprintf(fp,
76 
"///////////////////////////////////////////////////////////////////////////\n"
77 
"//\n"
78 
"// Filename:   qtrstage.v\n"
79 
"//             \n"
80 
"// Project:    %s\n"
81 
"//\n"
82 5 dgisselq 
"// Purpose:    This file encapsulates the 4 point stage of a decimation in\n"
83 
"//             frequency FFT.  This particular implementation is optimized\n"
84 
"//             so that all of the multiplies are accomplished by additions\n"
85 
"//             and multiplexers only.\n"
86 
"//\n"
87 2 dgisselq 
"//\n%s"
88 
"//\n",
89 
                prjname, creator);
90 
        fprintf(fp, "%s", cpyleft);
91 
 
92 
        fprintf(fp,
93 
"module\tqtrstage(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync);\n"
94 5 dgisselq 
        "\tparameter    IWIDTH=16, OWIDTH=IWIDTH+1;\n"
95 
        "\t// Parameters specific to the core that should be changed when this\n"
96 
        "\t// core is built ... Note that the minimum LGSPAN is 2.  Smaller \n"
97 
        "\t// spans must use the fftdoubles stage.\n"
98 
        "\tparameter\tLGWIDTH=8, ODD=0, INVERSE=0,SHIFT=0;\n"
99 
        "\tinput\t                              i_clk, i_rst, i_ce, i_sync;\n"
100 
        "\tinput\t      [(2*IWIDTH-1):0]        i_data;\n"
101 
        "\toutput\treg  [(2*OWIDTH-1):0]        o_data;\n"
102 
        "\toutput\treg                          o_sync;\n"
103 
        "\t\n"
104 
        "\treg\t        wait_for_sync;\n"
105 
        "\treg\t[2:0]   pipeline;\n"
106 2 dgisselq 
"\n"
107 5 dgisselq 
        "\treg\t[(IWIDTH):0]    sum_r, sum_i, diff_r, diff_i;\n"
108 
        "\twire\t[(IWIDTH):0]   n_diff_i;\n"
109 
        "\tassign n_diff_i = -diff_i;\n"
110 2 dgisselq 
"\n"
111 5 dgisselq 
        "\treg\t[(2*OWIDTH-1):0]        ob_a;\n"
112 
        "\twire\t[(2*OWIDTH-1):0]       ob_b;\n"
113 
        "\treg\t[(OWIDTH-1):0]          ob_b_r, ob_b_i;\n"
114 
        "\tassign       ob_b = { ob_b_r, ob_b_i };\n"
115 2 dgisselq 
"\n"
116 5 dgisselq 
        "\treg\t[(LGWIDTH-1):0]         iaddr;\n"
117 
        "\treg\t[(2*IWIDTH-1):0]        imem;\n"
118 2 dgisselq 
"\n"
119 5 dgisselq 
        "\twire\tsigned\t[(IWIDTH-1):0]\timem_r, imem_i;\n"
120 
        "\tassign\timem_r = imem[(2*IWIDTH-1):(IWIDTH)];\n"
121 
        "\tassign\timem_i = imem[(IWIDTH-1):0];\n"
122 2 dgisselq 
"\n"
123 5 dgisselq 
        "\twire\tsigned\t[(IWIDTH-1):0]\ti_data_r, i_data_i;\n"
124 
        "\tassign\ti_data_r = i_data[(2*IWIDTH-1):(IWIDTH)];\n"
125 
        "\tassign\ti_data_i = i_data[(IWIDTH-1):0];\n"
126 2 dgisselq 
"\n"
127 5 dgisselq 
        "\treg  [(2*OWIDTH-1):0]        omem;\n"
128 2 dgisselq 
"\n"
129 5 dgisselq 
        "\twire [(IWIDTH-1):0]  rnd;\n"
130 
        "\tassign rnd = ((IWIDTH+1-OWIDTH-SHIFT)!=0) ? { {(IWIDTH-1){1'b0}}, (OWIDTH<IWIDTH+1)? 1'b1:1'b0 } : {{(IWIDTH){1'b0}}};\n"
131 2 dgisselq 
"\n"
132 5 dgisselq 
        "\talways @(posedge i_clk)\n"
133 
                "\t\tif (i_rst)\n"
134 
                "\t\tbegin\n"
135 
                        "\t\t\twait_for_sync <= 1'b1;\n"
136 
                        "\t\t\tiaddr <= 0;\n"
137 
                        "\t\t\tpipeline <= 3'b000;\n"
138 
                "\t\tend\n"
139 
                "\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
140 
                "\t\tbegin\n"
141 
                        "\t\t\t// Always\n"
142 
                        "\t\t\timem <= i_data;\n"
143 
                        "\t\t\tiaddr <= iaddr + 1;\n"
144 
                        "\t\t\twait_for_sync <= 1'b0;\n"
145 2 dgisselq 
"\n"
146 5 dgisselq 
                        "\t\t\t// In sequence, clock = 0\n"
147 
                        "\t\t\tif (iaddr[0])\n"
148 
                        "\t\t\tbegin\n"
149 
                                "\t\t\t\tsum_r  <= imem_r + i_data_r + rnd;\n"
150 
                                "\t\t\t\tsum_i  <= imem_i + i_data_i + rnd;\n"
151 
                                "\t\t\t\tdiff_r <= imem_r - i_data_r + rnd;\n"
152 
                                "\t\t\t\tdiff_i <= imem_i - i_data_i + rnd;\n"
153 2 dgisselq 
"\n"
154 5 dgisselq 
                        "\t\t\t\tpipeline[2:0] <= { pipeline[1:0], 1'b1 };\n"
155 
                        "\t\t\tend else\n"
156 
                        "\t\t\t\tpipeline[2:0] <= { pipeline[1:0], 1'b0 };\n"
157 2 dgisselq 
"\n"
158 5 dgisselq 
                        "\t\t\t// In sequence, clock = 1\n"
159 
                        "\t\t\tif (pipeline[1])\n"
160 
                        "\t\t\tbegin\n"
161 
                        "\t\t\t\tob_a <= { sum_r[(IWIDTH):(IWIDTH+1-OWIDTH)],\n"
162 
                                                "\t\t\t\t\t\tsum_i[(IWIDTH):(IWIDTH+1-OWIDTH)] };\n"
163 
                                "\t\t\t\t// on Even, W = e^{-j2pi 1/4 0} = 1\n"
164 
                                "\t\t\t\tif (~ODD)\n"
165 
                                "\t\t\t\tbegin\n"
166 2 dgisselq 
"\t\t\t\t\tob_b_r <= diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
167 
"\t\t\t\t\tob_b_i <= diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
168 5 dgisselq 
                                "\t\t\t\tend else if (~INVERSE) begin\n"
169 2 dgisselq 
"\t\t\t\t\t// on Odd, W = e^{-j2pi 1/4} = -j\n"
170 
"\t\t\t\t\tob_b_r <=   diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
171 
"\t\t\t\t\tob_b_i <=   diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
172 5 dgisselq 
                                "\t\t\t\tend else begin\n"
173 2 dgisselq 
"\t\t\t\t\t// on Odd, W = e^{j2pi 1/4} = j\n"
174 
"\t\t\t\t\tob_b_r <= n_diff_i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
175 
"\t\t\t\t\tob_b_i <=   diff_r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
176 5 dgisselq 
                                "\t\t\t\tend\n"
177 
                                "\t\t\t\t// (wire) ob_b <= { ob_b_r, ob_b_i };\n"
178 
                        "\t\t\tend\n"
179 
                        "\t\t\t// In sequence, clock = 2\n"
180 
                        "\t\t\tif (pipeline[2])\n"
181 
                        "\t\t\tbegin\n"
182 
                                "\t\t\t\tomem <= ob_b;\n"
183 
                                "\t\t\t\to_data <= ob_a;\n"
184 
                        "\t\t\tend else\n"
185 
                                "\t\t\t\to_data <= omem;\n"
186 6 dgisselq 
                        "\t\t\t// Don\'t forget in the sync check that we are running\n"
187 
                        "\t\t\t// at two clocks per sample.  Thus we need to\n"
188 
                        "\t\t\t// produce a sync every 2^(LGWIDTH-1) clocks.\n"
189 
                        "\t\t\to_sync <= &(~iaddr[(LGWIDTH-2):3]) && (iaddr[2:0] == 3'b100);\n"
190 5 dgisselq 
                "\t\tend\n"
191 2 dgisselq 
"endmodule\n");
192 
}
193 
 
194 
void    build_dblstage(const char *fname) {
195 
        FILE    *fp = fopen(fname, "w");
196 
        if (NULL == fp) {
197 
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
198 
                perror("O/S Err was:");
199 
                return;
200 
        }
201 
 
202 
        fprintf(fp,
203 
"///////////////////////////////////////////////////////////////////////////\n"
204 
"//\n"
205 
"// Filename:   dblstage.v\n"
206 
"//\n"
207 
"// Project:    %s\n"
208 
"//\n"
209 
"// Purpose:    This is part of an FPGA implementation that will process\n"
210 5 dgisselq 
"//             the final stage of a decimate-in-frequency FFT, running\n"
211 
"//             through the data at two samples per clock.  If you notice\n"
212 
"//             from the derivation of an FFT, the only time both even and\n"
213 
"//             odd samples are used at the same time is in this stage.\n"
214 
"//             Therefore, other than this stage and these twiddles, all of\n"
215 
"//             the other stages can run two stages at a time at one sample\n"
216 
"//             per clock.\n"
217 2 dgisselq 
"//\n"
218 
"//             In this implementation, the output is valid one clock after\n"
219 
"//             the input is valid.  The output also accumulates one bit\n"
220 
"//             above and beyond the number of bits in the input.\n"
221 
"//             \n"
222 
"//             i_clk   A system clock\n"
223 6 dgisselq 
"//             i_rst   A synchronous reset\n"
224 2 dgisselq 
"//             i_ce    Circuit enable--nothing happens unless this line is high\n"
225 6 dgisselq 
"//             i_sync  A synchronization signal, high once per FFT at the start\n"
226 2 dgisselq 
"//             i_left  The first (even) complex sample input.  The higher order\n"
227 
"//                     bits contain the real portion, low order bits the\n"
228 
"//                     imaginary portion, all in two\'s complement.\n"
229 
"//             i_right The next (odd) complex sample input, same format as\n"
230 
"//                     i_left.\n"
231 
"//             o_left  The first (even) complex output.\n"
232 
"//             o_right The next (odd) complex output.\n"
233 6 dgisselq 
"//             o_sync  Output synchronization signal.\n"
234 2 dgisselq 
"//\n%s"
235 
"//\n", prjname, creator);
236 
 
237 
        fprintf(fp, "%s", cpyleft);
238 
        fprintf(fp,
239 6 dgisselq 
"module dblstage(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync);\n"
240 5 dgisselq 
        "\tparameter\tIWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;\n"
241 6 dgisselq 
        "\tinput\t\ti_clk, i_rst, i_ce, i_sync;\n"
242 5 dgisselq 
        "\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"
243 6 dgisselq 
        "\toutput\twire\t[(2*OWIDTH-1):0]\to_left, o_right;\n"
244 
        "\toutput\treg\t\t\to_sync;\n"
245 2 dgisselq 
"\n"
246 5 dgisselq 
        "\twire\tsigned\t[(IWIDTH-1):0]\ti_in_0r, i_in_0i, i_in_1r, i_in_1i;\n"
247 
        "\tassign\ti_in_0r = i_left[(2*IWIDTH-1):(IWIDTH)]; \n"
248 
        "\tassign\ti_in_0i = i_left[(IWIDTH-1):0]; \n"
249 
        "\tassign\ti_in_1r = i_right[(2*IWIDTH-1):(IWIDTH)]; \n"
250 
        "\tassign\ti_in_1i = i_right[(IWIDTH-1):0]; \n"
251 
        "\twire\t[(OWIDTH-1):0]\t\to_out_0r, o_out_0i,\n"
252 
                                "\t\t\t\t\to_out_1r, o_out_1i;\n"
253 2 dgisselq 
"\n"
254 5 dgisselq 
        "\t// Don't forget that we accumulate a bit by adding two values\n"
255 
        "\t// together. Therefore our intermediate value must have one more\n"
256 
        "\t// bit than the two originals.\n"
257 
        "\treg\t[IWIDTH:0]\tout_0r, out_0i, out_1r, out_1i;\n"
258 2 dgisselq 
"\n"
259 6 dgisselq 
        "\treg\twait_for_sync;\n"
260 
"\n"
261 5 dgisselq 
        "\talways @(posedge i_clk)\n"
262 6 dgisselq 
                "\t\tif (i_rst)\n"
263 
                        "\t\t\twait_for_sync <= 1'b1;\n"
264 
                "\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
265 5 dgisselq 
                "\t\tbegin\n"
266 6 dgisselq 
                        "\t\t\twait_for_sync <= 1'b0;\n"
267 
                        "\t\t\t//\n"
268 5 dgisselq 
                        "\t\t\tout_0r <= i_in_0r + i_in_1r;\n"
269 
                        "\t\t\tout_0i <= i_in_0i + i_in_1i;\n"
270 
                        "\t\t\t//\n"
271 
                        "\t\t\tout_1r <= i_in_0r - i_in_1r;\n"
272 
                        "\t\t\tout_1i <= i_in_0i - i_in_1i;\n"
273 6 dgisselq 
                        "\t\t\t//\n"
274 
                        "\t\t\to_sync <= i_sync;\n"
275 5 dgisselq 
                "\t\tend\n"
276 2 dgisselq 
"\n"
277 5 dgisselq 
        "\t// Now, if the master control program doesn't want to keep all of\n"
278 
        "\t// our bits, we can shift down to OWIDTH bits here.\n"
279 
        "\tassign\to_out_0r = out_0r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
280 
        "\tassign\to_out_0i = out_0i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
281 
        "\tassign\to_out_1r = out_1r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
282 
        "\tassign\to_out_1i = out_1i[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
283 2 dgisselq 
"\n"
284 5 dgisselq 
        "\tassign\to_left  = { o_out_0r, o_out_0i };\n"
285 
        "\tassign\to_right = { o_out_1r, o_out_1i };\n"
286 2 dgisselq 
"\n"
287 
"endmodule\n");
288 
        fclose(fp);
289 
}
290 
 
291 
void    build_multiply(const char *fname) {
292 
        FILE    *fp = fopen(fname, "w");
293 
        if (NULL == fp) {
294 
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
295 
                perror("O/S Err was:");
296 
                return;
297 
        }
298 
 
299 
        fprintf(fp,
300 
"///////////////////////////////////////////////////////////////////////////\n"
301 
"//\n"
302 
"// Filename:   shiftaddmpy.v\n"
303 
"//\n"
304 
"// Project:    %s\n"
305 
"//\n"
306 
"// Purpose:    A portable shift and add multiply.\n"
307 
"//\n"
308 
"//             While both Xilinx and Altera will offer single clock \n"
309 
"//             multiplies, this simple approach will multiply two numbers\n"
310 
"//             on any architecture.  The result maintains the full width\n"
311 
"//             of the multiply, there are no extra stuff bits, no rounding,\n"
312 
"//             no shifted bits, etc.\n"
313 
"//\n"
314 
"//             Further, for those applications that can support it, this\n"
315 
"//             multiply is pipelined and will produce one answer per clock.\n"
316 
"//\n"
317 
"//             For minimal processing delay, make the first parameter\n"
318 
"//             the one with the least bits, so that AWIDTH <= BWIDTH.\n"
319 
"//\n"
320 
"//             The processing delay in this multiply is (AWIDTH+1) cycles.\n"
321 
"//             That is, if the data is present on the input at clock t=0,\n"
322 
"//             the result will be present on the output at time t=AWIDTH+1;\n"
323 
"//\n"
324 
"//\n%s"
325 
"//\n", prjname, creator);
326 
 
327 
        fprintf(fp, "%s", cpyleft);
328 
        fprintf(fp,
329 
"module shiftaddmpy(i_clk, i_ce, i_a, i_b, o_r);\n"
330 
        "\tparameter\tAWIDTH=16,BWIDTH=AWIDTH;\n"
331 
        "\tinput\t\t\t\t\ti_clk, i_ce;\n"
332 
        "\tinput\t\t[(AWIDTH-1):0]\t\ti_a;\n"
333 
        "\tinput\t\t[(BWIDTH-1):0]\t\ti_b;\n"
334 
        "\toutput\treg\t[(AWIDTH+BWIDTH-1):0]\to_r;\n"
335 
"\n"
336 
        "\treg\t[(AWIDTH-1):0]\tu_a;\n"
337 
        "\treg\t[(BWIDTH-1):0]\tu_b;\n"
338 
        "\treg\t\t\tsgn;\n"
339 
"\n"
340 
        "\treg\t[(AWIDTH-2):0]\t\tr_a[0:(AWIDTH-1)];\n"
341 
        "\treg\t[(AWIDTH+BWIDTH-2):0]\tr_b[0:(AWIDTH-1)];\n"
342 
        "\treg\t\t\t\tr_s[0:(AWIDTH-1)];\n"
343 
        "\treg\t[(AWIDTH+BWIDTH-1):0]\tacc[0:(AWIDTH-1)];\n"
344 
        "\tgenvar k;\n"
345 
"\n"
346 5 dgisselq 
        "\t// If we were forced to stay within two\'s complement arithmetic,\n"
347 
        "\t// taking the absolute value here would require an additional bit.\n"
348 
        "\t// However, because our results are now unsigned, we can stay\n"
349 
        "\t// within the number of bits given (for now).\n"
350 2 dgisselq 
        "\talways @(posedge i_clk)\n"
351 
                "\t\tif (i_ce)\n"
352 
                "\t\tbegin\n"
353 
                        "\t\t\tu_a <= (i_a[AWIDTH-1])?(-i_a):(i_a);\n"
354 
                        "\t\t\tu_b <= (i_b[BWIDTH-1])?(-i_b):(i_b);\n"
355 
                        "\t\t\tsgn <= i_a[AWIDTH-1] ^ i_b[BWIDTH-1];\n"
356 
                "\t\tend\n"
357 
"\n"
358 
        "\talways @(posedge i_clk)\n"
359 
                "\t\tif (i_ce)\n"
360 
                "\t\tbegin\n"
361 
                        "\t\t\tacc[0] <= (u_a[0]) ? { {(AWIDTH){1'b0}}, u_b }\n"
362 
                        "\t\t\t\t\t: {(AWIDTH+BWIDTH){1'b0}};\n"
363 
                        "\t\t\tr_a[0] <= { u_a[(AWIDTH-1):1] };\n"
364 
                        "\t\t\tr_b[0] <= { {(AWIDTH-1){1'b0}}, u_b };\n"
365 
                        "\t\t\tr_s[0] <= sgn; // The final sign, needs to be preserved\n"
366 
                "\t\tend\n"
367 
"\n"
368 
        "\tgenerate\n"
369 
        "\talways @(posedge i_clk)\n"
370 
        "\tif (i_ce)\n"
371 
        "\tbegin\n"
372 
                "\t\tfor(k=0; k<AWIDTH-1; k++)\n"
373 
                "\t\tbegin\n"
374 
                        "\t\t\tacc[k+1] <= acc[k] + ((r_a[k][0]) ? {r_b[k],1'b0}:0);\n"
375 
                        "\t\t\tr_a[k+1] <= { 1'b0, r_a[k][(AWIDTH-2):1] };\n"
376 
                        "\t\t\tr_b[k+1] <= { r_b[k][(AWIDTH+BWIDTH-3):0], 1'b0};\n"
377 
                        "\t\t\tr_s[k+1] <= r_s[k];\n"
378 
                "\t\tend\n"
379 
        "\tend\n"
380 
        "\tendgenerate\n"
381 
"\n"
382 
        "\talways @(posedge i_clk)\n"
383 
                "\t\tif (i_ce)\n"
384 
                        "\t\t\to_r <= (r_s[AWIDTH-1]) ? (-acc[AWIDTH-1]) : acc[AWIDTH-1];\n"
385 
"\n"
386 
"endmodule\n");
387 
 
388 
        fclose(fp);
389 
}
390 
 
391 
void    build_dblreverse(const char *fname) {
392 
        FILE    *fp = fopen(fname, "w");
393 
        if (NULL == fp) {
394 
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
395 
                perror("O/S Err was:");
396 
                return;
397 
        }
398 
 
399 
        fprintf(fp,
400 
"///////////////////////////////////////////////////////////////////////////\n"
401 
"//\n"
402 
"// Filename:   dblreverse.v\n"
403 
"//\n"
404 
"// Project:    %s\n"
405 
"//\n"
406 
"// Purpose:    This module bitreverses a pipelined FFT input.  Operation is\n"
407 
"//             expected as follows:\n"
408 
"//\n"
409 
"//             i_clk   A running clock at whatever system speed is offered.\n"
410 
"//             i_rst   A synchronous reset signal, that resets all internals\n"
411 
"//             i_ce    If this is one, one input is consumed and an output\n"
412 
"//                     is produced.\n"
413 
"//             i_in_0, i_in_1\n"
414 
"//                     Two inputs to be consumed, each of width WIDTH.\n"
415 
"//             o_out_0, o_out_1\n"
416 
"//                     Two of the bitreversed outputs, also of the same\n"
417 
"//                     width, WIDTH.  Of course, there is a delay from the\n"
418 
"//                     first input to the first output.  For this purpose,\n"
419 
"//                     o_sync is present.\n"
420 
"//             o_sync  This will be a 1'b1 for the first value in any block.\n"
421 
"//                     Following a reset, this will only become 1'b1 once\n"
422 
"//                     the data has been loaded and is now valid.  After that,\n"
423 
"//                     all outputs will be valid.\n"
424 
"//\n%s"
425 
"//\n", prjname, creator);
426 
        fprintf(fp, "%s", cpyleft);
427 
        fprintf(fp,
428 
"\n\n"
429 
"//\n"
430 
"// How do we do bit reversing at two smples per clock?  Can we separate out\n"
431 
"// our work into eight memory banks, writing two banks at once and reading\n"
432 
"// another two banks in the same clock?\n"
433 
"//\n"
434 
"//     mem[00xxx0] = s_0[n]\n"
435 
"//     mem[00xxx1] = s_1[n]\n"
436 
"//     o_0[n] = mem[10xxx0]\n"
437 
"//     o_1[n] = mem[11xxx0]\n"
438 
"//     ...\n"
439 
"//     mem[01xxx0] = s_0[m]\n"
440 
"//     mem[01xxx1] = s_1[m]\n"
441 
"//     o_0[m] = mem[10xxx1]\n"
442 
"//     o_1[m] = mem[11xxx1]\n"
443 
"//     ...\n"
444 
"//     mem[10xxx0] = s_0[n]\n"
445 
"//     mem[10xxx1] = s_1[n]\n"
446 
"//     o_0[n] = mem[00xxx0]\n"
447 
"//     o_1[n] = mem[01xxx0]\n"
448 
"//     ...\n"
449 
"//     mem[11xxx0] = s_0[m]\n"
450 
"//     mem[11xxx1] = s_1[m]\n"
451 
"//     o_0[m] = mem[00xxx1]\n"
452 
"//     o_1[m] = mem[01xxx1]\n"
453 
"//     ...\n"
454 
"//\n"
455 5 dgisselq 
"//     The answer is that, yes we can but: we need to use four memory banks\n"
456 
"//     to do it properly.  These four banks are defined by the two bits\n"
457 
"//     that determine the top and bottom of the correct address.  Larger\n"
458 
"//     FFT\'s would require more memories.\n"
459 
"//\n"
460 2 dgisselq 
"//\n");
461 
        fprintf(fp,
462 
"module dblreverse(i_clk, i_rst, i_ce, i_in_0, i_in_1,\n"
463 5 dgisselq 
        "\t\to_out_0, o_out_1, o_sync);\n"
464 
        "\tparameter\t\t\tLGSIZE=4, WIDTH=24;\n"
465 
        "\tinput\t\t\t\ti_clk, i_rst, i_ce;\n"
466 
        "\tinput\t\t[(2*WIDTH-1):0]\ti_in_0, i_in_1;\n"
467 
        "\toutput\treg\t[(2*WIDTH-1):0]\to_out_0, o_out_1;\n"
468 
        "\toutput\treg\t\t\to_sync;\n"
469 2 dgisselq 
"\n"
470 5 dgisselq 
        "\treg\tin_reset;\n"
471 
        "\treg\t[(LGSIZE):0]\tiaddr;\n"
472 
        "\treg\t[(2*WIDTH-1):0]\tmem_0e [0:((1<<(LGSIZE-1))-1)];\n"
473 
        "\treg\t[(2*WIDTH-1):0]\tmem_0o [0:((1<<(LGSIZE-1))-1)];\n"
474 
        "\treg\t[(2*WIDTH-1):0]\tmem_1e [0:((1<<(LGSIZE-1))-1)];\n"
475 
        "\treg\t[(2*WIDTH-1):0]\tmem_1o [0:((1<<(LGSIZE-1))-1)];\n"
476 2 dgisselq 
"\n"
477 5 dgisselq 
        "\twire\t[(2*LGSIZE-1):0]       braddr;\n"
478 
        "\tgenvar\tk;\n"
479 
        "\tgenerate for(k=0; k<LGSIZE; k++)\n"
480 
                "\t\tassign braddr[k] = iaddr[LGSIZE-1-k];\n"
481 
        "\tendgenerate\n"
482 2 dgisselq 
"\n"
483 5 dgisselq 
        "\talways @(posedge i_clk)\n"
484 
                "\t\tif (i_rst)\n"
485 
                "\t\tbegin\n"
486 
                        "\t\t\tiaddr <= 0;\n"
487 
                        "\t\t\tin_reset <= 1'b1;\n"
488 
                "\t\tend else if (i_ce)\n"
489 
                "\t\tbegin\n"
490 
                        "\t\t\tif (iaddr[(LGSIZE-1)])\n"
491 
                        "\t\t\tbegin\n"
492 
                                "\t\t\t\tmem_1e[{iaddr[LGSIZE],iaddr[(LGSIZE-2):1]}] <= i_in_0;\n"
493 
                                "\t\t\t\tmem_1o[{iaddr[LGSIZE],iaddr[(LGSIZE-2):1]}] <= i_in_1;\n"
494 
                        "\t\t\tend else begin\n"
495 
                                "\t\t\t\tmem_0e[{iaddr[LGSIZE],iaddr[(LGSIZE-2):1]}] <= i_in_0;\n"
496 
                                "\t\t\t\tmem_0o[{iaddr[LGSIZE],iaddr[(LGSIZE-2):1]}] <= i_in_1;\n"
497 
                        "\t\t\tend\n"
498 
                        "\t\t\tiaddr <= iaddr + 2;\n"
499 
                        "\t\t\tif (&iaddr[(LGSIZE-1):1])\n"
500 
                                "\t\t\t\tin_reset <= 1'b0;\n"
501 
                        "\t\t\tif (in_reset)\n"
502 
                        "\t\t\tbegin\n"
503 
                                "\t\t\t\to_out_0 <= {(2*WIDTH){1'b0}};\n"
504 
                                "\t\t\t\to_out_1 <= {(2*WIDTH){1'b0}};\n"
505 
                                "\t\t\t\to_sync <= 1'b0;\n"
506 
                        "\t\t\tend else\n"
507 
                        "\t\t\tbegin\n"
508 
                                "\t\t\t\tif (braddr[0])\n"
509 
                                "\t\t\t\tbegin\n"
510 2 dgisselq 
"\t\t\t\t\to_out_0 <= mem_0o[{~iaddr[LGSIZE],braddr[(LGSIZE-2):1]}];\n"
511 
"\t\t\t\t\to_out_1 <= mem_1o[{~iaddr[LGSIZE],braddr[(LGSIZE-2):1]}];\n"
512 5 dgisselq 
                                "\t\t\t\tend else begin\n"
513 2 dgisselq 
"\t\t\t\t\to_out_0 <= mem_0e[{~iaddr[LGSIZE],braddr[(LGSIZE-2):1]}];\n"
514 
"\t\t\t\t\to_out_1 <= mem_1e[{~iaddr[LGSIZE],braddr[(LGSIZE-2):1]}];\n"
515 5 dgisselq 
                                "\t\t\t\tend\n"
516 
                                "\t\t\t\to_sync <= ~(|iaddr[(LGSIZE-1):0]);\n"
517 
                        "\t\t\tend\n"
518 
                "\t\tend\n"
519 2 dgisselq 
"\n"
520 
"endmodule;\n");
521 
 
522 
        fclose(fp);
523 
}
524 
 
525 
void    build_butterfly(const char *fname) {
526 
        FILE    *fp = fopen(fname, "w");
527 
        if (NULL == fp) {
528 
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
529 
                perror("O/S Err was:");
530 
                return;
531 
        }
532 
 
533 
        fprintf(fp,
534 
"///////////////////////////////////////////////////////////////////////////\n"
535 
"//\n"
536 
"// Filename:   butterfly.v\n"
537 
"//\n"
538 
"// Project:    %s\n"
539 
"//\n"
540 
"// Purpose:    This routine caculates a butterfly for a decimation\n"
541 
"//             in frequency version of an FFT.  Specifically, given\n"
542 
"//             complex Left and Right values together with a \n"
543 
"//             coefficient, the output of this routine is given\n"
544 
"//             by:\n"
545 
"//\n"
546 
"//             L' = L + R\n"
547 
"//             R' = (L - R)*C\n"
548 
"//\n"
549 
"//             The rest of the junk below handles timing (mostly),\n"
550 
"//             to make certain that L' and R' reach the output at\n"
551 
"//             the same clock.  Further, just to make certain\n"
552 
"//             that is the case, an 'aux' input exists.  This\n"
553 
"//             aux value will come out of this routine synchronized\n"
554 
"//             to the values it came in with.  (i.e., both L', R',\n"
555 
"//             and aux all have the same delay.)  Hence, a caller\n"
556 
"//             of this routine may set aux on the first input with\n"
557 
"//             valid data, and then wait to see aux set on the output\n"
558 
"//             to know when to find the first output with valid data.\n"
559 
"//\n"
560 
"//             All bits are preserved until the very last clock,\n"
561 
"//             where any more bits than OWIDTH will be quietly\n"
562 
"//             discarded.\n"
563 
"//\n"
564 
"//             This design features no overflow checking.\n"
565 
"// \n"
566 
"// Notes:\n"
567 
"//             CORDIC:\n"
568 
"//             Much as we would like, we can't use a cordic here.\n"
569 
"//             The goal is to accomplish an FFT, as defined, and a\n"
570 
"//             CORDIC places a scale factor onto the data.  Removing\n"
571 
"//             the scale factor would cost a two multiplies, which\n"
572 
"//             is precisely what we are trying to avoid.\n"
573 
"//\n"
574 
"//\n"
575 
"//             3-MULTIPLIES:\n"
576 
"//             It should also be possible to do this with three \n"
577 
"//             multiplies and an extra two addition cycles.  \n"
578 
"//\n"
579 
"//             We want\n"
580 
"//                     R+I = (a + jb) * (c + jd)\n"
581 
"//                     R+I = (ac-bd) + j(ad+bc)\n"
582 
"//             We multiply\n"
583 
"//                     P1 = ac\n"
584 
"//                     P2 = bd\n"
585 
"//                     P3 = (a+b)(c+d)\n"
586 
"//             Then \n"
587 
"//                     R+I=(P1-P2)+j(P3-P2-P1)\n"
588 
"//\n"
589 
"//             WIDTHS:\n"
590 
"//             On multiplying an X width number by an\n"
591 
"//             Y width number, X>Y, the result should be (X+Y)\n"
592 
"//             bits, right?\n"
593 
"//             -2^(X-1) <= a <= 2^(X-1) - 1\n"
594 
"//             -2^(Y-1) <= b <= 2^(Y-1) - 1\n"
595 
"//             (2^(Y-1)-1)*(-2^(X-1)) <= ab <= 2^(X-1)2^(Y-1)\n"
596 
"//             -2^(X+Y-2)+2^(X-1) <= ab <= 2^(X+Y-2) <= 2^(X+Y-1) - 1\n"
597 
"//             -2^(X+Y-1) <= ab <= 2^(X+Y-1)-1\n"
598 
"//             YUP!  But just barely.  Do this and you'll really want\n"
599 
"//             to drop a bit, although you will risk overflow in so\n"
600 
"//             doing.\n"
601 
"//\n%s"
602 
"//\n", prjname, creator);
603 
        fprintf(fp, "%s", cpyleft);
604 
 
605 
        fprintf(fp,
606 6 dgisselq 
"module\tbutterfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
607 5 dgisselq 
                "\t\to_left, o_right, o_aux);\n"
608 
        "\t// Public changeable parameters ...\n"
609 
        "\tparameter IWIDTH=16,CWIDTH=IWIDTH+4,OWIDTH=IWIDTH+1;\n"
610 
        "\t// Parameters specific to the core that should not be changed.\n"
611 
        "\tparameter    MPYDELAY=5'd20, // (IWIDTH+1 < CWIDTH)?(IWIDTH+4):(CWIDTH+3),\n"
612 
                        "\t\t\tSHIFT=0, ROUND=0;\n"
613 
        "\t// The LGDELAY should be the base two log of the MPYDELAY.  If\n"
614 
        "\t// this value is fractional, then round up to the nearest\n"
615 
        "\t// integer: LGDELAY=ceil(log(MPYDELAY)/log(2));\n"
616 
        "\tparameter\tLGDELAY=5;\n"
617 6 dgisselq 
        "\tinput\t\ti_clk, i_rst, i_ce;\n"
618 5 dgisselq 
        "\tinput\t\t[(2*CWIDTH-1):0] i_coef;\n"
619 
        "\tinput\t\t[(2*IWIDTH-1):0] i_left, i_right;\n"
620 
        "\tinput\t\ti_aux;\n"
621 
        "\toutput\twire [(2*OWIDTH-1):0] o_left, o_right;\n"
622 
        "\toutput\twire o_aux;\n"
623 2 dgisselq 
"\n"
624 5 dgisselq 
        "\twire\t[(OWIDTH-1):0] o_left_r, o_left_i, o_right_r, o_right_i;\n"
625 2 dgisselq 
"\n"
626 5 dgisselq 
        "\treg\t[(2*IWIDTH-1):0]\tr_left, r_right;\n"
627 
        "\treg\t\t\t\tr_aux, r_aux_2;\n"
628 
        "\treg\t[(2*CWIDTH-1):0]\tr_coef, r_coef_2;\n"
629 
        "\twire\tsigned\t[(CWIDTH-1):0]\tr_coef_r, r_coef_i;\n"
630 
        "\tassign\tr_coef_r  = r_coef_2[ (2*CWIDTH-1):(CWIDTH)];\n"
631 
        "\tassign\tr_coef_i  = r_coef_2[ (  CWIDTH-1):0];\n"
632 
        "\twire\tsigned\t[(IWIDTH-1):0]\tr_left_r, r_left_i, r_right_r, r_right_i;\n"
633 
        "\tassign\tr_left_r  = r_left[ (2*IWIDTH-1):(IWIDTH)];\n"
634 
        "\tassign\tr_left_i  = r_left[ (IWIDTH-1):0];\n"
635 
        "\tassign\tr_right_r = r_right[(2*IWIDTH-1):(IWIDTH)];\n"
636 
        "\tassign\tr_right_i = r_right[(IWIDTH-1):0];\n"
637 2 dgisselq 
"\n"
638 5 dgisselq 
        "\treg\tsigned\t[(IWIDTH):0]\tr_sum_r, r_sum_i, r_dif_r, r_dif_i;\n"
639 2 dgisselq 
"\n"
640 5 dgisselq 
        "\treg  [(LGDELAY-1):0] fifo_addr;\n"
641 
        "\twire [(LGDELAY-1):0] fifo_read_addr;\n"
642 6 dgisselq 
        "\tassign\tfifo_read_addr = fifo_addr - MPYDELAY;\n"
643 5 dgisselq 
        "\treg  [(2*IWIDTH+2):0]        fifo_left [ 0:((1<<LGDELAY)-1)];\n"
644 6 dgisselq 
        "\treg\t\t\t\tovalid;\n"
645 5 dgisselq 
"\n");
646 
        fprintf(fp,
647 
        "\t// Set up the input to the multiply\n"
648 2 dgisselq 
        "\talways @(posedge i_clk)\n"
649 
                "\t\tif (i_ce)\n"
650 
                "\t\tbegin\n"
651 
                        "\t\t\t// One clock just latches the inputs\n"
652 
                        "\t\t\tr_left <= i_left;        // No change in # of bits\n"
653 
                        "\t\t\tr_right <= i_right;\n"
654 
                        "\t\t\tr_aux <= i_aux;\n"
655 
                        "\t\t\tr_coef  <= i_coef;\n"
656 
                        "\t\t\t// Next clock adds/subtracts\n"
657 
                        "\t\t\tr_sum_r <= r_left_r + r_right_r; // Now IWIDTH+1 bits\n"
658 
                        "\t\t\tr_sum_i <= r_left_i + r_right_i;\n"
659 
                        "\t\t\tr_dif_r <= r_left_r - r_right_r;\n"
660 
                        "\t\t\tr_dif_i <= r_left_i - r_right_i;\n"
661 
                        "\t\t\t// Other inputs are simply delayed on second clock\n"
662 
                        "\t\t\tr_aux_2 <= r_aux;\n"
663 
                        "\t\t\tr_coef_2<= r_coef;\n"
664 
        "\t\tend\n"
665 5 dgisselq 
"\n");
666 
        fprintf(fp,
667 
        "\t// Don\'t forget to record the even side, since it doesn\'t need\n"
668 
        "\t// to be multiplied, but yet we still need the results in sync\n"
669 
        "\t// with the answer when it is ready.\n"
670 2 dgisselq 
        "\talways @(posedge i_clk)\n"
671 6 dgisselq 
                "\t\tif (i_rst)\n"
672 2 dgisselq 
                "\t\tbegin\n"
673 6 dgisselq 
                        "\t\t\tfifo_addr <= 0;\n"
674 
                        "\t\t\tovalid <= 1'b0;\n"
675 
                "\t\tend else if (i_ce)\n"
676 
                "\t\tbegin\n"
677 2 dgisselq 
                        "\t\t\t// Need to delay the sum side--nothing else happens\n"
678 
                        "\t\t\t// to it, but it needs to stay synchronized with the\n"
679 
                        "\t\t\t// right side.\n"
680 
                        "\t\t\tfifo_left[fifo_addr] <= { r_aux_2, r_sum_r, r_sum_i };\n"
681 
                        "\t\t\tfifo_addr <= fifo_addr + 1;\n"
682 6 dgisselq 
                        "\t\t\tovalid <= (ovalid) || (fifo_addr > MPYDELAY+1);\n"
683 2 dgisselq 
                "\t\tend\n"
684 
"\n"
685 5 dgisselq 
        "\twire\tsigned\t[(CWIDTH-1):0] ir_coef_r, ir_coef_i;\n"
686 
        "\tassign\tir_coef_r = r_coef_2[(2*CWIDTH-1):CWIDTH];\n"
687 
        "\tassign\tir_coef_i = r_coef_2[(CWIDTH-1):0];\n"
688 
        "\twire\tsigned\t[((IWIDTH+2)+(CWIDTH+1)-1):0]\tp_one, p_two, p_three;\n"
689 2 dgisselq 
"\n"
690 5 dgisselq 
"\n");
691 
        fprintf(fp,
692 
        "\t// Multiply output is always a width of the sum of the widths of\n"
693 
        "\t// the two inputs.  ALWAYS.  This is independent of the number of\n"
694 
        "\t// bits in p_one, p_two, or p_three.  These values needed to \n"
695 
        "\t// accumulate a bit (or two) each.  However, this approach to a\n"
696 
        "\t// three multiply complex multiply cannot increase the total\n"
697 
        "\t// number of bits in our final output.  We\'ll take care of\n"
698 
        "\t// dropping back down to the proper width, OWIDTH, in our routine\n"
699 
        "\t// below.\n"
700 2 dgisselq 
"\n"
701 5 dgisselq 
"\n");
702 
        fprintf(fp,
703 
        "\t// We accomplish here \"Karatsuba\" multiplication.  That is,\n"
704 
        "\t// by doing three multiplies we accomplish the work of four.\n"
705 
        "\t// Let\'s prove to ourselves that this works ... We wish to\n"
706 
        "\t// multiply: (a+jb) * (c+jd), where a+jb is given by\n"
707 
        "\t//\ta + jb = r_dif_r + j r_dif_i, and\n"
708 
        "\t//\tc + jd = ir_coef_r + j ir_coef_i.\n"
709 
        "\t// We do this by calculating the intermediate products P1, P2,\n"
710 
        "\t// and P3 as\n"
711 
        "\t//\tP1 = ac\n"
712 
        "\t//\tP2 = bd\n"
713 
        "\t//\tP3 = (a + b) * (c + d)\n"
714 
        "\t// and then complete our final answer with\n"
715 
        "\t//\tac - bd = P1 - P2 (this checks)\n"
716 
        "\t//\tad + bc = P3 - P2 - P1\n"
717 
        "\t//\t        = (ac + bc + ad + bd) - bd - ac\n"
718 
        "\t//\t        = bc + ad (this checks)\n"
719 2 dgisselq 
"\n"
720 5 dgisselq 
"\n");
721 
        fprintf(fp,
722 
        "\t// This should really be based upon an IF, such as in\n"
723 
        "\t// if (IWIDTH < CWIDTH) then ...\n"
724 
        "\t// However, this is the only (other) way I know to do it.\n"
725 2 dgisselq 
        "\tgenerate\n"
726 
        "\tif (CWIDTH < IWIDTH+1)\n"
727 
        "\tbegin\n"
728 
                "\t\t// We need to pad these first two multiplies by an extra\n"
729 5 dgisselq 
                "\t\t// bit just to keep them aligned with the third,\n"
730 
                "\t\t// simpler, multiply.\n"
731 2 dgisselq 
                "\t\tshiftaddmpy #(CWIDTH+1,IWIDTH+2) p1(i_clk, i_ce,\n"
732 
                                "\t\t\t\t{ir_coef_r[CWIDTH-1],ir_coef_r},\n"
733 
                                "\t\t\t\t{r_dif_r[IWIDTH],r_dif_r}, p_one);\n"
734 
                "\t\tshiftaddmpy #(CWIDTH+1,IWIDTH+2) p2(i_clk, i_ce,\n"
735 5 dgisselq 
                                "\t\t\t\t{ir_coef_i[CWIDTH-1],ir_coef_i},\n"
736 2 dgisselq 
                                "\t\t\t\t{r_dif_i[IWIDTH],r_dif_i}, p_two);\n"
737 
                "\t\tshiftaddmpy #(CWIDTH+1,IWIDTH+2) p3(i_clk, i_ce,\n"
738 5 dgisselq 
                        "\t\t\t\tir_coef_i+ir_coef_r,\n"
739 
                        "\t\t\t\tr_dif_r + r_dif_i,\n"
740 
                        "\t\t\t\tp_three);\n"
741 2 dgisselq 
        "\tend else begin\n"
742 
                "\t\tshiftaddmpy #(IWIDTH+2,CWIDTH+1) p1a(i_clk, i_ce,\n"
743 
                                "\t\t\t\t{r_dif_r[IWIDTH],r_dif_r},\n"
744 
                                "\t\t\t\t{ir_coef_r[CWIDTH-1],ir_coef_r}, p_one);\n"
745 
                "\t\tshiftaddmpy #(IWIDTH+2,CWIDTH+1) p2a(i_clk, i_ce,\n"
746 
                                "\t\t\t\t{r_dif_i[IWIDTH], r_dif_i},\n"
747 5 dgisselq 
                                "\t\t\t\t{ir_coef_i[CWIDTH-1],ir_coef_i}, p_two);\n"
748 2 dgisselq 
                "\t\tshiftaddmpy #(IWIDTH+2,CWIDTH+1) p3a(i_clk, i_ce,\n"
749 
                                "\t\t\t\tr_dif_r+r_dif_i,\n"
750 
                                "\t\t\t\tir_coef_i+ir_coef_r,\n"
751 
                                "\t\t\t\tp_three);\n"
752 
        "\tend\n"
753 
        "\tendgenerate\n"
754 5 dgisselq 
"\n");
755 
        fprintf(fp,
756 
        "\t// These values are held in memory and delayed during the\n"
757 
        "\t// multiply.  Here, we recover them.  During the multiply,\n"
758 
        "\t// values were multiplied by 2^(CWIDTH-2)*exp{-j*2*pi*...},\n"
759 
        "\t// therefore, the left_x values need to be right shifted by\n"
760 
        "\t// CWIDTH-2 as well.  The additional bits come from a sign\n"
761 
        "\t// extension.\n"
762 2 dgisselq 
        "\twire aux;\n"
763 5 dgisselq 
        "\twire\tsigned\t[(IWIDTH+CWIDTH):0]    fifo_i, fifo_r;\n"
764 
        "\treg\t\t[(2*IWIDTH+2):0]      fifo_read;\n"
765 
        "\tassign\tfifo_r = { {2{fifo_read[2*(IWIDTH+1)-1]}}, fifo_read[(2*(IWIDTH+1)-1):(IWIDTH+1)], {(CWIDTH-2){1'b0}} };\n"
766 
        "\tassign\tfifo_i = { {2{fifo_read[(IWIDTH+1)-1]}}, fifo_read[((IWIDTH+1)-1):0], {(CWIDTH-2){1'b0}} };\n"
767 
        "\tassign\taux = fifo_read[2*IWIDTH+2];\n"
768 2 dgisselq 
"\n"
769 
"\n"
770 5 dgisselq 
        "\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] b_left_r, b_left_i,\n"
771 
                        "\t\t\t\t\t\tb_right_r, b_right_i;\n"
772 
        "\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] mpy_r, mpy_i;\n"
773 
        "\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] rnd;\n"
774 
        "\tgenerate\n"
775 
        "\tif ((~ROUND)||(CWIDTH+IWIDTH-OWIDTH-SHIFT<1))\n"
776 
                "\t\tassign rnd = ({(CWIDTH+IWIDTH+3){1'b0}});\n"
777 
        "\telse\n"
778 
                "\t\tassign rnd = ({ {(OWIDTH+3+SHIFT){1'b0}},1'b1,\n"
779 
                "\t\t\t\t{(CWIDTH+IWIDTH-OWIDTH-SHIFT-1){1'b0}} });\n"
780 
        "\tendgenerate\n"
781 
"\n");
782 
        fprintf(fp,
783 2 dgisselq 
        "\talways @(posedge i_clk)\n"
784 
                "\t\tif (i_ce)\n"
785 
                "\t\tbegin\n"
786 
                        "\t\t\t// First clock, recover all values\n"
787 
                        "\t\t\tfifo_read <= fifo_left[fifo_read_addr];\n"
788 
                        "\t\t\t// These values are IWIDTH+CWIDTH+3 bits wide\n"
789 5 dgisselq 
                        "\t\t\t// although they only need to be (IWIDTH+1)\n"
790 
                        "\t\t\t// + (CWIDTH) bits wide.  (We\'ve got two\n"
791 
                        "\t\t\t// extra bits we need to get rid of.)\n"
792 2 dgisselq 
                        "\t\t\tmpy_r <= p_one - p_two;\n"
793 
                        "\t\t\tmpy_i <= p_three - p_one - p_two;\n"
794 
"\n"
795 
                        "\t\t\t// Second clock, round and latch for final clock\n"
796 
                        "\t\t\tb_right_r <= mpy_r + rnd;\n"
797 
                        "\t\t\tb_right_i <= mpy_i + rnd;\n"
798 5 dgisselq 
                        "\t\t\tb_left_r <= { {2{fifo_r[(IWIDTH+CWIDTH)]}},fifo_r } + rnd;\n"
799 
                        "\t\t\tb_left_i <= { {2{fifo_i[(IWIDTH+CWIDTH)]}},fifo_i } + rnd;\n"
800 6 dgisselq 
                        "\t\t\to_aux <= aux & ovalid;\n"
801 2 dgisselq 
                "\t\tend\n"
802 5 dgisselq 
"\n");
803 
        fprintf(fp,
804 2 dgisselq 
        "\t// Final clock--clock and remove unnecessary bits.\n"
805 5 dgisselq 
        "\t// We have (IWIDTH+CWIDTH+3) bits here, we need to drop down to\n"
806 
        "\t// OWIDTH, and SHIFT by SHIFT bits in the process.  The trick is\n"
807 
        "\t// that we don\'t need (IWIDTH+CWIDTH+3) bits.  We\'ve accumulated\n"
808 
        "\t// them, but the actual values will never fill all these bits.\n"
809 
        "\t// In particular, we only need:\n"
810 
        "\t//\t IWIDTH bits for the input\n"
811 
        "\t//\t     +1 bit for the add/subtract\n"
812 
        "\t//\t+CWIDTH bits for the coefficient multiply\n"
813 
        "\t//\t     +1 bit for the add/subtract in the complex multiply\n"
814 
        "\t//\t ------\n"
815 
        "\t//\t (IWIDTH+CWIDTH+2) bits at full precision.\n"
816 
        "\t//\n"
817 
        "\t// However, the coefficient multiply multiplied by a maximum value\n"
818 
        "\t// of 2^(CWIDTH-2).  Thus, we only have\n"
819 
        "\t//\t   IWIDTH bits for the input\n"
820 
        "\t//\t       +1 bit for the add/subtract\n"
821 
        "\t//\t+CWIDTH-2 bits for the coefficient multiply\n"
822 
        "\t//\t       +1 (optional) bit for the add/subtract in the cpx mpy.\n"
823 
        "\t//\t -------- ... multiply.  (This last bit may be shifted out.)\n"
824 
        "\t//\t (IWIDTH+CWIDTH) valid output bits. \n"
825 
        "\t// Now, if the user wants to keep any extras of these (via OWIDTH),\n"
826 
        "\t// or if he wishes to arbitrarily shift some of these off (via\n"
827 
        "\t// SHIFT) we accomplish that here.\n"
828 
        "\tassign o_left_r  = b_left_r[ (CWIDTH+IWIDTH-1-SHIFT-1):(CWIDTH+IWIDTH-OWIDTH-SHIFT-1)];\n"
829 
        "\tassign o_left_i  = b_left_i[ (CWIDTH+IWIDTH-1-SHIFT-1):(CWIDTH+IWIDTH-OWIDTH-SHIFT-1)];\n"
830 
        "\tassign o_right_r = b_right_r[(CWIDTH+IWIDTH-1-SHIFT-1):(CWIDTH+IWIDTH-OWIDTH-SHIFT-1)];\n"
831 
        "\tassign o_right_i = b_right_i[(CWIDTH+IWIDTH-1-SHIFT-1):(CWIDTH+IWIDTH-OWIDTH-SHIFT-1)];\n"
832 2 dgisselq 
"\n"
833 5 dgisselq 
        "\t// As a final step, we pack our outputs into two packed two\'s\n"
834 
        "\t// complement numbers per output word, so that each output word\n"
835 
        "\t// has (2*OWIDTH) bits in it, with the top half being the real\n"
836 
        "\t// portion and the bottom half being the imaginary portion.\n"
837 2 dgisselq 
        "\tassign       o_left = { o_left_r, o_left_i };\n"
838 
        "\tassign       o_right= { o_right_r,o_right_i};\n"
839 
"\n"
840 
"endmodule\n");
841 
        fclose(fp);
842 
}
843 
 
844 
void    build_stage(const char *fname, int stage, bool odd, int nbits, bool inv, int xtra) {
845 
        FILE    *fstage = fopen(fname, "w");
846 
        int     cbits = nbits + xtra;
847 
 
848 
        if ((cbits * 2) >= sizeof(long long)*8) {
849 
                fprintf(stderr, "ERROR: CMEM Coefficient precision requested overflows long long data type.\n");
850 
                exit(-1);
851 
        }
852 
 
853 
        if (fstage == NULL) {
854 
                fprintf(stderr, "ERROR: Could not open %s for writing!\n", fname);
855 
                perror("O/S Err was:");
856 
                fprintf(stderr, "Attempting to continue, but this file will be missing.\n");
857 
                return;
858 
        }
859 
 
860 
        fprintf(fstage,
861 
"////////////////////////////////////////////////////////////////////////////\n"
862 
"//\n"
863 
"// Filename:   %sfftstage_%c%d.v\n"
864 
"//\n"
865 
"// Project:    %s\n"
866 
"//\n"
867 
"// Purpose:    This file is (almost) a Verilog source file.  It is meant to\n"
868 
"//             be used by a FFT core compiler to generate FFTs which may be\n"
869 
"//             used as part of an FFT core.  Specifically, this file \n"
870 
"//             encapsulates the options of an FFT-stage.  For any 2^N length\n"
871 
"//             FFT, there shall be (N-1) of these stages.  \n"
872 
"//\n%s"
873 
"//\n",
874 
                (inv)?"i":"", (odd)?'o':'e', stage*2, prjname, creator);
875 
        fprintf(fstage, "%s", cpyleft);
876 
        fprintf(fstage, "module\t%sfftstage_%c%d(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync);\n",
877 
                (inv)?"i":"", (odd)?'o':'e', stage*2);
878 
        // These parameter values are useless at this point--they are to be
879 
        // replaced by the parameter values in the calling program.  Only
880 
        // problem is, the CWIDTH needs to match exactly!
881 
        fprintf(fstage, "\tparameter\tIWIDTH=%d,CWIDTH=%d,OWIDTH=%d;\n",
882 
                nbits, cbits, nbits+1);
883 
        fprintf(fstage,
884 
"\t// Parameters specific to the core that should be changed when this\n"
885 
"\t// core is built ... Note that the minimum LGSPAN (the base two log\n"
886 
"\t// of the span, or the base two log of the current FFT size) is 3.\n"
887 
"\t// Smaller spans (i.e. the span of 2) must use the dblstage module.\n"
888 6 dgisselq 
"\tparameter\tLGWIDTH=11, LGSPAN=9, LGBDLY=5, BFLYSHIFT=0;\n");
889 2 dgisselq 
        fprintf(fstage,
890 
"\tinput                                        i_clk, i_rst, i_ce, i_sync;\n"
891 
"\tinput                [(2*IWIDTH-1):0]        i_data;\n"
892 
"\toutput       reg     [(2*OWIDTH-1):0]        o_data;\n"
893 
"\toutput       reg                             o_sync;\n"
894 
"\n"
895 
"\treg  wait_for_sync;\n"
896 
"\treg  [(2*IWIDTH-1):0]        ib_a, ib_b;\n"
897 
"\treg  [(2*CWIDTH-1):0]        ib_c;\n"
898 
"\treg  ib_sync, b_ce;\n"
899 
"\n"
900 
"\treg  b_started;\n"
901 
"\twire ob_sync;\n"
902 
"\twire [(2*OWIDTH-1):0]        ob_a, ob_b;\n");
903 
        fprintf(fstage,
904 
"\n"
905 
"\t// %scmem is defined as an array of real and complex values,\n"
906 
"\t// where the top CWIDTH bits are the real value and the bottom\n"
907 
"\t// CWIDTH bits are the imaginary value.\n"
908 
"\t//\n"
909 
"\t// cmem[i] = { (2^(CWIDTH-2)) * cos(2*pi*i/(2^LGWIDTH)),\n"
910 
"\t//           (2^(CWIDTH-2)) * sin(2*pi*i/(2^LGWIDTH)) };\n"
911 
"\t//\n"
912 
"\treg  [(2*CWIDTH-1):0]        %scmem [0:((1<<LGSPAN)-1)];\n"
913 
"\tinitial\t$readmemh(\"%scmem_%c%d.hex\",%scmem);\n\n",
914 
                (inv)?"i":"", (inv)?"i":"",
915 
                (inv)?"i":"", (odd)?'o':'e',stage<<1,
916 
                (inv)?"i":"");
917 
        {
918 
                FILE    *cmem;
919 
                char    memfile[128], *ptr;
920 
 
921 
                strncpy(memfile, fname, 125);
922 
                if ((NULL != (ptr = strrchr(memfile, '/')))&&(ptr>memfile)) {
923 
                        ptr++;
924 
                        sprintf(ptr, "%scmem_%c%d.hex", (inv)?"i":"", (odd)?'o':'e', stage*2);
925 
                } else {
926 
                        sprintf(memfile, "%s/%scmem_%c%d.hex",
927 
                                COREDIR, (inv)?"i":"",
928 
                                (odd)?'o':'e', stage*2);
929 
                }
930 
                // strcpy(&memfile[strlen(memfile)-2], ".hex");
931 
                cmem = fopen(memfile, "w");
932 
                // fprintf(cmem, "// CBITS = %d, inv = %s\n", cbits, (inv)?"true":"false");
933 
                for(int i=0; i<stage/2; i++) {
934 
                        int k = 2*i+odd;
935 
                        double  W = ((inv)?1:-1)*2.0*M_PI*k/(double)stage;
936 
                        double  c, s;
937 
                        long long ic, is, vl;
938 
 
939 
                        c = cos(W); s = sin(W);
940 
                        ic = (long long)((double)((1ll<<(cbits-2)) * c + 0.5));
941 
                        is = (long long)((double)((1ll<<(cbits-2)) * s + 0.5));
942 
                        vl = (ic & (~(-1ll << (cbits))));
943 
                        vl <<= (cbits);
944 
                        vl |= (is & (~(-1ll << (cbits))));
945 
                        fprintf(cmem, "%0*llx\n", ((cbits*2+3)/4), vl);
946 
                        /*
947 
                        fprintf(cmem, "%0*llx\t\t// %f+j%f -> %llx +j%llx\n",
948 
                                ((cbits*2+3)/4), vl, c, s,
949 
                                ic & (~(-1ll<<(((cbits+3)/4)*4))),
950 
                                is & (~(-1ll<<(((cbits+3)/4)*4))));
951 
                        */
952 
                } fclose(cmem);
953 
        }
954 
 
955 
        fprintf(fstage,
956 6 dgisselq 
"\treg  [(LGWIDTH-2):0]         iaddr;\n"
957 2 dgisselq 
"\treg  [(2*IWIDTH-1):0]        imem    [0:((1<<LGSPAN)-1)];\n"
958 
"\n"
959 
"\treg  [(LGSPAN-1):0]          oB;\n"
960 
"\treg  [(2*OWIDTH-1):0]        omem    [0:((1<<LGSPAN)-1)];\n"
961 
"\n"
962 
"\talways @(posedge i_clk)\n"
963 
        "\t\tif (i_rst)\n"
964 
        "\t\tbegin\n"
965 
                "\t\t\twait_for_sync <= 1'b1;\n"
966 
                "\t\t\tiaddr <= 0;\n"
967 
                "\t\t\toB <= 0;\n"
968 
                "\t\t\tb_ce <= 1'b0;\n"
969 
        "\t\tend\n"
970 
        "\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
971 
        "\t\tbegin\n"
972 
                "\t\t\t//\n"
973 
                "\t\t\t// First step: Record what we\'re not ready to use yet\n"
974 
                "\t\t\t//\n"
975 
                "\t\t\timem[iaddr[(LGSPAN-1):0]] <= i_data;\n"
976 
                "\t\t\tiaddr <= iaddr + 1;\n"
977 
                "\t\t\twait_for_sync <= 1'b0;\n"
978 
"\n"
979 
                "\t\t\t//\n"
980 
                "\t\t\t// Now, we have all the inputs, so let\'s feed the\n"
981 
                "\t\t\t// butterfly\n"
982 
                "\t\t\t//\n"
983 6 dgisselq 
                "\t\t\tif (iaddr[LGSPAN])\n"
984 2 dgisselq 
                "\t\t\tbegin\n"
985 
                        "\t\t\t\t// One input from memory, ...\n"
986 
                        "\t\t\t\tib_a <= imem[iaddr[(LGSPAN-1):0]];\n"
987 
                        "\t\t\t\t// One input clocked in from the top\n"
988 
                        "\t\t\t\tib_b <= i_data;\n"
989 
                        "\t\t\t\t// Set the sync to true on the very first\n"
990 
                        "\t\t\t\t// valid input in, and hence on the very\n"
991 
                        "\t\t\t\t// first valid data out per FFT.\n"
992 6 dgisselq 
                        "\t\t\t\tib_sync <= (iaddr==(1<<(LGSPAN)));\n"
993 2 dgisselq 
                        "\t\t\t\tib_c <= %scmem[iaddr[(LGSPAN-1):0]];\n"
994 
                        "\t\t\t\tb_ce <= 1'b1;\n"
995 
                "\t\t\tend else\n"
996 
                        "\t\t\t\tb_ce <= 1'b0;\n"
997 
"\n"
998 
                "\t\t\t//\n"
999 
                "\t\t\t// Next step: recover the outputs from the butterfly\n"
1000 
                "\t\t\t//\n"
1001 
                "\t\t\tif ((ob_sync||b_started)&&(b_ce))\n"
1002 
                "\t\t\tbegin // A butterfly output is available\n"
1003 
                        "\t\t\t\tb_started <= 1'b1;\n"
1004 
                        "\t\t\t\tomem[oB] <= ob_b;\n"
1005 
                        "\t\t\t\toB <= oB+1;\n"
1006 
"\n"
1007 6 dgisselq 
                        "\t\t\t\to_sync <= (ob_sync);\n"
1008 2 dgisselq 
                        "\t\t\t\to_data <= ob_a;\n"
1009 
                "\t\t\tend else if (b_started)\n"
1010 
                "\t\t\tbegin // and keep outputting once you start--at a rate\n"
1011 
                "\t\t\t// of one guaranteed output per clock that has i_ce set.\n"
1012 
                        "\t\t\t\to_data <= omem[oB];\n"
1013 
                        "\t\t\t\toB <= oB + 1;\n"
1014 
                        "\t\t\t\to_sync <= 1'b0;\n"
1015 
                "\t\t\tend else\n"
1016 
                        "\t\t\t\to_sync <= 1'b0;\n"
1017 
        "\t\tend\n"
1018 5 dgisselq 
"\n", (inv)?"i":"");
1019 
        fprintf(fstage,
1020 2 dgisselq 
"\tbutterfly #(.IWIDTH(IWIDTH),.CWIDTH(CWIDTH),.OWIDTH(OWIDTH),\n"
1021 5 dgisselq 
"\t\t\t.MPYDELAY(%d\'d%d),.LGDELAY(LGBDLY),.SHIFT(BFLYSHIFT))\n"
1022 6 dgisselq 
"\t\tbfly(i_clk, i_rst, (b_ce&i_ce), ib_c,\n"
1023 2 dgisselq 
"\t\t\tib_a, ib_b, ib_sync, ob_a, ob_b, ob_sync);\n"
1024 
"endmodule;\n",
1025 5 dgisselq 
        lgdelay(nbits, xtra), (1<xtra)?(nbits+4):(nbits+xtra+3));
1026 2 dgisselq 
}
1027 
 
1028 
void    usage(void) {
1029 
        fprintf(stderr,
1030 
"USAGE:\tfftgen [-f <size>] [-d dir] [-c cbits] [-n nbits] [-m mxbits] [-s01]\n"
1031 
// "\tfftgen -i\n"
1032 
"\t-c <cbits>\tCauses all internal complex coefficients to be\n"
1033 
"\t\tlonger than the corresponding data bits, to help avoid\n"
1034 
"\t\tcoefficient truncation errors.\n"
1035 
"\t-d <dir>\tPlaces all of the generated verilog files into <dir>.\n"
1036 
"\t-f <size>\tSets the size of the FFT as the number of complex\n"
1037 
"\t\tsamples input to the transform.\n"
1038 
"\t-n <nbits>\tSets the number of bits in the twos complement input\n"
1039 
"\t\tto the FFT routine.\n"
1040 
"\t-m <mxbits>\tSets the maximum bit width that the FFT should ever\n"
1041 
"\t\tproduce.  Internal values greater than this value will be\n"
1042 
"\t\ttruncated to this value.\n"
1043 
"\t-s\tSkip the final bit reversal stage.  This is useful in\n"
1044 
"\t\talgorithms that need to apply a filter without needing to do\n"
1045 
"\t\tbin shifting, as these algorithms can, with this option, just\n"
1046 
"\t\tmultiply by a bit reversed correlation sequence and then\n"
1047 
"\t\tinverse FFT the (still bit reversed) result.\n"
1048 
"\t-S\tInclude the final bit reversal stage (default).\n"
1049 
"\t-0\tA forward FFT (default), meaning that the coefficients are\n"
1050 
"\t\tgiven by e^{-j 2 pi k/N n }.\n"
1051 
"\t-1\tAn inverse FFT, meaning that the coefficients are\n"
1052 
"\t\tgiven by e^{ j 2 pi k/N n }.\n");
1053 
}
1054 
 
1055 
// Features still needed:
1056 
//      Interactivity.
1057 
//      Some number of maximum bits, beyond which we won't accumulate any more.
1058 
//      Obviously, the build_stage above.
1059 
//      Copying the files of interest into the fft-core directory, from
1060 
//              whatever directory this file is run out of.
1061 
int main(int argc, char **argv) {
1062 
        int     fftsize = -1, lgsize = -1;
1063 
        int     nbitsin = 16, xtracbits = 4;
1064 
        int     nbitsout, maxbitsout = -1;
1065 
        bool    bitreverse = true, inverse=false, interactive = false,
1066 
                verbose_flag = false;
1067 
        FILE    *vmain;
1068 
        char    fname[128], coredir[1024] = "fft-core";
1069 
 
1070 
 
1071 
        if (argc <= 1)
1072 
                usage();
1073 
 
1074 
        for(int argn=1; argn<argc; argn++) {
1075 
                if ('-' == argv[argn][0]) {
1076 
                        for(int j=1; (argv[argn][j])&&(j<100); j++) {
1077 
                                switch(argv[argn][j]) {
1078 
                                        case '0':
1079 
                                                inverse = false;
1080 
                                                break;
1081 
                                        case '1':
1082 
                                                inverse = true;
1083 
                                                break;
1084 
                                        case 'c':
1085 
                                                if (argn+1 >= argc) {
1086 
                                                        printf("No extra number of coefficient bits given\n");
1087 
                                                        usage(); exit(-1);
1088 
                                                }
1089 
                                                xtracbits = atoi(argv[++argn]);
1090 
                                                j+= 200;
1091 
                                                break;
1092 
                                        case 'd':
1093 
                                                if (argn+1 >= argc) {
1094 
                                                        printf("No extra number of coefficient bits given\n");
1095 
                                                        usage(); exit(-1);
1096 
                                                }
1097 
                                                strcpy(coredir, argv[++argn]);
1098 
                                                j += 200;
1099 
                                                break;
1100 
                                        case 'f':
1101 
                                                if (argn+1 >= argc) {
1102 
                                                        printf("No FFT Size given\n");
1103 
                                                        usage(); exit(-1);
1104 
                                                }
1105 
                                                fftsize = atoi(argv[++argn]);
1106 
                                                { int sln = strlen(argv[argn]);
1107 
                                                if (!isdigit(argv[argn][sln-1])){
1108 
                                                        switch(argv[argn][sln-1]) {
1109 
                                                        case 'k': case 'K':
1110 
                                                                fftsize <<= 10;
1111 
                                                                break;
1112 
                                                        case 'm': case 'M':
1113 
                                                                fftsize <<= 20;
1114 
                                                                break;
1115 
                                                        case 'g': case 'G':
1116 
                                                                fftsize <<= 30;
1117 
                                                                break;
1118 
                                                        default:
1119 
                                                                printf("Unknown FFT size, %s\n", argv[argn]);
1120 
                                                                exit(-1);
1121 
                                                        }
1122 
                                                }}
1123 
                                                j += 200;
1124 
                                                break;
1125 
                                        case 'h':
1126 
                                                usage();
1127 
                                                exit(0);
1128 
                                                break;
1129 
                                        case 'i':
1130 
                                                interactive = true;
1131 
                                                break;
1132 
                                        case 'm':
1133 
                                                if (argn+1 >= argc) {
1134 
                                                        printf("No maximum output bit value given\n");
1135 
                                                        exit(-1);
1136 
                                                }
1137 
                                                maxbitsout = atoi(argv[++argn]);
1138 
                                                j += 200;
1139 
                                                break;
1140 
                                        case 'n':
1141 
                                                if (argn+1 >= argc) {
1142 
                                                        printf("No input bit size given\n");
1143 
                                                        exit(-1);
1144 
                                                }
1145 
                                                nbitsin = atoi(argv[++argn]);
1146 
                                                j += 200;
1147 
                                                break;
1148 
                                        case 'S':
1149 
                                                bitreverse = true;
1150 
                                                break;
1151 
                                        case 's':
1152 
                                                bitreverse = false;
1153 
                                                break;
1154 
                                        case 'v':
1155 
                                                verbose_flag = true;
1156 
                                                break;
1157 
                                        default:
1158 
                                                printf("Unknown argument, -%c\n", argv[argn][j]);
1159 
                                                usage();
1160 
                                                exit(-1);
1161 
                                }
1162 
                        }
1163 
                } else {
1164 
                        printf("Unrecognized argument, %s\n", argv[argn]);
1165 
                        usage();
1166 
                        exit(-1);
1167 
                }
1168 
        }
1169 
 
1170 
        if ((lgsize < 0)&&(fftsize > 1)) {
1171 
                for(lgsize=1; (1<<lgsize) < fftsize; lgsize++)
1172 
                        ;
1173 
        }
1174 
 
1175 
        if ((fftsize <= 0)||(nbitsin < 1)||(nbitsin>48)) {
1176 
                printf("INVALID PARAMETERS!!!!\n");
1177 
                exit(-1);
1178 
        }
1179 
 
1180 
 
1181 
        if (nextlg(fftsize) != fftsize) {
1182 
                fprintf(stderr, "ERR: FFTSize (%d) *must* be a power of two\n",
1183 
                                fftsize);
1184 
                exit(-1);
1185 
        } else if (fftsize < 2) {
1186 
                fprintf(stderr, "ERR: Minimum FFTSize is 2, not %d\n",
1187 
                                fftsize);
1188 
                if (fftsize == 1) {
1189 
                        fprintf(stderr, "You do realize that a 1 point FFT makes very little sense\n");
1190 
                        fprintf(stderr, "in an FFT operation that handles two samples per clock?\n");
1191 
                        fprintf(stderr, "If you really need to do an FFT of this size, the output\n");
1192 
                        fprintf(stderr, "can be connected straight to the input.\n");
1193 
                } else {
1194 
                        fprintf(stderr, "Indeed, a size of %d doesn\'t make much sense to me at all.\n", fftsize);
1195 
                        fprintf(stderr, "Is such an operation even defined?\n");
1196 
                }
1197 
                exit(-1);
1198 
        }
1199 
 
1200 
        // Calculate how many output bits we'll have, and what the log
1201 
        // based two size of our FFT is.
1202 
        {
1203 
                int     tmp_size = fftsize;
1204 
 
1205 
                // The first stage always accumulates one bit, regardless
1206 
                // of whether you need to or not.
1207 
                nbitsout = nbitsin + 1;
1208 
                tmp_size >>= 1;
1209 
 
1210 
                while(tmp_size > 4) {
1211 
                        nbitsout += 1;
1212 
                        tmp_size >>= 2;
1213 
                }
1214 
 
1215 
                if (tmp_size > 1)
1216 
                        nbitsout ++;
1217 
 
1218 
                if (fftsize <= 2)
1219 
                        bitreverse = false;
1220 
        } if ((maxbitsout > 0)&&(nbitsout > maxbitsout))
1221 
                nbitsout = maxbitsout;
1222 
 
1223 
 
1224 
        {
1225 
                struct stat     sbuf;
1226 
                if (lstat(coredir, &sbuf)==0) {
1227 
                        if (!S_ISDIR(sbuf.st_mode)) {
1228 
                                fprintf(stderr, "\'%s\' already exists, and is not a directory!\n", coredir);
1229 
                                fprintf(stderr, "I will stop now, lest I overwrite something you care about.\n");
1230 
                                fprintf(stderr, "To try again, please remove this file.\n");
1231 
                                exit(-1);
1232 
                        }
1233 
                } else
1234 
                        mkdir(coredir, 0755);
1235 
                if (access(coredir, X_OK|W_OK) != 0) {
1236 
                        fprintf(stderr, "I have no access to the directory \'%s\'.\n", coredir);
1237 
                        exit(-1);
1238 
                }
1239 
        }
1240 
 
1241 
        sprintf(fname, "%s/%sfftmain.v", coredir, (inverse)?"i":"");
1242 
        vmain = fopen(fname, "w");
1243 
        if (NULL == vmain) {
1244 
                fprintf(stderr, "Could not open \'%s\' for writing\n", fname);
1245 
                perror("Err from O/S:");
1246 
                exit(-1);
1247 
        }
1248 
 
1249 
        fprintf(vmain, "/////////////////////////////////////////////////////////////////////////////\n");
1250 
        fprintf(vmain, "//\n");
1251 
        fprintf(vmain, "// Filename:    %sfftmain.v\n", (inverse)?"i":"");
1252 
        fprintf(vmain, "//\n");
1253 
        fprintf(vmain, "// Project:     %s\n", prjname);
1254 
        fprintf(vmain, "//\n");
1255 
        fprintf(vmain, "// Purpose:     This is the main module in the Doubletime FPGA FFT project.\n");
1256 
        fprintf(vmain, "//              As such, all other modules are subordinate to this one.\n");
1257 
        fprintf(vmain, "//              (I have been reading too much legalese this week ...)\n");
1258 
        fprintf(vmain, "//              This module accomplish a fixed size Complex FFT on %d data\n", fftsize);
1259 
        fprintf(vmain, "//              points.  The FFT is fully pipelined, and accepts as inputs\n");
1260 
        fprintf(vmain, "//              two complex two\'s complement samples per clock.\n");
1261 
        fprintf(vmain, "//\n");
1262 
        fprintf(vmain, "// Parameters:\n");
1263 
        fprintf(vmain, "//      i_clk\tThe clock.  All operations are synchronous with this clock.\n");
1264 
        fprintf(vmain, "//\ti_rst\tSynchronous reset, active high.  Setting this line will\n");
1265 
        fprintf(vmain, "//\t\t\tforce the reset of all of the internals to this routine.\n");
1266 
        fprintf(vmain, "//\t\t\tFurther, following a reset, the o_sync line will go\n");
1267 
        fprintf(vmain, "//\t\t\thigh the same time the first output sample is valid.\n");
1268 
        fprintf(vmain, "//      i_ce\tA clock enable line.  If this line is set, this module\n");
1269 
        fprintf(vmain, "//\t\t\twill accept two complex values as inputs, and produce\n");
1270 
        fprintf(vmain, "//\t\t\ttwo (possibly empty) complex values as outputs.\n");
1271 
        fprintf(vmain, "//\t\ti_left\tThe first of two complex input samples.  This value\n");
1272 
        fprintf(vmain, "//\t\t\tis split into two two\'s complement numbers, of \n");
1273 
        fprintf(vmain, "//\t\t\t%d bits each, with the real portion in the high\n", nbitsin);
1274 
        fprintf(vmain, "//\t\t\torder bits, and the imaginary portion taking the\n");
1275 
        fprintf(vmain, "//\t\t\tbottom %d bits.\n", nbitsin);
1276 
        fprintf(vmain, "//\t\ti_right\tThis is the same thing as i_left, only this is the\n");
1277 
        fprintf(vmain, "//\t\t\tsecond of two such samples.  Hence, i_left would\n");
1278 
        fprintf(vmain, "//\t\t\tcontain input sample zero, i_right would contain\n");
1279 
        fprintf(vmain, "//\t\t\tsample one.  On the next clock i_left would contain\n");
1280 
        fprintf(vmain, "//\t\t\tinput sample two, i_right number three and so forth.\n");
1281 
        fprintf(vmain, "//\t\to_left\tThe first of two output samples, of the same\n");
1282 
        fprintf(vmain, "//\t\t\tformat as i_left, only having %d bits for each of\n", nbitsout);
1283 
        fprintf(vmain, "//\t\t\tthe real and imaginary components, leading to %d\n", nbitsout*2);
1284 
        fprintf(vmain, "//\t\t\tbits total.\n");
1285 
        fprintf(vmain, "//\t\to_right\tThe second of two output samples produced each clock.\n");
1286 
        fprintf(vmain, "//\t\t\tThis has the same format as o_left.\n");
1287 
        fprintf(vmain, "//\t\to_sync\tA one bit output indicating the first valid sample\n");
1288 
        fprintf(vmain, "//\t\t\tproduced by this FFT following a reset.  Ever after,\n");
1289 
        fprintf(vmain, "//\t\t\tthis will indicate the first sample of an FFT frame.\n");
1290 
        fprintf(vmain, "//\n");
1291 
        fprintf(vmain, "%s", creator);
1292 
        fprintf(vmain, "//\n");
1293 
        fprintf(vmain, "%s", cpyleft);
1294 
 
1295 
 
1296 
        fprintf(vmain, "//\n");
1297 
        fprintf(vmain, "//\n");
1298 
        fprintf(vmain, "module %sfftmain(i_clk, i_rst, i_ce,\n", (inverse)?"i":"");
1299 
        fprintf(vmain, "\t\ti_left, i_right,\n");
1300 
        fprintf(vmain, "\t\to_left, o_right, o_sync);\n");
1301 
        fprintf(vmain, "\tparameter\tIWIDTH=%d, OWIDTH=%d, LGWIDTH=%d;\n", nbitsin, nbitsout, lgsize);
1302 
        assert(lgsize > 0);
1303 
        fprintf(vmain, "\tinput\t\ti_clk, i_rst, i_ce;\n");
1304 
        fprintf(vmain, "\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n");
1305 
        fprintf(vmain, "\toutput\treg\t[(2*OWIDTH-1):0]\to_left, o_right;\n");
1306 
        fprintf(vmain, "\toutput\treg\t\t\to_sync;\n");
1307 
        fprintf(vmain, "\n\n");
1308 
 
1309 
        fprintf(vmain, "\t// Outputs of the FFT, ready for bit reversal.\n");
1310 
        fprintf(vmain, "\twire\t[(2*OWIDTH-1):0]\tbr_left, br_right;\n");
1311 
        fprintf(vmain, "\n\n");
1312 
 
1313 
        int     tmp_size = fftsize, lgtmp = lgsize;
1314 
        if (fftsize == 2) {
1315 
                if (bitreverse) {
1316 
                        fprintf(vmain, "\treg\tbr_start;\n");
1317 
                        fprintf(vmain, "\talways @(posedge i_clk)\n");
1318 
                        fprintf(vmain, "\t\tif (i_rst)\n");
1319 
                        fprintf(vmain, "\t\t\tbr_start <= 1'b0;\n");
1320 
                        fprintf(vmain, "\t\telse if (i_ce)\n");
1321 
                        fprintf(vmain, "\t\t\tbr_start <= 1'b1;\n");
1322 
                }
1323 
                fprintf(vmain, "\n\n");
1324 6 dgisselq 
                fprintf(vmain, "\tdblstage\t#(IWIDTH)\tstage_2(i_clk, i_rst, i_ce,\n");
1325 
                fprintf(vmain, "\t\t\t(~i_rst), i_left, i_right, br_left, br_right);\n");
1326 2 dgisselq 
                fprintf(vmain, "\n\n");
1327 
        } else {
1328 
                int     nbits = nbitsin, dropbit=0;
1329 
                // Always do a first stage
1330 
                fprintf(vmain, "\n\n");
1331 
                fprintf(vmain, "\twire\t\tw_s%d, w_os%d;\n", fftsize, fftsize);
1332 
                fprintf(vmain, "\twire\t[(2*IWIDTH+1):0]\tw_e%d, w_o%d;\n", fftsize, fftsize);
1333 
                fprintf(vmain, "\t%sfftstage_e%d\t#(IWIDTH,IWIDTH+%d,IWIDTH+1,%d,%d,%d,0)\tstage_e%d(i_clk, i_rst, i_ce,\n",
1334 
                        (inverse)?"i":"", fftsize,
1335 
                        xtracbits,
1336 
                        lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
1337 
                        fftsize);
1338 
                fprintf(vmain, "\t\t\t(~i_rst), i_left, w_e%d, w_s%d);\n", fftsize, fftsize);
1339 
                fprintf(vmain, "\t%sfftstage_o%d\t#(IWIDTH,IWIDTH+%d,IWIDTH+1,%d,%d,%d,0)\tstage_o%d(i_clk, i_rst, i_ce,\n",
1340 
                        (inverse)?"i":"", fftsize,
1341 
                        xtracbits,
1342 
                        lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
1343 
                        fftsize);
1344 
                fprintf(vmain, "\t\t\t(~i_rst), i_left, w_o%d, w_os%d);\n", fftsize, fftsize);
1345 
                fprintf(vmain, "\n\n");
1346 
 
1347 
                sprintf(fname, "%s/%sfftstage_e%d.v", coredir, (inverse)?"i":"", fftsize);
1348 
                build_stage(fname, fftsize/2, 0, nbits, inverse, xtracbits);     // Even stage
1349 
                sprintf(fname, "%s/%sfftstage_o%d.v", coredir, (inverse)?"i":"", fftsize);
1350 
                build_stage(fname, fftsize/2, 1, nbits, inverse, xtracbits);    // Odd  stage
1351 
 
1352 
                nbits += 1;     // New number of input bits
1353 
                tmp_size >>= 1; lgtmp--;
1354 
                dropbit = 0;
1355 
                fprintf(vmain, "\n\n");
1356 
                while(tmp_size >= 8) {
1357 
                        int     obits = nbits+((dropbit)?0:1);
1358 
 
1359 
                        if ((maxbitsout > 0)&&(obits > maxbitsout))
1360 
                                obits = maxbitsout;
1361 
 
1362 
                        fprintf(vmain, "\twire\t\tw_s%d, w_os%d;\n", tmp_size, tmp_size);
1363 
                        fprintf(vmain, "\twire\t[%d:0]\tw_e%d, w_o%d;\n", 2*obits-1, tmp_size, tmp_size);
1364 
                        fprintf(vmain, "\t%sfftstage_e%d\t#(%d,%d,%d,%d,%d,%d,%d)\tstage_e%d(i_clk, i_rst, i_ce,\n",
1365 
                                (inverse)?"i":"", tmp_size,
1366 
                                nbits, nbits+xtracbits, obits,
1367 
                                lgsize, lgtmp-2, lgdelay(nbits,xtracbits), dropbit,
1368 
                                tmp_size);
1369 
                        fprintf(vmain, "\t\t\t\t\t\tw_s%d, w_e%d, w_e%d, w_s%d);\n", tmp_size<<1, tmp_size<<1, tmp_size, tmp_size);
1370 
                        fprintf(vmain, "\t%sfftstage_o%d\t#(%d,%d,%d,%d,%d,%d,%d)\tstage_o%d(i_clk, i_rst, i_ce,\n",
1371 
                                (inverse)?"i":"", tmp_size,
1372 
                                nbits, nbits+xtracbits, obits,
1373 
                                lgsize, lgtmp-2, lgdelay(nbits,xtracbits), dropbit,
1374 
                                tmp_size);
1375 
                        fprintf(vmain, "\t\t\t\t\t\tw_s%d, w_o%d, w_o%d, w_os%d);\n", tmp_size<<1, tmp_size<<1, tmp_size, tmp_size);
1376 
                        fprintf(vmain, "\n\n");
1377 
 
1378 
                        sprintf(fname, "%s/%sfftstage_e%d.v", coredir, (inverse)?"i":"", tmp_size);
1379 
                        build_stage(fname, tmp_size/2, 0, nbits, inverse, xtracbits);    // Even stage
1380 
                        sprintf(fname, "%s/%sfftstage_o%d.v", coredir, (inverse)?"i":"", tmp_size);
1381 
                        build_stage(fname, tmp_size/2, 1, nbits, inverse, xtracbits);   // Odd  stage
1382 
 
1383 
 
1384 
                        dropbit ^= 1;
1385 
                        nbits = obits;
1386 
                        tmp_size >>= 1; lgtmp--;
1387 
                }
1388 
 
1389 
                if (tmp_size == 4) {
1390 
                        int     obits = nbits+((dropbit)?0:1);
1391 
 
1392 
                        if ((maxbitsout > 0)&&(obits > maxbitsout))
1393 
                                obits = maxbitsout;
1394 
 
1395 
                        fprintf(vmain, "\twire\t\tw_s4, w_os4;\n");
1396 
                        fprintf(vmain, "\twire\t[%d:0]\tw_e4, w_o4;\n", 2*obits-1);
1397 
                        fprintf(vmain, "\tqtrstage\t#(%d,%d,%d,0,%d,%d)\tstage_e4(i_clk, i_rst, i_ce,\n",
1398 
                                nbits, obits, lgsize, (inverse)?1:0, dropbit);
1399 6 dgisselq 
                        fprintf(vmain, "\t\t\t\t\t\tw_s8, w_e8, w_e4, w_s4);\n");
1400 2 dgisselq 
                        fprintf(vmain, "\tqtrstage\t#(%d,%d,%d,1,%d,%d)\tstage_o4(i_clk, i_rst, i_ce,\n",
1401 
                                nbits, obits, lgsize, (inverse)?1:0, dropbit);
1402 6 dgisselq 
                        fprintf(vmain, "\t\t\t\t\t\tw_s8, w_o8, w_o4, w_os4);\n");
1403 2 dgisselq 
                        dropbit ^= 1;
1404 
                        nbits = obits;
1405 
                        tmp_size >>= 1; lgtmp--;
1406 
                }
1407 
 
1408 
                {
1409 
                        int obits = nbits+((dropbit)?0:1);
1410 
                        if (obits > nbitsout)
1411 
                                obits = nbitsout;
1412 
                        if ((maxbitsout>0)&&(obits > maxbitsout))
1413 
                                obits = maxbitsout;
1414 
                        fprintf(vmain, "\twire\t\tw_s2;\n");
1415 
                        fprintf(vmain, "\twire\t[%d:0]\tw_e2, w_o2;\n", 2*obits-1);
1416 6 dgisselq 
                        fprintf(vmain, "\tdblstage\t#(%d,%d,%d)\tstage_2(i_clk, i_rst, i_ce,\n", nbits, obits,dropbit);
1417 
                        fprintf(vmain, "\t\t\t\t\tw_s4, w_e4, w_o4, w_e2, w_o2, w_s2);\n");
1418 2 dgisselq 
 
1419 
                        fprintf(vmain, "\n\n");
1420 
                        nbits = obits;
1421 
                }
1422 
 
1423 
                fprintf(vmain, "\t// Prepare for a (potential) bit-reverse stage.\n");
1424 
                fprintf(vmain, "\tassign\tbr_left  = w_e2;\n");
1425 
                fprintf(vmain, "\tassign\tbr_right = w_o2;\n");
1426 
                fprintf(vmain, "\n");
1427 
                if (bitreverse) {
1428 
                        fprintf(vmain, "\twire\tbr_start;\n");
1429 
                        fprintf(vmain, "\treg\tr_br_started;\n");
1430 
                        fprintf(vmain, "\t// A delay of one clock here is perfect, as it matches the delay in\n");
1431 
                        fprintf(vmain, "\t// our dblstage.\n");
1432 
                        fprintf(vmain, "\talways @(posedge i_clk)\n");
1433 
                        fprintf(vmain, "\t\tif (i_rst)\n");
1434 
                        fprintf(vmain, "\t\t\tr_br_started <= 1'b0;\n");
1435 
                        fprintf(vmain, "\t\telse\n");
1436 
                        fprintf(vmain, "\t\t\tr_br_started <= r_br_started || w_s4;\n");
1437 
                        fprintf(vmain, "\tassign\tbr_start = r_br_started;\n");
1438 
                }
1439 
        }
1440 
 
1441 
        fprintf(vmain, "\n");
1442 
        fprintf(vmain, "\t// Now for the bit-reversal stage.\n");
1443 
        fprintf(vmain, "\twire\tbr_sync;\n");
1444 
        fprintf(vmain, "\twire\t[(2*OWIDTH-1):0]\tbr_o_left, br_o_right;\n");
1445 
        if (bitreverse) {
1446 
                fprintf(vmain, "\tdblreverse\t#(%d,%d)\trevstage(i_clk, i_rst,\n", lgsize, nbitsout);
1447 
                fprintf(vmain, "\t\t\t(i_ce & br_start), br_left, br_right,\n");
1448 
                fprintf(vmain, "\t\t\tbr_o_left, br_o_right, br_sync);\n");
1449 
        } else {
1450 
                fprintf(vmain, "\tassign\tbr_o_left  = br_left;\n");
1451 
                fprintf(vmain, "\tassign\tbr_o_right = br_right;\n");
1452 
                fprintf(vmain, "\tassign\tbr_sync    = w_s2;\n");
1453 
        }
1454 
 
1455 
        fprintf(vmain, "\n\n");
1456 
        fprintf(vmain, "\t// Last clock: Register our outputs, we\'re done.\n");
1457 
        fprintf(vmain, "\talways @(posedge i_clk)\n");
1458 
        fprintf(vmain, "\t\tbegin\n");
1459 
        fprintf(vmain, "\t\t\to_left  <= br_o_left;\n");
1460 
        fprintf(vmain, "\t\t\to_right <= br_o_right;\n");
1461 
        fprintf(vmain, "\t\t\to_sync  <= br_sync;\n");
1462 
        fprintf(vmain, "\t\tend\n");
1463 
        fprintf(vmain, "\n\n");
1464 
        fprintf(vmain, "endmodule\n");
1465 
        fclose(vmain);
1466 
 
1467 
        sprintf(fname, "%s/butterfly.v", coredir);
1468 
        build_butterfly(fname);
1469 
 
1470 
        sprintf(fname, "%s/shiftaddmpy.v", coredir);
1471 
        build_multiply(fname);
1472 
 
1473 
        sprintf(fname, "%s/qtrstage.v", coredir);
1474 
        build_quarters(fname);
1475 
 
1476 
        sprintf(fname, "%s/dblstage.v", coredir);
1477 
        build_dblstage(fname);
1478 
 
1479 
        if (bitreverse) {
1480 
                sprintf(fname, "%s/dblreverse.v", coredir);
1481 
                build_dblreverse(fname);
1482 
        }
1483 
}
1484 
 

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