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unicore |
---------------------------------------------------------------------
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---- ----
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---- DCT IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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entity DCT_BEH is
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generic( SIGNED_DATA: integer);
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port (
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DATAIN: in STD_LOGIC_VECTOR (7 downto 0);
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CLK: in STD_LOGIC;
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RST: in STD_LOGIC;
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EN: in STD_LOGIC;
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START: in STD_LOGIC;
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READY : out STD_LOGIC:='0';
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DATAOUT: out STD_LOGIC_VECTOR ( 11 downto 0) --:=x"0000"
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);
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end DCT_BEH;
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architecture DCT_BEH of DCT_BEH is
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type TLUT2 is array(0 to 255 ) of real;
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type TLUT3 is array(0 to 63 ) of real;
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type TLUT1 is array(0 to 255 ) of std_logic_vector(7 downto 0);
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constant LATENCY:integer:=3; -- 40; --51;
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constant c : real := 0.7071;
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constant c0 : real := 0.9808;
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constant c1 : real := 0.8315;
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constant c2 : real := 0.5556;
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constant c3 : real := 0.1951;
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constant c4 : real := 0.9239;
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constant c5 : real := 0.3827;
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Constant c6 : real := 0.7071;
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constant c0i : real := -0.9808;
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constant c1i : real := -0.8315;
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constant c2i : real := -0.5556;
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constant c3i : real := -0.1951;
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constant c4i : real := -0.9239;
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constant c5i : real := -0.3827;
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Constant c6i : real := -0.7071;
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Constant ROM3:Tlut3:=( (
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c,c,c,c,c,c,c,c,
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c0,c1,c2,c3,c3i,c2i,c1i,c0i,
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c4,c5,c5i,c4i,c4i,c5i,c5,c4,
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c1,c3i,c0i,c2i,c2,c0,c3,c1i,
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c6,c6i,c6i,c6,c6,c6i,c6i,c6,
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c2,c0i,c3,c1,c1i,c3i,c0,c2i,
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c5,c4i,c4,c5i,c5i,c4,c4i,c5,
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c3,c2i,c1,c0i,c0,c1i,c2,c3i
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));
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Constant ROM4:Tlut3:=( (
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c,c0,c4,c1,c6,c2,c5,c3,
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c,c1,c5,c3i,c6i,c0i,c4i,c2i,
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c,c2,c5i,c0i,c6i,c3,c4,c1,
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c,c3,c4i,c2i,c6,c1,c5i,c0i,
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c,c3i,c4i,c2,c6,c1i,c5i,c0,
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c,c2i,c5i,c0,c6i,c3i,c4,c1i,
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c,c1i,c5,c3,c6i,c0,c4i,c2,
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c,c0i,c4,c1i,c6,c2i,c5,c3i
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));
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signal RESET: std_logic;
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signal COEF : STD_LOGIC_VECTOR (6 downto 0);
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signal X,X11,DATAINi: STD_LOGIC_VECTOR (7 downto 0);
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signal Y1,y2: STD_LOGIC_VECTOR (15 downto 0);
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signal Y,DATAOUTi: STD_LOGIC_VECTOR (11 downto 0);
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signal K1,K2,X1,k8,couna: INTEGER;
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signal k3,k4,k7: real;
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signal ram00,ramres,ramt : tlut3;
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signal prov,prov1: std_logic_vector (7 downto 0);
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signal inarray,inarray0,tmpar1,tmpar2,tmpar3: tlut3;
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signal index: integer range 0 to 63;
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signal CLK64,eoutput,indataready,indataready2, startdel,startd1,startd2, startfix,readyi:boolean;
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signal delay,cycle: integer:=0;
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begin
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G1: if SIGNED_DATA=1 generate
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DATAINi<=DATAIN;
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end generate;
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G0: if SIGNED_DATA=0 generate
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DATAINi<=unsigned (DATAIN) - 128;
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end generate;
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DATA_INPUT: process(CLK,RST,START)
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variable index: integer range 0 to 64;
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begin
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if RST='1' or START='1' then
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index:=0; indataready<=false;
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for i in 0 to 63 loop
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inarray0(i)<=0.0;
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end loop;
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elsif CLK='1' and CLK'event then
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if en='1' then
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inarray0(index)<=REAL(CONV_INTEGER(SIGNED(DATAINi)));
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index:=(index+1) mod 64;
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if index=63 then
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indataready<=true;
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else
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indataready<=false;
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end if;
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end if;
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end if;
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end process;
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DATAREADY:process(CLK)
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begin
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if CLK'event and CLK='1' then
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if en='1' then
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indataready2<=indataready;
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if indataready2 then
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inarray<=inarray0;
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end if;
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end if;
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end if;
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end process;
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DCT: process --Discrete Cosine Transform calculation
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variable cc0,cc1,cc2,cc3,cc4,cc5,cc6: real;
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variable ac0,ac1,ac2,ac3,ac4,ac5,ac6,ac7: real;
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variable s,i,j,k: integer;
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begin
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for s in 0 to 7 loop
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for j in 0 to 7 loop
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ac0:= 0.0;
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for i in 0 to 7 loop
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cc0 := rom3(s*8 + i);
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cc1 := (inarray(j + i*8)); -- - 128.0);
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ac0 := ac0 + cc0 * cc1;
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end loop;
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ram00(s*8 +j) <= ac0;
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ramt(j*8 +s)<=ac0/2.0;
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wait for 1 ps;
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end loop;
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end loop;
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wait for 5 ps;
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for s in 0 to 7 loop
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for j in 0 to 7 loop
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ac0:= 0.0;
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for i in 0 to 7 loop
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cc0 := ram00(s*8 + i);
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cc1 := rom3(j*8 + i);
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ac0 := ac0 + cc0 * cc1;
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end loop;
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ramres(s*8 +j) <= ac0/8.0; --results
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wait for 1 ps;
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end loop;
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end loop;
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wait on indataready2;
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end process;
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-- CLK64<= indataready ;
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DATA_OUTPUT:process(CLK,RST,START)
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-- variable delay: integer;
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begin
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if RST='1' or START='1' then
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startfix<=false;
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elsif START='0' and START'event then
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startfix<=true;
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end if;
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if RST='1' or START='1' then
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eoutput<=false;
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startdel<=false;
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delay<=0;
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elsif rising_edge(CLK) and startd2 then
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if en='1' then
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startdel<=(delay=LATENCY); --momemt of 1 st result ready
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delay<=delay+1;
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if startdel then
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eoutput<=true;
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end if;
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end if;
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end if;
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if RST='1' or START='1' then
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cycle<=0;
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readyi<=false;
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elsif rising_edge(CLK) and eoutput then
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if en='1' then
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cycle<=(cycle+1) mod 64;
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end if;
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end if;
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readyi<= cycle = 63 or startdel; -- 63
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if readyi then READY<= '1' ; else READY<= '0'; end if;
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if RST='1' or STARTDel then
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index<=0;
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elsif CLK='1' and CLK'event and eoutput then --
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if en='1' then
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index<=(index+1) mod 64;
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end if;
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end if;
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end process;
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process(clk,rst)
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begin
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if RST='1' or STARTDel then
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DATAOUT<= (others => '0');
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elsif CLK='1' and CLK'event and eoutput then --
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if en='1' then
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DATAOUT<=CONV_STD_LOGIC_VECTOR(INTEGER( tmpar2(index)),12); -- 12
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DATAOUTi<=CONV_STD_LOGIC_VECTOR(INTEGER( ramt((index-14) mod 64)),12); -- 16
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end if;
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end if;
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end process;
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RESULT_ARRAY: process(readyi,CLK)
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begin
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if CLK='1' and CLK'event and readyi then
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if en='1' then
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tmpar2<=tmpar1;
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end if;
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end if;
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end process ;
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DELAYED:process ( indataready2,START,RESET) --delay for 128 cycles
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begin
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if START='1' or RESET='1' then
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startd2<=false;
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startd1<=false;
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elsif indataready2 and indataready2'event then
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if en='1' then
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for i in 0 to 63 loop
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tmpar1(i)<=ramres(i)*2.0; --SCALING !!!
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end loop;
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startd2<=startd1;
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startd1<=STARTFIX;
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end if;
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end if;
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end process;
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end DCT_BEH;
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