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unicore |
---------------------------------------------------------------------
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---- ----
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---- DCT IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- DESCRIPTION:
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--
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-- FUNCTION Discrete Cosine Transform of 8 samples using algorithm by
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-- Arai, Agui, and Nakajama
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-- input data bit width: 8 bit , signed or unsigned
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-- output data bit width: 10 bit
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-- coefficient bit width: 11 bit
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-- Synthesable for FPGAs of any vendor, preferably for Xilinx FPGA
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--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_signed.all;
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entity DCT8AAN1 is
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generic( d_signed:integer:=1;--1 input data signed 0 - unsigned, and for compression 1/2 is subtracted
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scale_out:integer:=1); -- 1 output data are scaled 0 - genuine DCT
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port (
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CLK: in STD_LOGIC;
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RST: in STD_LOGIC;
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START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
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EN: in STD_LOGIC; -- operation enable to slow-down the calculations
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DATA_IN: in STD_LOGIC_VECTOR (7 downto 0);
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RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outputted
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DATA_OUT: out STD_LOGIC_VECTOR (9 downto 0) -- output data
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);
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end DCT8AAN1;
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architecture STAGE of DCT8AAN1 is
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type Tarr8 is array(0 to 7) of STD_LOGIC_VECTOR (10 downto 0);
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type Tarr16 is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0);
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signal sr16:TARR16:=(others=>(others=>'0')); -- SRL16 array
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constant S:Tarr8:=--(0.5/sqrt(2.0), 0.25/cos(pii*1.0),0.25/cos(pii*2.0),0.25/cos(pii*3.0),
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-- 0.25/cos(pii*4.0),0.25/cos(pii*5.0),0.25/cos(pii*6.0),0.25/cos(pii*7.0));
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(conv_std_logic_vector(integer(0.35355*2.0**9),11),
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conv_std_logic_vector(integer(0.2549*2.0**9),11),
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conv_std_logic_vector(integer(0.2706*2.0**9),11),
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conv_std_logic_vector(integer(0.30067*2.0**9),11),
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conv_std_logic_vector(integer(0.35355*2.0**9),11),
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conv_std_logic_vector(integer(0.44999*2.0**9),11),
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conv_std_logic_vector(integer(0.65328*2.0**9),11),
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conv_std_logic_vector(integer(1.2815*2.0**9),11) );
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constant m1 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.70711*2.0**9),11); --cos(pii*4.0); --
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constant m2 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.38268*2.0**9),11);--cos(pii*6.0); --
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constant m3 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(0.5412 *2.0**9),11);--(cos(pii*2.0) - cos(pii*6.0)); --
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constant m4 : STD_LOGIC_VECTOR (10 downto 0) := conv_std_logic_vector(integer(1.3066*2.0**9),11);--cos(pii*2.0) + cos(pii*6.0); --
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constant zeros : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
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constant a1_2 : STD_LOGIC_VECTOR (7 downto 0) := "10"&zeros;
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signal sr: STD_LOGIC_VECTOR (10 downto 0) ;
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signal cycle,ad1,cycle6: integer range 0 to 7;
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signal cycles: integer range 0 to 31;
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signal di,a1,a2,a3,a4: STD_LOGIC_VECTOR (7 downto 0);
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signal bp,bm,b1,b2,b3,b4,b6:STD_LOGIC_VECTOR (8 downto 0);
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signal cp,cm,c1,c2,c3,c4:STD_LOGIC_VECTOR (10 downto 0);
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signal dp,dm:STD_LOGIC_VECTOR (11 downto 0);
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signal rd:STD_LOGIC_VECTOR (11 downto 0);
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signal ep:STD_LOGIC_VECTOR (22 downto 0);
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signal e27:STD_LOGIC_VECTOR (10 downto 0);
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signal m1_4:STD_LOGIC_VECTOR (10 downto 0);
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signal fp,fm,f45,s7,s07,spt:STD_LOGIC_VECTOR (11 downto 0);
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signal SP : STD_LOGIC_VECTOR (22 downto 0);
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begin
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UU_COUN0:process(CLK,RST)
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begin
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if RST = '1' then
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cycle <=0;
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cycle6 <=(-6) mod 8;
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ad1<= ( - 5) mod 8;
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cycles <=16;
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RDY<='0';
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elsif CLK = '1' and CLK'event then
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if en = '1' then
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RDY<='0';
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if START = '1' then
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cycle <=0;
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cycle6 <=(-6) mod 8;
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ad1<= ( - 5) mod 8;
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cycles <=0;
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elsif en = '1' then
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cycle<=(cycle +1) mod 8 ;
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cycle6<=(cycle6 +1) mod 8 ;
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ad1<=(ad1 +1) mod 8;
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if cycles=15 then
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RDY<='1';
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end if;
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if cycles/=17 then
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cycles<=(cycles +1) ;
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end if;
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end if;
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end if;
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end if;
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end process;
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SRL16_a:process(CLK) begin -- SRL16
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if CLK'event and CLK='1' then
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if en='1' and (cycle=1 or cycle=2 or cycle=3 or cycle=4) then
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sr16<=di & sr16(0 to 14); -- shift SRL16
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end if;
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end if;
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end process;
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a1<= sr16(ad1); -- output from SRL16
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SM_B:process(clk,rst)
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begin
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if RST = '1' then
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di <= (others => '0');
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bp <= (others => '0');
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bm <= (others => '0');
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elsif CLK = '1' and CLK'event then
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if en = '1' then
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if d_signed =0 then
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di<=unsigned(DATA_IN) - unsigned( a1_2);
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else
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di<=DATA_IN;
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end if;
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bp<=SXT(di,9) + a1;
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bm<=a1 - SXT(di,9);
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end if;
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end if;
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end process;
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SM_C:process(clk,rst)
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begin
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if RST = '1' then
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b1 <= (others => '0');
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b2 <= (others => '0');
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b3 <= (others => '0');
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b4 <= (others => '0');
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b6 <= (others => '0');
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cp <= (others => '0');
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cm <= (others => '0');
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c1 <= (others => '0');
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elsif CLK = '1' and CLK'event then
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if en = '1' then
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b1<=bp;
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b2<=b1;
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if cycle = 2 then
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b3<=b4;
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else
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b3<=b2;
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end if;
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b4<=b3;
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b6<=bm;
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case cycle is
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when 0|1|7 =>cp<=SXT(bm,11)+b6;
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when 2|3 =>cp<= SXT(b2,11)+b3;
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when others=> cp<=cp+c1;
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end case;
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c1<=cp;
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if cycle=2 or cycle=3 then
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cm<=SXT(b2,11) - b3;
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else
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cm<=cp - c1;
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end if;
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end if;
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end if;
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end process;
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SM_D:process(clk,rst)
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begin
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if RST = '1' then
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c2 <= (others => '0');
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c3 <= (others => '0');
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c4 <= (others => '0');
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--s6 <= (others => '0');
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dp <= (others => '0');
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dm <= (others => '0');
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elsif CLK = '1' and CLK'event then
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if en = '1' then
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if cycle=3 or cycle=4 or cycle=5 then
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c2<=cm;
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end if;
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if cycle = 1 then
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c3<=c1;
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end if;
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if cycle = 2 then
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c4<=SXT(b6,11);
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elsif cycle=5 then
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c4<=c2;
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end if;
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if cycle = 4 then
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dp<= SXT(cm, 12)+c2(10 downto 0);
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else
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dp<= ep(20 downto 9)+c4(10 downto 0);
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end if;
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if cycle = 2 then
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dm<= c3(10 downto 0) - SXT(cp, 12);
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elsif cycle=3 or cycle =7 then
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dm<= c4(10 downto 0) - ep(20 downto 9);
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end if;
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end if;
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end if;
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end process;
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MPU1:process(clk,rst)
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begin
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if CLK = '1' and CLK'event then
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if en = '1' then
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case cycle is
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when 1|5 => m1_4<=m1;
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when 2 => m1_4<=m4;
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when 3 => m1_4<=m2;
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when others => m1_4<=m3;
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end case ;
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case cycle is
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when 1|2 => rd<= SXT(cp,12);
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when 3 => rd<=dm;
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when 4 => rd<= SXT(c3,12);
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when others => rd<=dp;
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end case ;
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ep<=rd*m1_4;
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e27<= ep(19 downto 9);
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end if;
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end if;
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end process;
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SM_F:process(clk,rst)
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begin
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if RST = '1' then
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fp <= (others => '0');
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fm <= (others => '0');
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f45 <= (others => '0');
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s7 <= (others => '0');
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elsif CLK = '1' and CLK'event then
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if en = '1' then
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case cycle is
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when 3 => fp<=ep(19 downto 9) + SXT(c4,12);
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when 5 => fp<=ep(19 downto 9) + SXT(e27,12);
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when 6|0 => fp<=fp + f45;
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when 7 => fp<=e27 +f45;
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when others=> null;
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end case;
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if cycle=4 then
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f45<=fp;
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elsif cycle=6 then
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f45<=SXT(e27,12);
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elsif cycle=7 or cycle=0 then
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f45<=SXT(dm,12);
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end if;
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fm<=f45 - fp;
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if cycle=7 then
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s7<=fm;
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end if;
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end if;
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end if;
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end process;
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MPU2:process(clk,rst)
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| 308 |
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begin
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if CLK = '1' and CLK'event then
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| 310 |
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if en = '1' then
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sr<=s(cycle6);
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case cycle is
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when 6 => s07<= SXT(c1,12);
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when 7|3 => s07<=fp;
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when 0 => s07<= SXT(dp,12);
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when 1 => s07<= SXT(fm,12);
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when 2 => s07<= SXT(c2,12);
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when 4 => s07<= SXT(f45,12);
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when others => s07<=s7;
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end case ;
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| 321 |
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if scale_out =0 then
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|
|
sp<=s07*sr;
|
| 323 |
|
|
DATA_OUT <=sp(18 downto 9);
|
| 324 |
|
|
else
|
| 325 |
|
|
spt<=s07;
|
| 326 |
|
|
DATA_OUT <= spt(10 downto 1);
|
| 327 |
|
|
end if;
|
| 328 |
|
|
end if;
|
| 329 |
|
|
end if;
|
| 330 |
|
|
end process;
|
| 331 |
|
|
|
| 332 |
|
|
|
| 333 |
|
|
end STAGE;
|
