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---------------------------------------------------------------------
----                                                             ----
----  DCT IP core                                                ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
--              DESCRIPTION:
--
--      FUNCTION        2-D Discrete Cosine Transform of  for 8x8 samples using algorithm by
--                                                      Arai, Agui, and Nakajama
--                       input data bit width: 8 bit ,  signed or unsigned
--                       output   data bit width: 12 bit   
--                       coefficient bit width: 11 bit.                                                                                                 
--                      When output data are scaled then the number of multipliers is equal to 2. 
--                      Buffer memories are based on FIFO
--                      Synthesable for  FPGAs of any vendor, preferably for Xilinx FPGA                                         
--      
--      
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity DCT_AAN is
        generic(
                d_signed:integer:=1;    --1 input data signed; 0 - unsigned, and for compression 1/2 is subtracted
                scale_out:integer:=0);              -- 1 output data are scaled; 0 - genuine DCT 
        port(
                CLK : in STD_LOGIC;
                RST : in STD_LOGIC;
                START: in STD_LOGIC;         -- after this impulse the 0-th datum is sampled
                EN: in STD_LOGIC;                    -- operation enable to slow-down the calculations
                DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
                RDY : out STD_LOGIC;
                DATA_OUT : out STD_LOGIC_VECTOR(11 downto 0)
                );
end DCT_AAN;
 
architecture CONSTR of DCT_AAN is
 
        component DCT8AAN1 is
                generic( d_signed:integer:=1;              --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted
                        scale_out:integer:=0);              -- 1 output data are scaled 0 - genuine DCT 
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        START: in STD_LOGIC;         -- after this impulse the 0-th datum is sampled
                        EN: in STD_LOGIC;                    -- operation enable to slow-down the calculations
                        DATA_IN: in STD_LOGIC_VECTOR (7 downto 0);
                        RDY: out   STD_LOGIC;     -- delayed START impulse, after it the 0-th result is outputted
                        DATA_OUT: out STD_LOGIC_VECTOR (9 downto 0) --  output data
                        );
        end  component ;
 
        component DCT8AAN2 is
                generic( d_signed:integer:=1;   --1 input data signed; 0 - unsigned, and for compression 1/2 is subtracted
                        scale_out:integer:=0);              -- 1 output data are scaled; 0 - genuine DCT 
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        START: in STD_LOGIC;         -- after this impulse the 0-th datum is sampled
                        EN: in STD_LOGIC;                    -- operation enable to slow-down the calculations
                        DATA_IN: in STD_LOGIC_VECTOR (9 downto 0);
                        RDY: out   STD_LOGIC;     -- delayed START impulse, after it the 0-th result is outpitted
                        DATA_OUT: out STD_LOGIC_VECTOR (11 downto 0) --  output data
                        );
        end      component;
 
        component DCT_BUF is
                generic( wi: integer:= 10    -- input data width
                        );
                port (
                        CLK: in STD_LOGIC;
                        RST: in STD_LOGIC;
                        START: in STD_LOGIC;         -- after this impulse the 0-th datum is sampled
                        EN: in STD_LOGIC;                    -- operation enable to slow-down the calculations
                        DATA_IN: in STD_LOGIC_VECTOR (wi-1 downto 0);
                        RDY: out   STD_LOGIC;     -- delayed START impulse, after it the 0-th result is outputted
                        DATA_OUT: out STD_LOGIC_VECTOR (wi-1 downto 0) --  output data
                        );
        end     component ;
 
        signal rdy1,rdy2,rdy3 : STD_LOGIC;
        signal data1,data1r: STD_LOGIC_VECTOR (9 downto 0);
        signal data2: STD_LOGIC_VECTOR (11 downto 0);
 
 
begin
 
        U_ST1: DCT8AAN1
        generic map( d_signed=>d_signed,                   --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted
                                scale_out=>scale_out)              -- 1 output data are scaled 0 - genuine DCT 
        port map(CLK, RST,
                                START =>START,       -- after this impulse the 0-th datum is sampled
                                EN =>EN,                     -- operation enable to slow-down the calculations
                                DATA_IN =>DATA_IN,
                                RDY =>rdy1,       -- delayed START impulse, just after it the 0-th result is outputted
                                DATA_OUT=>data1 --  output data
                                );
 
        U_B1:DCT_BUF
        generic map( wi=> 10    -- input data width
                )
        port map(CLK,   RST,
                                START=>rdy1,     -- after this impulse the 0-th datum is sampled
                                EN=>EN,              -- operation enable to slow-down the calculations
                                DATA_IN=>data1,
                                RDY=>rdy2,        -- delayed START impulse, after it the 0-th result is outputted
                                DATA_OUT=>data1r --  output data
                                );
 
        U_ST2: DCT8AAN2
        generic map( d_signed=>1,                  --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted
                                scale_out=>scale_out)              -- 1 output data are scaled 0 - genuine DCT 
        port map(CLK, RST,
                                START =>rdy2,        -- after this impulse the 0-th datum is sampled
                                EN =>EN,                     -- operation enable to slow-down the calculations
                                DATA_IN =>data1r,
                                RDY =>rdy3,       -- delayed START impulse, after it the 0-th result is outputted
                                DATA_OUT=>data2 --  output data
                                );
 
        U_B2:DCT_BUF
        generic map( wi=> 12    -- input data width
                )
        port map(CLK,   RST,
                                START=>rdy3,     -- after this impulse the 0-th datum is sampled
                                EN=>EN,              -- operation enable to slow-down the calculations
                                DATA_IN=>data2,
                                RDY=>RDY,         -- delayed START impulse, after it the 0-th result is outputted
                                DATA_OUT=>DATA_OUT --  output data
                                );
 
 
end CONSTR;

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- DCT IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
40			`-- DESCRIPTION:`
41			`--`
42			`-- FUNCTION 2-D Discrete Cosine Transform of for 8x8 samples using algorithm by`
43			`-- Arai, Agui, and Nakajama`
44			`-- input data bit width: 8 bit , signed or unsigned`
45			`-- output data bit width: 12 bit`
46			`-- coefficient bit width: 11 bit.`
47			`-- When output data are scaled then the number of multipliers is equal to 2.`
48			`-- Buffer memories are based on FIFO`
49			`-- Synthesable for FPGAs of any vendor, preferably for Xilinx FPGA`
50			`--`
51			`--`
52			`--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
53
54
55			`library IEEE;`
56			`use IEEE.STD_LOGIC_1164.all;`
57
58			`entity DCT_AAN is`
59			`generic(`
60			`d_signed:integer:=1; --1 input data signed; 0 - unsigned, and for compression 1/2 is subtracted`
61			`scale_out:integer:=0); -- 1 output data are scaled; 0 - genuine DCT`
62			`port(`
63			`CLK : in STD_LOGIC;`
64			`RST : in STD_LOGIC;`
65			`START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled`
66			`EN: in STD_LOGIC; -- operation enable to slow-down the calculations`
67			`DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);`
68			`RDY : out STD_LOGIC;`
69			`DATA_OUT : out STD_LOGIC_VECTOR(11 downto 0)`
70			`);`
71			`end DCT_AAN;`
72
73			`architecture CONSTR of DCT_AAN is`
74
75			`component DCT8AAN1 is`
76			`generic( d_signed:integer:=1; --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted`
77			`scale_out:integer:=0); -- 1 output data are scaled 0 - genuine DCT`
78			`port (`
79			`CLK: in STD_LOGIC;`
80			`RST: in STD_LOGIC;`
81			`START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled`
82			`EN: in STD_LOGIC; -- operation enable to slow-down the calculations`
83			`DATA_IN: in STD_LOGIC_VECTOR (7 downto 0);`
84			`RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outputted`
85			`DATA_OUT: out STD_LOGIC_VECTOR (9 downto 0) -- output data`
86			`);`
87			`end component ;`
88
89			`component DCT8AAN2 is`
90			`generic( d_signed:integer:=1; --1 input data signed; 0 - unsigned, and for compression 1/2 is subtracted`
91			`scale_out:integer:=0); -- 1 output data are scaled; 0 - genuine DCT`
92			`port (`
93			`CLK: in STD_LOGIC;`
94			`RST: in STD_LOGIC;`
95			`START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled`
96			`EN: in STD_LOGIC; -- operation enable to slow-down the calculations`
97			`DATA_IN: in STD_LOGIC_VECTOR (9 downto 0);`
98			`RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outpitted`
99			`DATA_OUT: out STD_LOGIC_VECTOR (11 downto 0) -- output data`
100			`);`
101			`end component;`
102
103			`component DCT_BUF is`
104			`generic( wi: integer:= 10 -- input data width`
105			`);`
106			`port (`
107			`CLK: in STD_LOGIC;`
108			`RST: in STD_LOGIC;`
109			`START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled`
110			`EN: in STD_LOGIC; -- operation enable to slow-down the calculations`
111			`DATA_IN: in STD_LOGIC_VECTOR (wi-1 downto 0);`
112			`RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outputted`
113			`DATA_OUT: out STD_LOGIC_VECTOR (wi-1 downto 0) -- output data`
114			`);`
115			`end component ;`
116
117			`signal rdy1,rdy2,rdy3 : STD_LOGIC;`
118			`signal data1,data1r: STD_LOGIC_VECTOR (9 downto 0);`
119			`signal data2: STD_LOGIC_VECTOR (11 downto 0);`
120
121
122			`begin`
123
124			`U_ST1: DCT8AAN1`
125			`generic map( d_signed=>d_signed, --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted`
126			`scale_out=>scale_out) -- 1 output data are scaled 0 - genuine DCT`
127			`port map(CLK, RST,`
128			`START =>START, -- after this impulse the 0-th datum is sampled`
129			`EN =>EN, -- operation enable to slow-down the calculations`
130			`DATA_IN =>DATA_IN,`
131			`RDY =>rdy1, -- delayed START impulse, just after it the 0-th result is outputted`
132			`DATA_OUT=>data1 -- output data`
133			`);`
134
135			`U_B1:DCT_BUF`
136			`generic map( wi=> 10 -- input data width`
137			`)`
138			`port map(CLK, RST,`
139			`START=>rdy1, -- after this impulse the 0-th datum is sampled`
140			`EN=>EN, -- operation enable to slow-down the calculations`
141			`DATA_IN=>data1,`
142			`RDY=>rdy2, -- delayed START impulse, after it the 0-th result is outputted`
143			`DATA_OUT=>data1r -- output data`
144			`);`
145
146			`U_ST2: DCT8AAN2`
147			`generic map( d_signed=>1, --1 input data signed 0 - unsigned, and for compression 1/2 is subtracted`
148			`scale_out=>scale_out) -- 1 output data are scaled 0 - genuine DCT`
149			`port map(CLK, RST,`
150			`START =>rdy2, -- after this impulse the 0-th datum is sampled`
151			`EN =>EN, -- operation enable to slow-down the calculations`
152			`DATA_IN =>data1r,`
153			`RDY =>rdy3, -- delayed START impulse, after it the 0-th result is outputted`
154			`DATA_OUT=>data2 -- output data`
155			`);`
156
157			`U_B2:DCT_BUF`
158			`generic map( wi=> 12 -- input data width`
159			`)`
160			`port map(CLK, RST,`
161			`START=>rdy3, -- after this impulse the 0-th datum is sampled`
162			`EN=>EN, -- operation enable to slow-down the calculations`
163			`DATA_IN=>data2,`
164			`RDY=>RDY, -- delayed START impulse, after it the 0-th result is outputted`
165			`DATA_OUT=>DATA_OUT -- output data`
166			`);`
167
168
169			`end CONSTR;`

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[/] [dct_idct/] [trunk/] [dct/] [RTL/] [DCT_AAN.vhd] - Blame information for rev 2