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unicore |
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---- ----
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---- DCT IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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--DESCRIPTION:
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--
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-- FUNCTION 64 data are stored to the FIFO buffer
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-- 64 data read from FIFO taps in the transposed order.
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-- Synthesable for Xilinx FPGAs.
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--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_signed.all;
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entity DCT_BUF is
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generic( wi: integer:= 10 -- input data width
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);
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port (
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CLK: in STD_LOGIC;
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RST: in STD_LOGIC;
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START: in STD_LOGIC; -- after this impulse the 0-th datum is sampled
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EN: in STD_LOGIC; -- operation enable to slow-down the calculations
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DATA_IN: in STD_LOGIC_VECTOR (wi-1 downto 0);
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RDY: out STD_LOGIC; -- delayed START impulse, after it the 0-th result is outputted
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DATA_OUT: out STD_LOGIC_VECTOR (wi-1 downto 0) -- output data
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);
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end DCT_BUF;
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architecture SRL16 of DCT_BUF is
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constant rnd: STD_LOGIC:='0';
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type Tarr100 is array (0 to 99) of STD_LOGIC_VECTOR (wi -1 downto 0);
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type Tarr64i is array (0 to 63) of integer range 0 to 127 ;
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constant Addrr:Tarr64i:=
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(49,50-8, 51-16,52-24, 53-32,54-40,55-48,56-56,
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56, 57-8, 58-16,59-24, 60-32,61-40,62-48,63-56,
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63, 64-8, 65-16,66-24, 67-32,68-40,69-48,70-56,
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70, 71-8, 72-16,73-24, 74-32,75-40,76-48,77-56,
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77, 78-8, 79-16,80-24, 81-32,82-40,83-48,84-56,
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84, 85-8, 86-16,87-24, 88-32,89-40,90-48,91-56,
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91, 92-8, 93-16,94-24, 95-32,96-40,97-48,98-56,
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98, 99-8,100-16,101-24,102-32,103-40,104-48,105-56);
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signal sr64:TARR100:=(others=>(others=>'0')); -- масив регiстрiв SRL16
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signal cycle,ad1: integer range 0 to 63;
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signal ad2: integer range 0 to 99;
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signal cycles: integer range 0 to 63;
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begin
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UU_COUN:process(CLK,RST)
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begin
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if RST = '1' then
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ad1<= ( - 5) mod 64;
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cycles <=63;
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RDY<='0';
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elsif CLK = '1' and CLK'event then
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if en = '1' then
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RDY<='0';
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if START = '1' then
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ad1<= ( - 48) mod 64;
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cycles <=0;
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elsif en = '1' then
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ad1<=(ad1 +1) mod 64;
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RDY<='0';
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if cycles/=63 then
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cycles<=(cycles +1) ;
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end if;
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if cycles=48 then
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RDY<='1';
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ad1 <=0;
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end if;
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end if;
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end if;
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end if;
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end process;
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SRL16_a:process(CLK) begin -- SRL16
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if CLK'event and CLK='1' then
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if en='1' then
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sr64<=DATA_IN & sr64(0 to 98); -- shift SRL16
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ad2<= Addrr(ad1) ; --FIFO address recoding
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end if;
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end if;
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end process;
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DATA_OUT <=sr64(ad2); -- output from SRL16
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end SRL16;
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