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john_fpga |
---------------------------------------------------------------------
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-- File : DDR2_Control_VHDL.vhd
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-- Projekt : Prj_12_DDR2
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-- Zweck : DDR2-Verwaltung (Init,Read,Write)
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-- Datum : 19.08.2011
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-- Version : 2.0
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-- Plattform : XILINX Spartan-3A
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-- FPGA : XC3S700A-FGG484
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-- Sprache : VHDL
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-- ISE : ISE-Design-Suite V:13.1
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-- Autor : UB
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-- Mail : Becker_U(at)gmx.de
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---------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--------------------------------------------
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-- Beschreibung :
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--
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-- das DDR2-RAM hat 512 MBit (64MByte) Speicherplatz
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-- organisiert in 16Bit Woertern
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--
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-- es werden immer Datenworte von 64Bit ausgelesen
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-- oder geschrieben (weil der Burst-Mode auf 4 steht)
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-- aus dem Grund ist der Daten-Vektor für Read/Write
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-- 64Bit breit
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--
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-- das RAM ist ein 4 Blöcke unterteilt (zu je 16Mbyte)
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-- Bank "00" bis Bank "11" : 2Bit
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--
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-- jeder Block ist in 8192 Reihen zu je 1024 Spalten organisiert
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-- ROW "0000000000000" bis "1111111111111" : 13Bit
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-- COL "0000000000" bis "1111111111" : 10Bit
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--
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-- die übergebene Adresse an die FIFO Komponente
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-- mit 25 Bit setzt sich dann so zusammen
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--
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-- input_adress = ROW & COL & BANK
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-- (25Bit) 13Bit 10Bit 2Bit
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-- pro Adresse stehen 16bit Daten
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--
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-- in diesem Demo-Programm wird nur Bank=0
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-- COL=0 und ROW= 0 bis 15 benutzt
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---------------------------------------------
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--
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-- das CONTROL steuert die READ und WRITE funktion
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-- je nachdem welcher Button gedrückt wurde
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--
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--------------------------------------------
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-- Vorsicht !! zur Adressierung :
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-- Der Burst-Mode steht FIX auf "4"
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-- damit werden IMMER 4 (16bit) Zellen gelesen
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-- und beschrieben (also imer 64Bit)
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--
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-- wenn also das 64bit Wort "123456789ABCDEF0" in Adr 0
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-- geschrieben wird, sieht der Speicher danach so aus :
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-- Row 0 Col 0 = "1234"
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-- Row 0 Col 1 = "5678"
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-- Row 0 Col 2 = "9ABC"
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-- Row 0 Col 3 = "DEF0"
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--
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-- Der Col-Counter muss also immer um 4 Adressen
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-- incrementiert / decrementiert werden
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--
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-- in der Demo hier wird nur der ROW-Counter verändert
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--
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--------------------------------------------
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entity DDR2_Control_VHDL is
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--------------------------------------------
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-- Port Deklerationen
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--------------------------------------------
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port (
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reset_in : in std_logic;
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clk_in : in std_logic;
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clk90_in : in std_logic;
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init_done : in std_logic;
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command_register : out std_logic_vector(2 downto 0);
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input_adress : out std_logic_vector(24 downto 0);
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input_data : out std_logic_vector(31 downto 0);
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output_data : in std_logic_vector(31 downto 0);
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cmd_ack : in std_logic;
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data_valid : in std_logic;
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burst_done : out std_logic;
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auto_ref_req : in std_logic;
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debounce_in : in std_logic_vector(7 downto 0);
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risingedge_in : in std_logic_vector(3 downto 0);
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data_out : out std_logic_vector(7 downto 0)
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);
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end DDR2_Control_VHDL;
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architecture Verhalten of DDR2_Control_VHDL is
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--------------------------------------------
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-- Einbinden einer Componente
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-- zum schreiben eines 64Bit Wertes
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--------------------------------------------
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COMPONENT DDR2_Write_VHDL
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PORT (
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reset_in : in std_logic;
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clk_in : in std_logic;
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clk90_in : in std_logic;
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w_command_register : out std_logic_vector(2 downto 0);
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w_cmd_ack : in std_logic;
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w_burst_done : out std_logic;
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write_en : in std_logic;
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write_busy : out std_logic;
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input_data : out std_logic_vector(31 downto 0);
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write_data : in std_logic_vector(63 downto 0)
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);
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END COMPONENT DDR2_Write_VHDL;
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--------------------------------------------
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-- Einbinden einer Componente
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-- zum lesen eines 64Bit Wertes
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--------------------------------------------
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COMPONENT DDR2_Read_VHDL
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PORT (
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reset_in : in std_logic;
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clk_in : in std_logic;
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clk90_in : in std_logic;
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r_command_register : out std_logic_vector(2 downto 0);
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r_cmd_ack : in std_logic;
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r_burst_done : out std_logic;
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r_data_valid : in std_logic;
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read_en : in std_logic;
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read_busy : out std_logic;
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output_data : in std_logic_vector(31 downto 0);
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read_data : out std_logic_vector(63 downto 0)
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);
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END COMPONENT DDR2_Read_VHDL;
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--------------------------------------------
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-- Interne Signale
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--------------------------------------------
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constant INIT_PAUSE : integer := 133000; -- pause 1ms (Wichtig !!)
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signal v_counter : natural range 0 to INIT_PAUSE := INIT_PAUSE;
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--------------------------------------------
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-- 16 Konstante Werte erzeugen, die beim INIT
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-- (Auto-Write) ins RAM geschrieben werden
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-- ein Wert ist 64Bit = 8 Byte breit
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--------------------------------------------
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constant MAX_ADR : integer := 15; -- 0 bis 15 = 16 Werte
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type RAM_DATA_TYP is array (0 to MAX_ADR) of std_logic_vector(63 downto 0);
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constant RAM_DATA : RAM_DATA_TYP :=
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(
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x"0123456789ABCDEF", x"123456789ABCDEF0", x"23456789ABCDEF01", x"3456789ABCDEF012",
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x"456789ABCDEF0123", x"56789ABCDEF01234", others => (x"639CC6398C7318E7")
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);
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signal v_array_pos : natural range 0 to MAX_ADR+1 := 0;
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--------------------------------------------
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-- Definition der ROW,COL,BANK adressen
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--------------------------------------------
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signal v_ROW : std_logic_vector(12 downto 0):= (others => '0'); -- 13Bit
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signal v_COL : std_logic_vector(9 downto 0):= (others => '0'); -- 10Bit
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signal v_BANK : std_logic_vector(1 downto 0):= (others => '0'); -- 2Bit
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-- zwischenspeicher fuer daten
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signal v_write_data : std_logic_vector(63 downto 0):= (others => '0');
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signal v_read_data : std_logic_vector(63 downto 0):= (others => '0');
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--------------------------------------------
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-- Ein Konstanter Wert, der mit WRITE-Button
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-- ins RAM geschrieben wird
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--------------------------------------------
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constant CONST_DATA : std_logic_vector(63 downto 0):= x"31CE629DC43B8877";
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--------------------------------------------
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-- State-Machine-Typen
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--------------------------------------------
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type STATE_M_TYPE is (
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M1_START_UP,
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M2_WAIT_4_DONE,
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M3_AUTO_WRITE_START,
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M4_AUTO_WRITE_INIT,
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M5_AUTO_WRITING,
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M6_AUTO_READ_INIT,
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M7_AUTO_READING,
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M8_NOP,
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M9_WRITE_INIT,
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M10_WRITING,
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M11_READ_INIT,
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M12_READING
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);
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signal STATE_M : STATE_M_TYPE := M1_START_UP;
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--------------------------------------------
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-- sonstige Signale
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--------------------------------------------
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signal v_write_en : std_logic:='0'; -- '1'=chip-select
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signal v_read_en : std_logic:='0'; -- '1'=chip-select
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signal v_write_busy : std_logic; -- '1'=belegt, '0'=frei
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signal v_read_busy : std_logic; -- '1'=belegt, '0'=frei
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signal v_main_command_register : std_logic_vector(2 downto 0):= (others => '0');
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signal v_write_command_register : std_logic_vector(2 downto 0):= (others => '0');
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signal v_read_command_register : std_logic_vector(2 downto 0):= (others => '0');
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signal v_write_burst_done : std_logic;
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signal v_read_burst_done : std_logic;
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begin
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--------------------------------------------------
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-- Instantz einer Componente erzeugen und verbinden
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-- zum schreiben eines 64Bit Wertes
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--------------------------------------------------
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INST_DDR2_Write_VHDL : DDR2_Write_VHDL
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PORT MAP (
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reset_in => reset_in,
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clk_in => clk_in,
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clk90_in => clk90_in,
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w_command_register => v_write_command_register,
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w_cmd_ack => cmd_ack,
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w_burst_done => v_write_burst_done,
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write_en => v_write_en,
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write_busy => v_write_busy,
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input_data => input_data,
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write_data => v_write_data
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);
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--------------------------------------------------
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-- Instantz einer Componente erzeugen und verbinden
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-- zum lesen eines 64Bit Wertes
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--------------------------------------------------
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INST_DDR2_Read_VHDL : DDR2_Read_VHDL
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PORT MAP (
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reset_in => reset_in,
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clk_in => clk_in,
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clk90_in => clk90_in,
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r_command_register => v_read_command_register,
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r_cmd_ack => cmd_ack,
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r_burst_done => v_read_burst_done,
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r_data_valid => data_valid,
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read_en => v_read_en,
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read_busy => v_read_busy,
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output_data => output_data,
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read_data => v_read_data
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);
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-----------------------------------------
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-- State-Machine :
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-- 1. wartet nach Reset 1ms
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-- 2. sendet das INIT-Kommando an das RAM
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-- 3. Wartet auf das INIT_DONE vom RAM
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-- 4. Schreiben von 16 Datenwerten ins RAM
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-- 5. Auslesen von Adr0
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-- 6. Warte auf Tastendrück
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--
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-- 7a. North/South = ändern der Adresse (ROW)
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-- 7b. East = auslesen eines Wertes
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-- 7c. West = schreiben eines Wertes
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-- 8. Sprung zu Punkt 6
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-----------------------------------------
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P_State_Main : process(clk_in,reset_in)
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begin
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if reset_in = '1' then
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-- reset button ist gedrueckt
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STATE_M <= M1_START_UP;
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v_write_en <= '0';
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v_read_en <= '0';
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v_main_command_register <= "000"; -- NOP
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v_counter <= INIT_PAUSE;
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v_ROW <= (others => '0');
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v_COL <= (others => '0');
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v_BANK <= (others => '0');
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v_array_pos <= 0;
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elsif falling_edge(clk_in) then
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case STATE_M is
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-----------------------------------------------------
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-- INITIALISIERUNG vom RAM : WICHTIG !! :
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-- nach dem Reset wird 1ms gewartet und danach
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-- wird das INIT-Kommando an das RAM gesendet
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-- und auf das Init-Done-Signal vom RAM gewartet
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-----------------------------------------------------
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when M1_START_UP =>
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-- warte 1ms nach Reset bis RAM bereit
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-- WICHTIG !! das steht so im Datasheet
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if v_counter = 0 then
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-- nach 1ms INIT-Kommando (für einen Clock) anlegen
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STATE_M <= M2_WAIT_4_DONE;
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v_main_command_register <= "010"; -- INIT-CMD
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else
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v_main_command_register <= "000"; -- NOP
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v_counter <= v_counter - 1;
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end if;
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when M2_WAIT_4_DONE =>
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-- warte auf Init-Done-Signal vom RAM
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v_main_command_register <= "000"; -- NOP
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if (init_done = '1') then
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-- das RAM ist jetzt bereit
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STATE_M <= M3_AUTO_WRITE_START;
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end if;
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-----------------------------------------------------
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-- automatisches schreiben von ein paar Werten :
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-- es werden 16 feste Datenwerte in die Adressen 0-15
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-- ins RAM geschrieben
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-----------------------------------------------------
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when M3_AUTO_WRITE_START =>
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-- automatisches schreiben von daten ins RAM
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if v_array_pos > MAX_ADR then
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-- wenn alle adressen geschrieben sind
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STATE_M <= M6_AUTO_READ_INIT;
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v_ROW <= (others => '0');
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else
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if v_write_busy = '0' and auto_ref_req = '0' then
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-- wenn RAM nicht beschäftigt ist, starte das schreiben
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STATE_M <= M4_AUTO_WRITE_INIT;
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end if;
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end if;
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when M4_AUTO_WRITE_INIT =>
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-- warten bis zum schreiben bereit
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if v_write_busy = '0' and v_write_en='0' then
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-- daten zum schreiben freigeben
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|
|
v_write_en <= '1';
|
| 323 |
|
|
elsif v_write_busy = '1' and v_write_en='1' then
|
| 324 |
|
|
-- daten werden geschrieben
|
| 325 |
|
|
v_write_en <= '0';
|
| 326 |
|
|
STATE_M <= M5_AUTO_WRITING;
|
| 327 |
|
|
end if;
|
| 328 |
|
|
when M5_AUTO_WRITING =>
|
| 329 |
|
|
-- warte bis schreiben fertig
|
| 330 |
|
|
if v_write_busy = '0' then
|
| 331 |
|
|
-- naechste adresse beschreiben
|
| 332 |
|
|
v_array_pos <= v_array_pos +1;
|
| 333 |
|
|
v_ROW <= v_ROW +1;
|
| 334 |
|
|
STATE_M <= M3_AUTO_WRITE_START;
|
| 335 |
|
|
end if;
|
| 336 |
|
|
-----------------------------------------------------
|
| 337 |
|
|
-- automatisches lesen von einem Wert :
|
| 338 |
|
|
-- es wird der Inhalt von Adr 0 vom RAM ausgelesen
|
| 339 |
|
|
-----------------------------------------------------
|
| 340 |
|
|
when M6_AUTO_READ_INIT =>
|
| 341 |
|
|
-- automatisches lesen vom RAM (ein wert)
|
| 342 |
|
|
-- warten bis zum lesen bereit
|
| 343 |
|
|
if v_read_busy = '0' and v_read_en='0' and auto_ref_req = '0' then
|
| 344 |
|
|
-- daten zum lesen freigeben
|
| 345 |
|
|
v_read_en <= '1';
|
| 346 |
|
|
elsif v_read_busy = '1' and v_read_en='1' then
|
| 347 |
|
|
-- daten werden gelesen
|
| 348 |
|
|
v_read_en <= '0';
|
| 349 |
|
|
STATE_M <= M7_AUTO_READING;
|
| 350 |
|
|
end if;
|
| 351 |
|
|
when M7_AUTO_READING =>
|
| 352 |
|
|
-- warte bis lesen fertig
|
| 353 |
|
|
if v_read_busy = '0' then
|
| 354 |
|
|
STATE_M <= M8_NOP;
|
| 355 |
|
|
end if;
|
| 356 |
|
|
-----------------------------------------------------
|
| 357 |
|
|
-- Dauerloop : warten auf User-Eingabe :
|
| 358 |
|
|
-- hier wird gewartet, bis einer der 4 Buttons
|
| 359 |
|
|
-- gedrückt wurde
|
| 360 |
|
|
-----------------------------------------------------
|
| 361 |
|
|
when M8_NOP =>
|
| 362 |
|
|
-- warte auf Taste fuer READ oder WRITE
|
| 363 |
|
|
v_write_en <= '0';
|
| 364 |
|
|
v_read_en <= '0';
|
| 365 |
|
|
if risingedge_in(3) = '1' and v_write_busy = '0' and auto_ref_req = '0' then
|
| 366 |
|
|
-- button = west
|
| 367 |
|
|
-- write starten (nur wenn nicht busy und kein refresh-zyklus)
|
| 368 |
|
|
STATE_M <= M9_WRITE_INIT;
|
| 369 |
|
|
elsif risingedge_in(0) = '1' and v_read_busy = '0' and auto_ref_req = '0' then
|
| 370 |
|
|
-- button = east
|
| 371 |
|
|
-- read starten (nur wenn nicht busy und kein refresh-zyklus)
|
| 372 |
|
|
STATE_M <= M11_READ_INIT;
|
| 373 |
|
|
end if;
|
| 374 |
|
|
-- warte auf Taste fuer Adr-Up oder Adr-Down
|
| 375 |
|
|
if risingedge_in(1)='1' and v_ROW < 255 then
|
| 376 |
|
|
-- button = north
|
| 377 |
|
|
v_ROW <= v_ROW + 1;
|
| 378 |
|
|
elsif risingedge_in(2)='1' and v_ROW > 0 then
|
| 379 |
|
|
-- button = south
|
| 380 |
|
|
v_ROW <= v_ROW - 1;
|
| 381 |
|
|
end if;
|
| 382 |
|
|
-----------------------------------------------------
|
| 383 |
|
|
-- WRITE : schreiben eines Wertes ins RAM :
|
| 384 |
|
|
-- ein fester Datenwert wird in die aktuelle Adresse
|
| 385 |
|
|
-- ins RAM geschrieben
|
| 386 |
|
|
-----------------------------------------------------
|
| 387 |
|
|
when M9_WRITE_INIT =>
|
| 388 |
|
|
-- warten bis zum schreiben bereit
|
| 389 |
|
|
if v_write_busy = '0' and v_write_en='0' then
|
| 390 |
|
|
-- daten zum schreiben freigeben
|
| 391 |
|
|
v_write_en <= '1';
|
| 392 |
|
|
elsif v_write_busy = '1' and v_write_en='1' then
|
| 393 |
|
|
-- daten werden geschrieben
|
| 394 |
|
|
v_write_en <= '0';
|
| 395 |
|
|
STATE_M <= M10_WRITING;
|
| 396 |
|
|
end if;
|
| 397 |
|
|
when M10_WRITING =>
|
| 398 |
|
|
-- warte bis schreiben fertig
|
| 399 |
|
|
if v_write_busy = '0' then
|
| 400 |
|
|
STATE_M <= M8_NOP;
|
| 401 |
|
|
end if;
|
| 402 |
|
|
-----------------------------------------------------
|
| 403 |
|
|
-- READ : lesen eines Wertes vom RAM :
|
| 404 |
|
|
-- die aktuelle Adresse vom RAM wird ausgelesen
|
| 405 |
|
|
-----------------------------------------------------
|
| 406 |
|
|
when M11_READ_INIT =>
|
| 407 |
|
|
-- warten bis zum lesen bereit
|
| 408 |
|
|
if v_read_busy = '0' and v_read_en='0' then
|
| 409 |
|
|
-- daten zum lesen freigeben
|
| 410 |
|
|
v_read_en <= '1';
|
| 411 |
|
|
elsif v_read_busy = '1' and v_read_en='1' then
|
| 412 |
|
|
-- daten werden gelesen
|
| 413 |
|
|
v_read_en <= '0';
|
| 414 |
|
|
STATE_M <= M12_READING;
|
| 415 |
|
|
end if;
|
| 416 |
|
|
when M12_READING =>
|
| 417 |
|
|
-- warte bis lesen fertig
|
| 418 |
|
|
if v_read_busy = '0' then
|
| 419 |
|
|
STATE_M <= M8_NOP;
|
| 420 |
|
|
end if;
|
| 421 |
|
|
when others =>
|
| 422 |
|
|
NULL;
|
| 423 |
|
|
end case;
|
| 424 |
|
|
end if;
|
| 425 |
|
|
end process P_State_Main;
|
| 426 |
|
|
|
| 427 |
|
|
-----------------------------------------
|
| 428 |
|
|
-- Weiterleitung von Signalen
|
| 429 |
|
|
-- in Abhängigkeit von Read oder Write :
|
| 430 |
|
|
-----------------------------------------
|
| 431 |
|
|
P_SIGNAL : process(clk_in)
|
| 432 |
|
|
begin
|
| 433 |
|
|
if falling_edge(clk_in) then
|
| 434 |
|
|
if STATE_M=M4_AUTO_WRITE_INIT or STATE_M=M5_AUTO_WRITING then
|
| 435 |
|
|
-----------------------------------------------------
|
| 436 |
|
|
-- automatisches schreiben von ein paar Werten
|
| 437 |
|
|
-----------------------------------------------------
|
| 438 |
|
|
v_write_data <= RAM_DATA(v_array_pos);
|
| 439 |
|
|
input_adress <= v_ROW & v_COL & v_BANK;
|
| 440 |
|
|
command_register <= v_write_command_register;
|
| 441 |
|
|
burst_done <= v_write_burst_done;
|
| 442 |
|
|
elsif STATE_M=M6_AUTO_READ_INIT or STATE_M=M7_AUTO_READING then
|
| 443 |
|
|
-----------------------------------------------------
|
| 444 |
|
|
-- automatisches lesen von einem Wert
|
| 445 |
|
|
-----------------------------------------------------
|
| 446 |
|
|
v_write_data <= (others => '0');
|
| 447 |
|
|
input_adress <= v_ROW & v_COL & v_BANK;
|
| 448 |
|
|
command_register <= v_read_command_register;
|
| 449 |
|
|
burst_done <= v_read_burst_done;
|
| 450 |
|
|
elsif STATE_M=M9_WRITE_INIT or STATE_M=M10_WRITING then
|
| 451 |
|
|
-----------------------------------------------------
|
| 452 |
|
|
-- WRITE : schreiben eines Wertes ins RAM
|
| 453 |
|
|
-----------------------------------------------------
|
| 454 |
|
|
v_write_data <= CONST_DATA;
|
| 455 |
|
|
input_adress <= v_ROW & v_COL & v_BANK;
|
| 456 |
|
|
command_register <= v_write_command_register;
|
| 457 |
|
|
burst_done <= v_write_burst_done;
|
| 458 |
|
|
elsif STATE_M=M11_READ_INIT or STATE_M=M12_READING then
|
| 459 |
|
|
-----------------------------------------------------
|
| 460 |
|
|
-- READ : lesen eines Wertes vom RAM
|
| 461 |
|
|
-----------------------------------------------------
|
| 462 |
|
|
v_write_data <= (others => '0');
|
| 463 |
|
|
input_adress <= v_ROW & v_COL & v_BANK;
|
| 464 |
|
|
command_register <= v_read_command_register;
|
| 465 |
|
|
burst_done <= v_read_burst_done;
|
| 466 |
|
|
else
|
| 467 |
|
|
-----------------------------------------------------
|
| 468 |
|
|
-- Dauerloop oder INIT
|
| 469 |
|
|
-----------------------------------------------------
|
| 470 |
|
|
v_write_data <= (others => '0');
|
| 471 |
|
|
input_adress <= (others => '0');
|
| 472 |
|
|
command_register <= v_main_command_register;
|
| 473 |
|
|
burst_done <= '0';
|
| 474 |
|
|
end if;
|
| 475 |
|
|
end if;
|
| 476 |
|
|
end process P_SIGNAL;
|
| 477 |
|
|
|
| 478 |
|
|
-----------------------------------------
|
| 479 |
|
|
-- Ausgabe der gelesenen Daten
|
| 480 |
|
|
-- je nach Schalterstellung
|
| 481 |
|
|
-----------------------------------------
|
| 482 |
|
|
P_DataOut : process(clk_in,reset_in)
|
| 483 |
|
|
begin
|
| 484 |
|
|
if reset_in = '1' then
|
| 485 |
|
|
-- reset button ist gedrueckt
|
| 486 |
|
|
data_out <= (others => '0');
|
| 487 |
|
|
elsif falling_edge(clk_in) then
|
| 488 |
|
|
if debounce_in(7 downto 5)="000" then data_out <= v_read_data(7 downto 0);
|
| 489 |
|
|
elsif debounce_in(7 downto 5)="001" then data_out <= v_read_data(15 downto 8);
|
| 490 |
|
|
elsif debounce_in(7 downto 5)="010" then data_out <= v_read_data(23 downto 16);
|
| 491 |
|
|
elsif debounce_in(7 downto 5)="011" then data_out <= v_read_data(31 downto 24);
|
| 492 |
|
|
elsif debounce_in(7 downto 5)="100" then data_out <= v_read_data(39 downto 32);
|
| 493 |
|
|
elsif debounce_in(7 downto 5)="101" then data_out <= v_read_data(47 downto 40);
|
| 494 |
|
|
elsif debounce_in(7 downto 5)="110" then data_out <= v_read_data(55 downto 48);
|
| 495 |
|
|
elsif debounce_in(7 downto 5)="111" then data_out <= v_read_data(63 downto 56);
|
| 496 |
|
|
end if;
|
| 497 |
|
|
-------------------------------------------
|
| 498 |
|
|
end if;
|
| 499 |
|
|
end process P_DataOut;
|
| 500 |
|
|
|
| 501 |
|
|
end Verhalten;
|
| 502 |
|
|
|
