URL
https://opencores.org/ocsvn/ddr2_sdram/ddr2_sdram/trunk
[/] [ddr2_sdram/] [trunk/] [Top_Modul_VHDL_bitgen.xwbt] - Blame information for rev 2
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
john_fpga |
INTSTYLE=ise
|
| 2 |
|
|
INFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\Top_Modul_VHDL.ncd
|
| 3 |
|
|
OUTFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\Top_Modul_VHDL.bit
|
| 4 |
|
|
FAMILY=Spartan3A and Spartan3AN
|
| 5 |
|
|
PART=xc3s700a-4fg484
|
| 6 |
|
|
WORKINGDIR=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2
|
| 7 |
|
|
LICENSE=WebPack
|
| 8 |
|
|
USER_INFO=205456775_0_0_536
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
