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john_fpga |
--*****************************************************************************
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-- DISCLAIMER OF LIABILITY
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--
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-- This file contains proprietary and confidential information of
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-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
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-- from Xilinx, and may be used, copied and/or disclosed only
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-- pursuant to the terms of a valid license agreement with Xilinx.
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--
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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-- does not warrant that functions included in the Materials will
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-- Materials will be uninterrupted or error-free, or that defects
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-- in the Materials will be corrected. Furthermore, Xilinx does
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-- results of the use, of the Materials in terms of correctness,
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-- accuracy, reliability or otherwise.
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--
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-- Xilinx products are not designed or intended to be fail-safe,
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-- or for use in any application requiring fail-safe performance,
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-- such as life-support or safety devices or systems, Class III
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-- medical devices, nuclear facilities, applications related to
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-- the deployment of airbags, or any other applications that could
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-- lead to death, personal injury or severe property or
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-- environmental damage (individually and collectively, "critical
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-- applications"). Customer assumes the sole risk and liability
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-- of any use of Xilinx products in critical applications,
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-- subject only to applicable laws and regulations governing
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-- limitations on product liability.
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--
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-- Copyright 2005, 2006, 2007 Xilinx, Inc.
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-- All rights reserved.
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--
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-- This disclaimer and copyright notice must be retained as part
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-- of this file at all times.
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 3.6.1
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-- \ \ Application : MIG
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-- / / Filename : DDR2_Ram_Core_infrastructure.vhd
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-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
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-- \ \ / \ Date Created : Mon May 2 2005
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-- \___\/\___\
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-- Device : Spartan-3/3A/3A-DSP
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-- Design Name : DDR2 SDRAM
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-- Purpose :
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--*****************************************************************************
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library ieee;
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library UNISIM;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use UNISIM.VCOMPONENTS.all;
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entity DDR2_Ram_Core_infrastructure is
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port(
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delay_sel_val1_val : out std_logic_vector(4 downto 0);
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delay_sel_val : in std_logic_vector(4 downto 0);
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rst_calib1 : in std_logic;
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clk_int : in std_logic;
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-- debug signals
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dbg_delay_sel : out std_logic_vector(4 downto 0);
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dbg_rst_calib : out std_logic
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);
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end DDR2_Ram_Core_infrastructure;
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architecture arc of DDR2_Ram_Core_infrastructure is
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signal delay_sel_val1 : std_logic_vector(4 downto 0);
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signal rst_calib1_r1 : std_logic;
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signal rst_calib1_r2 : std_logic;
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begin
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delay_sel_val1_val <= delay_sel_val1;
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dbg_delay_sel <= delay_sel_val1;
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dbg_rst_calib <= rst_calib1_r2;
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process(clk_int)
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begin
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if clk_int 'event and clk_int = '0' then
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rst_calib1_r1 <= rst_calib1;
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end if;
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end process;
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process(clk_int)
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begin
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if clk_int 'event and clk_int = '1' then
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rst_calib1_r2 <= rst_calib1_r1;
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end if;
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end process;
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process(clk_int)
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begin
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if clk_int 'event and clk_int = '1' then
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if (rst_calib1_r2 = '0') then
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delay_sel_val1 <= delay_sel_val;
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else
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delay_sel_val1 <= delay_sel_val1;
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end if;
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end if;
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end process;
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end arc;
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