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john_fpga |
--*****************************************************************************
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-- DISCLAIMER OF LIABILITY
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--
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-- This file contains proprietary and confidential information of
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-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
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-- from Xilinx, and may be used, copied and/or disclosed only
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-- pursuant to the terms of a valid license agreement with Xilinx.
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--
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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-- does not warrant that functions included in the Materials will
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-- meet the requirements of Licensee, or that the operation of the
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-- Materials will be uninterrupted or error-free, or that defects
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-- in the Materials will be corrected. Furthermore, Xilinx does
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-- results of the use, of the Materials in terms of correctness,
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-- accuracy, reliability or otherwise.
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--
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-- Xilinx products are not designed or intended to be fail-safe,
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-- or for use in any application requiring fail-safe performance,
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-- such as life-support or safety devices or systems, Class III
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-- lead to death, personal injury or severe property or
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-- environmental damage (individually and collectively, "critical
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-- applications"). Customer assumes the sole risk and liability
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-- of any use of Xilinx products in critical applications,
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-- subject only to applicable laws and regulations governing
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-- limitations on product liability.
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--
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-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
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-- All rights reserved.
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--
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-- This disclaimer and copyright notice must be retained as part
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-- of this file at all times.
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 3.6.1
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-- \ \ Application : MIG
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-- / / Filename : DDR2_Ram_Core_s3_dqs_iob.vhd
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-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
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-- \ \ / \ Date Created : Mon May 2 2005
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-- \___\/\___\
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-- Device : Spartan-3/3A/3A-DSP
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-- Design Name : DDR2 SDRAM
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-- Purpose : This module instantiates DDR IOB output flip-flops, an
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-- output buffer with registered tri-state, and an input buffer
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-- for a single strobe/dqs bit. The DDR IOB output flip-flops
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-- are used to forward strobe to memory during a write. During
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-- a read, the output of the IBUF is routed to the internal
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-- delay module, dqs_delay.
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library UNISIM;
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use UNISIM.VCOMPONENTS.all;
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entity DDR2_Ram_Core_s3_dqs_iob is
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port(
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clk : in std_logic;
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ddr_dqs_reset : in std_logic;
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ddr_dqs_enable : in std_logic;
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ddr_dqs : inout std_logic;
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ddr_dqs_n : inout std_logic;
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dqs : out std_logic);
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end DDR2_Ram_Core_s3_dqs_iob;
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architecture arc of DDR2_Ram_Core_s3_dqs_iob is
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signal dqs_q : std_logic;
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signal ddr_dqs_enable1 : std_logic;
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signal vcc : std_logic;
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signal gnd : std_logic;
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signal ddr_dqs_enable_b : std_logic;
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signal data1 : std_logic;
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signal clk180 : std_logic;
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attribute IOB : string;
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attribute syn_useioff : boolean;
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attribute IOB of U1 : label is "FORCE";
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attribute syn_useioff of U1 : label is true;
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begin
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--******************************************************************************
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-- Output DDR generation. This includes instantiation of the output DDR flip flop.
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-- Additionally, to keep synthesis tools from register sharing, manually
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-- instantiate the output tri-state flip-flop.
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--******************************************************************************
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vcc <= '1';
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gnd <= '0';
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clk180 <= not clk;
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ddr_dqs_enable_b <= not ddr_dqs_enable;
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data1 <= '0' when ddr_dqs_reset = '1' else
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'1';
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U1 : FD
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port map (
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D => ddr_dqs_enable_b,
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Q => ddr_dqs_enable1,
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C => clk
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);
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U2 : FDDRRSE
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port map (
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Q => dqs_q,
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C0 => clk,
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C1 => clk180,
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CE => vcc,
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D0 => data1,
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D1 => gnd,
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R => gnd,
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S => gnd
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);
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--***********************************************************************
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-- IO buffer for dqs signal. Allows for distribution of dqs
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-- to the data (DQ) loads.
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--***********************************************************************
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U3 : OBUFTDS port map (
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I => dqs_q,
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T => ddr_dqs_enable1,
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O => ddr_dqs,
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OB => ddr_dqs_n
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);
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U4 : IBUFDS port map(
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I => ddr_dqs,
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IB => ddr_dqs_n,
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O => dqs
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);
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end arc;
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