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john_fpga |
--*****************************************************************************
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-- DISCLAIMER OF LIABILITY
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--
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-- This file contains proprietary and confidential information of
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-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
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-- from Xilinx, and may be used, copied and/or disclosed only
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-- pursuant to the terms of a valid license agreement with Xilinx.
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--
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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-- does not warrant that functions included in the Materials will
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-- meet the requirements of Licensee, or that the operation of the
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-- Materials will be uninterrupted or error-free, or that defects
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-- in the Materials will be corrected. Furthermore, Xilinx does
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-- not warrant or make any representations regarding use, or the
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-- results of the use, of the Materials in terms of correctness,
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-- accuracy, reliability or otherwise.
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--
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-- Xilinx products are not designed or intended to be fail-safe,
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-- or for use in any application requiring fail-safe performance,
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-- such as life-support or safety devices or systems, Class III
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-- medical devices, nuclear facilities, applications related to
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-- the deployment of airbags, or any other applications that could
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-- lead to death, personal injury or severe property or
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-- environmental damage (individually and collectively, "critical
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-- applications"). Customer assumes the sole risk and liability
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-- of any use of Xilinx products in critical applications,
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-- subject only to applicable laws and regulations governing
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-- limitations on product liability.
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--
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-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
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-- All rights reserved.
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--
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-- This disclaimer and copyright notice must be retained as part
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-- of this file at all times.
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 3.6.1
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-- \ \ Application : MIG
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-- / / Filename : DDR2_Ram_Core_top_0.vhd
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-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
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-- \ \ / \ Date Created : Mon May 2 2005
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-- \___\/\___\
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-- Device : Spartan-3/3A/3A-DSP
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-- Design Name : DDR2 SDRAM
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-- Purpose : This modules has the instantiations infrastructure, iobs,
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-- controller and data_paths modules
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--*****************************************************************************
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library ieee;
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library UNISIM;
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use ieee.std_logic_1164.all;
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use work.DDR2_Ram_Core_parameters_0.all;
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use UNISIM.VCOMPONENTS.all;
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entity DDR2_Ram_Core_top_0 is
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port(
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wait_200us : in std_logic;
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rst_dqs_div_in : in std_logic;
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rst_dqs_div_out : out std_logic;
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user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
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user_data_mask : in std_logic_vector(((DATA_MASK_WIDTH*2)-1) downto 0);
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user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1)
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downto 0) := (others => 'Z');
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user_data_valid : out std_logic;
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user_input_address : in std_logic_vector(((ROW_ADDRESS +
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COLUMN_ADDRESS + BANK_ADDRESS)-1) downto 0);
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user_command_register : in std_logic_vector(2 downto 0);
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burst_done : in std_logic;
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auto_ref_req : out std_logic;
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user_cmd_ack : out std_logic;
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init_done : out std_logic;
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ar_done : out std_logic;
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ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
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ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
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ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0)
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:= (others => 'Z');
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ddr2_cke : out std_logic;
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ddr2_cs_n : out std_logic;
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ddr2_ras_n : out std_logic;
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ddr2_cas_n : out std_logic;
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ddr2_we_n : out std_logic;
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ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
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ddr2_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
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ddr2_a : out std_logic_vector((ROW_ADDRESS-1) downto 0);
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ddr2_odt : out std_logic;
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ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
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ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
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clk_tb : out std_logic;
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clk90_tb : out std_logic;
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sys_rst_tb : out std_logic;
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sys_rst90_tb : out std_logic;
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sys_rst180_tb : out std_logic;
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clk_int : in std_logic;
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clk90_int : in std_logic;
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delay_sel_val : in std_logic_vector(4 downto 0);
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sys_rst : in std_logic;
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sys_rst90 : in std_logic;
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sys_rst180 : in std_logic;
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-- debug signals
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dbg_delay_sel : out std_logic_vector(4 downto 0);
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dbg_rst_calib : out std_logic;
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vio_out_dqs : in std_logic_vector(4 downto 0);
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vio_out_dqs_en : in std_logic;
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vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
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vio_out_rst_dqs_div_en : in std_logic
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);
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end DDR2_Ram_Core_top_0;
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architecture arc of DDR2_Ram_Core_top_0 is
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component DDR2_Ram_Core_controller_0
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port(
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auto_ref_req : out std_logic;
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wait_200us : in std_logic;
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clk : in std_logic;
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rst0 : in std_logic;
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rst180 : in std_logic;
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address : in std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS)-1)
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downto 0);
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bank_addr : in std_logic_vector((BANK_ADDRESS-1) downto 0);
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command_register : in std_logic_vector(2 downto 0);
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burst_done : in std_logic;
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ddr_rasb_cntrl : out std_logic;
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ddr_casb_cntrl : out std_logic;
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ddr_web_cntrl : out std_logic;
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ddr_ba_cntrl : out std_logic_vector((BANK_ADDRESS-1) downto 0);
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ddr_address_cntrl : out std_logic_vector((ROW_ADDRESS-1) downto 0);
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ddr_cke_cntrl : out std_logic;
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ddr_csb_cntrl : out std_logic;
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ddr_ODT_cntrl : out std_logic;
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dqs_enable : out std_logic;
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dqs_reset : out std_logic;
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write_enable : out std_logic;
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rst_calib : out std_logic;
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rst_dqs_div_int : out std_logic;
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cmd_ack : out std_logic;
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init : out std_logic;
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ar_done : out std_logic;
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read_fifo_rden : out std_logic -- Added new signal
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);
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end component;
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component DDR2_Ram_Core_data_path_0
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port(
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user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
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user_data_mask : in std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
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clk : in std_logic;
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clk90 : in std_logic;
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reset : in std_logic;
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reset90 : in std_logic;
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write_enable : in std_logic;
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rst_dqs_div_in : in std_logic;
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delay_sel : in std_logic_vector(4 downto 0);
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dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
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dq : in std_logic_vector((DATA_WIDTH-1) downto 0);
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u_data_val : out std_logic;
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user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
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write_en_val : out std_logic;
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data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
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data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
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write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
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write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0);
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read_fifo_rden : in std_logic; -- Added new signal
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-- debug singals
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vio_out_dqs : in std_logic_vector(4 downto 0);
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vio_out_dqs_en : in std_logic;
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vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
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vio_out_rst_dqs_div_en : in std_logic
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);
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end component;
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component DDR2_Ram_Core_infrastructure
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port(
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clk_int : in std_logic;
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rst_calib1 : in std_logic;
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delay_sel_val : in std_logic_vector(4 downto 0);
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delay_sel_val1_val : out std_logic_vector(4 downto 0);
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-- debug signals
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dbg_delay_sel : out std_logic_vector(4 downto 0);
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dbg_rst_calib : out std_logic
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);
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end component;
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component DDR2_Ram_Core_iobs_0
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port(
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clk : in std_logic;
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clk90 : in std_logic;
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ddr_rasb_cntrl : in std_logic;
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ddr_casb_cntrl : in std_logic;
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ddr_web_cntrl : in std_logic;
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ddr_cke_cntrl : in std_logic;
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ddr_csb_cntrl : in std_logic;
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ddr_ODT_cntrl : in std_logic;
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ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS-1) downto 0);
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ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS-1) downto 0);
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rst_dqs_div_int : in std_logic;
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dqs_reset : in std_logic;
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dqs_enable : in std_logic;
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ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
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ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
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ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
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write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
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write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
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write_en_val : in std_logic;
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data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
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data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
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ddr_odt : out std_logic;
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ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
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ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
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ddr_rasb : out std_logic;
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ddr_casb : out std_logic;
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ddr_web : out std_logic;
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ddr_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
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ddr_address : out std_logic_vector((ROW_ADDRESS-1) downto 0);
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ddr_cke : out std_logic;
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ddr_csb : out std_logic;
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rst_dqs_div : out std_logic;
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rst_dqs_div_in : in std_logic;
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rst_dqs_div_out : out std_logic;
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dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
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ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
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dq : out std_logic_vector((DATA_WIDTH-1) downto 0)
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);
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end component;
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signal rst_calib : std_logic;
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signal delay_sel : std_logic_vector(4 downto 0);
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signal write_enable : std_logic;
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signal dqs_div_rst : std_logic;
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signal dqs_enable : std_logic;
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signal dqs_reset : std_logic;
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signal dqs_int_delay_in : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
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signal dq : std_logic_vector((DATA_WIDTH-1) downto 0);
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signal write_en_val : std_logic;
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signal data_mask_f : std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
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signal data_mask_r : std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
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signal write_data_falling : std_logic_vector((DATA_WIDTH-1) downto 0);
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signal write_data_rising : std_logic_vector((DATA_WIDTH-1) downto 0);
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signal ddr_rasb_cntrl : std_logic;
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signal ddr_casb_cntrl : std_logic;
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signal ddr_web_cntrl : std_logic;
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signal ddr_ba_cntrl : std_logic_vector((BANK_ADDRESS-1) downto 0);
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signal ddr_address_cntrl : std_logic_vector((ROW_ADDRESS-1) downto 0);
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signal ddr_cke_cntrl : std_logic;
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signal ddr_csb_cntrl : std_logic;
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signal ddr_odt_cntrl : std_logic;
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signal rst_dqs_div_int : std_logic;
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signal read_fifo_rden : std_logic;
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begin
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clk_tb <= clk_int after 1 ps;
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clk90_tb <= clk90_int after 1 ps;
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sys_rst_tb <= sys_rst;
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sys_rst90_tb <= sys_rst90;
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sys_rst180_tb <= sys_rst180;
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controller0 : DDR2_Ram_Core_controller_0
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port map (
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auto_ref_req => auto_ref_req,
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wait_200us => wait_200us,
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clk => clk_int,
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rst0 => sys_rst,
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rst180 => sys_rst180,
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address => user_input_address(((ROW_ADDRESS + COLUMN_ADDRESS +
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BANK_ADDRESS)-1) downto BANK_ADDRESS),
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bank_addr => user_input_address(BANK_ADDRESS-1 downto 0),
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command_register => user_command_register,
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burst_done => burst_done,
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ddr_rasb_cntrl => ddr_rasb_cntrl,
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ddr_casb_cntrl => ddr_casb_cntrl,
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ddr_web_cntrl => ddr_web_cntrl,
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ddr_ba_cntrl => ddr_ba_cntrl,
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ddr_address_cntrl => ddr_address_cntrl,
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ddr_cke_cntrl => ddr_cke_cntrl,
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ddr_csb_cntrl => ddr_csb_cntrl,
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ddr_odt_cntrl => ddr_odt_cntrl,
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dqs_enable => dqs_enable,
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dqs_reset => dqs_reset,
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write_enable => write_enable,
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rst_calib => rst_calib,
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rst_dqs_div_int => rst_dqs_div_int,
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cmd_ack => user_cmd_ack,
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init => init_done,
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ar_done => ar_done,
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|
|
read_fifo_rden => read_fifo_rden -- Added new signal
|
298 |
|
|
);
|
299 |
|
|
|
300 |
|
|
data_path0 : DDR2_Ram_Core_data_path_0
|
301 |
|
|
port map (
|
302 |
|
|
user_input_data => user_input_data,
|
303 |
|
|
user_data_mask => user_data_mask,
|
304 |
|
|
clk => clk_int,
|
305 |
|
|
clk90 => clk90_int,
|
306 |
|
|
reset => sys_rst,
|
307 |
|
|
reset90 => sys_rst90,
|
308 |
|
|
write_enable => write_enable,
|
309 |
|
|
rst_dqs_div_in => dqs_div_rst,
|
310 |
|
|
delay_sel => delay_sel,
|
311 |
|
|
dqs_int_delay_in => dqs_int_delay_in,
|
312 |
|
|
dq => dq,
|
313 |
|
|
u_data_val => user_data_valid,
|
314 |
|
|
user_output_data => user_output_data,
|
315 |
|
|
write_en_val => write_en_val,
|
316 |
|
|
data_mask_f => data_mask_f,
|
317 |
|
|
data_mask_r => data_mask_r,
|
318 |
|
|
write_data_falling => write_data_falling,
|
319 |
|
|
write_data_rising => write_data_rising,
|
320 |
|
|
read_fifo_rden => read_fifo_rden, -- Added new signal
|
321 |
|
|
--debug signals
|
322 |
|
|
vio_out_dqs => vio_out_dqs,
|
323 |
|
|
vio_out_dqs_en => vio_out_dqs_en,
|
324 |
|
|
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
|
325 |
|
|
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
|
326 |
|
|
);
|
327 |
|
|
|
328 |
|
|
infrastructure0 : DDR2_Ram_Core_infrastructure
|
329 |
|
|
port map (
|
330 |
|
|
clk_int => clk_int,
|
331 |
|
|
rst_calib1 => rst_calib,
|
332 |
|
|
delay_sel_val => delay_sel_val,
|
333 |
|
|
delay_sel_val1_val => delay_sel,
|
334 |
|
|
dbg_delay_sel => dbg_delay_sel,
|
335 |
|
|
dbg_rst_calib => dbg_rst_calib
|
336 |
|
|
);
|
337 |
|
|
|
338 |
|
|
iobs0 : DDR2_Ram_Core_iobs_0
|
339 |
|
|
port map (
|
340 |
|
|
clk => clk_int,
|
341 |
|
|
clk90 => clk90_int,
|
342 |
|
|
ddr_rasb_cntrl => ddr_rasb_cntrl,
|
343 |
|
|
ddr_casb_cntrl => ddr_casb_cntrl,
|
344 |
|
|
ddr_odt_cntrl => ddr_odt_cntrl,
|
345 |
|
|
ddr_web_cntrl => ddr_web_cntrl,
|
346 |
|
|
ddr_cke_cntrl => ddr_cke_cntrl,
|
347 |
|
|
ddr_csb_cntrl => ddr_csb_cntrl,
|
348 |
|
|
ddr_address_cntrl => ddr_address_cntrl,
|
349 |
|
|
ddr_ba_cntrl => ddr_ba_cntrl,
|
350 |
|
|
rst_dqs_div_int => rst_dqs_div_int,
|
351 |
|
|
dqs_reset => dqs_reset,
|
352 |
|
|
dqs_enable => dqs_enable,
|
353 |
|
|
ddr_dqs => ddr2_dqs,
|
354 |
|
|
ddr_dqs_n => ddr2_dqs_n,
|
355 |
|
|
ddr_dq => ddr2_dq,
|
356 |
|
|
write_data_falling => write_data_falling,
|
357 |
|
|
write_data_rising => write_data_rising,
|
358 |
|
|
write_en_val => write_en_val,
|
359 |
|
|
data_mask_f => data_mask_f,
|
360 |
|
|
data_mask_r => data_mask_r,
|
361 |
|
|
ddr_odt => ddr2_odt,
|
362 |
|
|
ddr2_ck => ddr2_ck,
|
363 |
|
|
ddr2_ck_n => ddr2_ck_n,
|
364 |
|
|
ddr_rasb => ddr2_ras_n,
|
365 |
|
|
ddr_casb => ddr2_cas_n,
|
366 |
|
|
ddr_web => ddr2_we_n,
|
367 |
|
|
ddr_ba => ddr2_ba,
|
368 |
|
|
ddr_address => ddr2_a,
|
369 |
|
|
ddr_cke => ddr2_cke,
|
370 |
|
|
ddr_csb => ddr2_cs_n,
|
371 |
|
|
rst_dqs_div => dqs_div_rst,
|
372 |
|
|
rst_dqs_div_in => rst_dqs_div_in,
|
373 |
|
|
rst_dqs_div_out => rst_dqs_div_out,
|
374 |
|
|
dqs_int_delay_in => dqs_int_delay_in,
|
375 |
|
|
ddr_dm => ddr2_dm,
|
376 |
|
|
dq => dq
|
377 |
|
|
);
|
378 |
|
|
|
379 |
|
|
end arc;
|