OpenCores
URL https://opencores.org/ocsvn/ddr3_synthesizable_bfm/ddr3_synthesizable_bfm/trunk

Subversion Repositories ddr3_synthesizable_bfm

[/] [ddr3_synthesizable_bfm/] [trunk/] [rtl/] [ddr3_sr36.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 slai
/*
2
Multibits Shift Register
3
2010-2011 sclai <laikos@yahoo.com>
4
 
5
This library is free software; you can redistribute it and/or modify it
6
 under the terms of the GNU Lesser General Public License as published by
7
 the Free Software Foundation; either version 2.1 of the License,
8
 or (at your option) any later version.
9
 
10
 This library is distributed in the hope that it will be useful, but
11
 WITHOUT ANY WARRANTY; without even the implied warranty of
12
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13
 Lesser General Public License for more details.
14
 
15
 You should have received a copy of the GNU Lesser General Public
16
 License along with this library; if not, write to the Free Software
17
 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
18
 USA
19
*/
20
module ddr3_sr36 #(
21
parameter PIPE_LEN=7
22
)(
23
input wire        clk,
24
input wire [35:0] shift_in,
25
output wire [35:0]shift_out
26
);
27
//register to hold value
28
reg [PIPE_LEN-1:0] d0;
29
reg [PIPE_LEN-1:0] d1;
30
reg [PIPE_LEN-1:0] d2;
31
reg [PIPE_LEN-1:0] d3;
32
reg [PIPE_LEN-1:0] d4;
33
reg [PIPE_LEN-1:0] d5;
34
reg [PIPE_LEN-1:0] d6;
35
reg [PIPE_LEN-1:0] d7;
36
reg [PIPE_LEN-1:0] d8;
37
reg [PIPE_LEN-1:0] d9;
38
reg [PIPE_LEN-1:0] d10;
39
reg [PIPE_LEN-1:0] d11;
40
reg [PIPE_LEN-1:0] d12;
41
reg [PIPE_LEN-1:0] d13;
42
reg [PIPE_LEN-1:0] d14;
43
reg [PIPE_LEN-1:0] d15;
44
reg [PIPE_LEN-1:0] d16;
45
reg [PIPE_LEN-1:0] d17;
46
reg [PIPE_LEN-1:0] d18;
47
reg [PIPE_LEN-1:0] d19;
48
reg [PIPE_LEN-1:0] d20;
49
reg [PIPE_LEN-1:0] d21;
50
reg [PIPE_LEN-1:0] d22;
51
reg [PIPE_LEN-1:0] d23;
52
reg [PIPE_LEN-1:0] d24;
53
reg [PIPE_LEN-1:0] d25;
54
reg [PIPE_LEN-1:0] d26;
55
reg [PIPE_LEN-1:0] d27;
56
reg [PIPE_LEN-1:0] d28;
57
reg [PIPE_LEN-1:0] d29;
58
reg [PIPE_LEN-1:0] d30;
59
reg [PIPE_LEN-1:0] d31;
60
reg [PIPE_LEN-1:0] d32;
61
reg [PIPE_LEN-1:0] d33;
62
reg [PIPE_LEN-1:0] d34;
63
reg [PIPE_LEN-1:0] d35;
64
always @(posedge clk)
65
begin
66
  d35 <={shift_in[35],d35[PIPE_LEN-1:1]};
67
  d34 <={shift_in[34],d34[PIPE_LEN-1:1]};
68
  d33 <={shift_in[33],d33[PIPE_LEN-1:1]};
69
  d32 <={shift_in[32],d32[PIPE_LEN-1:1]};
70
  d31 <={shift_in[31],d31[PIPE_LEN-1:1]};
71
  d30 <={shift_in[30],d30[PIPE_LEN-1:1]};
72
  d29 <={shift_in[29],d29[PIPE_LEN-1:1]};
73
  d28 <={shift_in[28],d28[PIPE_LEN-1:1]};
74
  d27 <={shift_in[27],d27[PIPE_LEN-1:1]};
75
  d26 <={shift_in[26],d26[PIPE_LEN-1:1]};
76
  d25 <={shift_in[25],d25[PIPE_LEN-1:1]};
77
  d24 <={shift_in[24],d24[PIPE_LEN-1:1]};
78
  d23 <={shift_in[23],d23[PIPE_LEN-1:1]};
79
  d22 <={shift_in[22],d22[PIPE_LEN-1:1]};
80
  d21 <={shift_in[21],d21[PIPE_LEN-1:1]};
81
  d20 <={shift_in[20],d20[PIPE_LEN-1:1]};
82
  d19 <={shift_in[19],d19[PIPE_LEN-1:1]};
83
  d18 <={shift_in[18],d18[PIPE_LEN-1:1]};
84
  d17 <={shift_in[17],d17[PIPE_LEN-1:1]};
85
  d16 <={shift_in[16],d16[PIPE_LEN-1:1]};
86
  d15 <={shift_in[15],d15[PIPE_LEN-1:1]};
87
  d14 <={shift_in[14],d14[PIPE_LEN-1:1]};
88
  d13 <={shift_in[13],d13[PIPE_LEN-1:1]};
89
  d12 <={shift_in[12],d12[PIPE_LEN-1:1]};
90
  d11 <={shift_in[11],d11[PIPE_LEN-1:1]};
91
  d10 <={shift_in[10],d10[PIPE_LEN-1:1]};
92
  d9  <={shift_in[ 9], d9[PIPE_LEN-1:1]};
93
  d8  <={shift_in[ 8], d8[PIPE_LEN-1:1]};
94
  d7  <={shift_in[ 7], d7[PIPE_LEN-1:1]};
95
  d6  <={shift_in[ 6], d6[PIPE_LEN-1:1]};
96
  d5  <={shift_in[ 5], d5[PIPE_LEN-1:1]};
97
  d4  <={shift_in[ 4], d4[PIPE_LEN-1:1]};
98
  d3  <={shift_in[ 3], d3[PIPE_LEN-1:1]};
99
  d2  <={shift_in[ 2], d2[PIPE_LEN-1:1]};
100
  d1  <={shift_in[ 1], d1[PIPE_LEN-1:1]};
101
  d0  <={shift_in[ 0], d0[PIPE_LEN-1:1]};
102
end
103
 
104
assign shift_out={d35[0],d34[0],d33[0],d32[0],
105
d31[0],d30[0],d29[0],d28[0],d27[0],d26[0],d25[0],d24[0],
106
d23[0],d22[0],d21[0],d20[0],d19[0],d18[0],d17[0],d16[0],
107
d15[0],d14[0],d13[0],d12[0],d11[0],d10[0],d9[0],d8[0],
108
d7[0],d6[0],d5[0],d4[0],d3[0],d2[0],d1[0],d0[0]
109
};
110
endmodule
111
 
112
 
113
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.