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\begin{document}
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%\maketitle
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\begin{center}
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\Large Direct Digital Synthesizer IP Core\\[0.4cm]
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\large Martin Kumm \\[0.5cm]
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\large \today \\[0.5cm]
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%\Large 19.12.2007 \\[1.0cm]
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\end{center}
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%\tableofcontents
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%\newpage
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The DDS IP core (\verb|dds_synthesizer|) is a implementation of a direct digital frequency synthesizer (DDS) (also called number controlled oscillator, NCO) which produces a sinewave at the output with a specified frequency and phase (adjustable at runtime). The resolution of the frequency tuning word (FTW), the phase and the amplitude are defined seperately. While the FTW resolution can be set by the generic \verb|ftw_width|, phase and amplitude resolution are defined as constants \verb|phase_width| and \verb|ampl_width| in the seperate package \verb|sine_lut_pkg|. This is generated by a matlab script (\verb|matlab/sine_lut_gen.m|), the m-files are described in their headers. The most relevant LUTs (in the range 8...16Bit) have been generated and are located in the ``\verb|VHDL/sine_lut|'' folder. The nomenclature of the files is \verb|sine_<phase_width>_x_<amplitude_width>_pkg.vhd|. By adding one of these files to the project, the resolution of phase and amplitude is automatically defined.
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Figure 1 shows a block diagram of the implemented DDS synthesizer. The signals \verb|clk| and \verb|reset| are not shown here. The resolution parameters have been renamed (\verb|ftw_width|=N, \verb|phase_width|=M and \verb|amplitude_width|=P). Only the first period of the sinewave is stored in the LUT, the two most significant bits of the phase word are used either to shift the input value or to invert the output amplitude, depending on the quadrant of the sinewave. The LUT is clocked, so the total delay from input to output is 3 clock cycles.
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\begin{figure}[H]
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\centering
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\includegraphics[width=14cm]{images/dds_implementation}
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\caption{Block diagram of the DDS implementation}
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\label{fig:dds_implementation}
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\end{figure}
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The output frequency will be determined by the FTW (\verb|ftw_i|)
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\begin{equation}
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f_{DDS}=\frac{FTW}{2^M} f_s \ \ .
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\label{equ:ftw}
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\end{equation}
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The initial phase (when using more than one synthesizer) can be set by setting the PTW (\verb|phase_i|) to
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\begin{equation}
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\varphi_{DDS}=\frac{PTW}{2^N} 2 \pi \ \ .
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\label{equ:ptw}
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\end{equation}
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A Testbench is realized in \verb|dds_synthesizer_tb.vhd|, the corresponding Modelsim project can be found in the \verb|/sim| folder. The ports of the entity are described in Table~\ref{tab:ports}.
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\begin{table}[H]
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\centering
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\begin{tabular}{l|c|c|l}
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\hline
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\hline
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Name & Direction & Wordsize & Description \\
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\hline
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\verb|clk_i| & \verb|in| & 1 & clock \\
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\verb|rst_i| & \verb|in| & 1 & reset \\
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\verb|ftw_i| & \verb|in| & \verb|ftw_width| & Frequency Tuning Word, see Formula (\ref{equ:ftw}) \\
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\verb|phase_i| & \verb|in| & \verb|phase_width| & Phase Tuning Word, see Formula (\ref{equ:ptw}) \\
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\verb|phase_o| & \verb|out| & \verb|phase_width| & Instantaneous Phase Output \\
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\verb|ampl_o| & \verb|out| & \verb|ampl_width | & Amplitude Output \\
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\hline
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\hline
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\end{tabular}
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\caption{Entity port description}
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\label{tab:ports}
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\end{table}
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%\bibliographystyle{alpha}
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%\bibliography{dsp_4_sdr}
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\end{document}
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