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jdoin |
-- TestBench Template
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity testbench is
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end testbench;
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architecture behavior of testbench is
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--=============================================================================================
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-- Constants
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--=============================================================================================
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-- clock period
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constant CLK_PERIOD : time := 10 ns;
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--=============================================================================================
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-- COMPONENT DECLARATIONS
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--=============================================================================================
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COMPONENT debounce_atlys_top
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PORT(
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gclk_i : IN std_logic;
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sw_i : IN std_logic_vector(7 downto 0);
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led_o : OUT std_logic_vector(7 downto 0);
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strb_o : OUT std_logic;
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dbg_o : OUT std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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--=============================================================================================
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-- Signals for internal operation
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--=============================================================================================
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--- clock signals ---
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signal sysclk : std_logic := '0'; -- 100MHz clock
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--- switch debouncer signals ---
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signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- switch data
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-- debug output signals
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signal leds : std_logic_vector (7 downto 0); -- board leds
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signal dbg : std_logic_vector (15 downto 0); -- LA debug vector
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signal strobe : std_logic;
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signal sw_input : std_logic_vector (7 downto 0); -- raw switches
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signal sw_output : std_logic_vector (7 downto 0); -- debounced switches
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begin
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--=============================================================================================
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-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
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--=============================================================================================
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-- debounce_atlys_top:
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-- receives the 100 MHz clock from the board clock oscillator
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-- receives the 8 slide switches and 5 pushbuttons as test stimuli
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-- connects to 8 board LEDs
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-- connects to 16 debug pins
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Inst_debounce_atlys_top: debounce_atlys_top
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PORT MAP(
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gclk_i => sysclk, -- connect board clock
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sw_i => sw_data, -- connect board switches
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led_o => leds, -- connect board leds
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strb_o => strobe, -- connect strobe debug
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dbg_o => dbg -- connect logic analyzer
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);
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-- debug signals mapped on dbg vector
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sw_input <= dbg(7 downto 0);
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sw_output <= dbg(15 downto 8);
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--=============================================================================================
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-- CLOCK GENERATION
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--=============================================================================================
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gclk_proc: process is
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begin
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loop
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sysclk <= not sysclk;
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wait for CLK_PERIOD / 2;
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end loop;
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end process gclk_proc;
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--=============================================================================================
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-- TEST BENCH STIMULI
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--=============================================================================================
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tb : process
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begin
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wait for 100 ns; -- wait until global set/reset completes
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sw_data <= X"00";
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wait for 1 us;
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-- change switches to 0x93, with bouncing
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sw_data <= X"81";
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wait for 50 ns;
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sw_data <= X"80";
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wait for 250 ns;
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sw_data <= X"91";
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wait for 40 ns;
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sw_data <= X"81";
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wait for 90 ns;
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sw_data <= X"93";
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wait for 40 us;
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-- change switches to 0x3E, with bouncing
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sw_data <= X"97";
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wait for 50 ns;
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sw_data <= X"16";
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wait for 150 ns;
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sw_data <= X"3E";
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wait for 300 ns;
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sw_data <= X"2C";
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wait for 50 ns;
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sw_data <= X"3D";
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wait for 400 ns;
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sw_data <= X"3E";
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wait for 50 us;
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-- end simulation
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assert false report "End Simulation" severity failure; -- stop simulation
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end process tb;
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-- End Test Bench
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END;
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