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[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys_top.syr] - Blame information for rev 7

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Release 13.1 - xst O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Reading design: debounce_atlys_top.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "debounce_atlys_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "debounce_atlys_top"
Output Format                      : NGC
Target Device                      : xc6slx45-2-csg324
 
---- Source Options
Top Module Name                    : debounce_atlys_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Gray
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : No
ROM Extraction                     : No
Shift Register Extraction          : NO
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No
 
---- Target Options
LUT Combining                      : Area
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\grp_debouncer.vhd" into library work
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" into library work
Parsing entity .
Parsing architecture  of entity .
 
=========================================================================
*                            HDL Elaboration                            *
=========================================================================
 
Elaborating entity  (architecture ) from library .
 
Elaborating entity  (architecture ) with generics from library .
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" Line 71: Net  does not have a driver.
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Synthesizing Unit .
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/debounce_atlys_top.vhd".
WARNING:Xst:2935 - Signal 'dbg<15>', unconnected in block 'debounce_atlys_top', is tied to its initial value (0).
    Found 7-bit register for signal .
    Summary:
        inferred   7 D-type flip-flop(s).
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/grp_debouncer.vhd".
        N = 7
        CNT_VAL = 5000
    Found 7-bit register for signal .
    Found 7-bit register for signal .
    Found 1-bit register for signal .
    Found 7-bit register for signal .
    Found 13-bit register for signal .
    Found 14-bit adder for signal  created at line 167.
    Found 7-bit comparator not equal for signal  created at line 192
    Found 7-bit comparator not equal for signal  created at line 194
    Summary:
        inferred   1 Adder/Subtractor(s).
        inferred  35 D-type flip-flop(s).
        inferred   2 Comparator(s).
Unit  synthesized.
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Adders/Subtractors                                   : 1
 14-bit adder                                          : 1
# Registers                                            : 6
 1-bit register                                        : 1
 13-bit register                                       : 1
 7-bit register                                        : 4
# Comparators                                          : 2
 7-bit comparator not equal                            : 2
 
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
 
Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# Counters                                             : 1
 13-bit up counter                                     : 1
# Registers                                            : 29
 Flip-Flops                                            : 29
# Comparators                                          : 2
 7-bit comparator not equal                            : 2
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block debounce_atlys_top, actual ratio is 0.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers                                            : 42
 Flip-Flops                                            : 42
 
=========================================================================
 
=========================================================================
*                           Partition Report                            *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Design Summary                             *
=========================================================================
 
Top Level Output File Name         : debounce_atlys_top.ngc
 
Primitive and Black Box Usage:
------------------------------
# BELS                             : 73
#      GND                         : 1
#      INV                         : 1
#      LUT1                        : 12
#      LUT3                        : 1
#      LUT4                        : 9
#      LUT6                        : 23
#      MUXCY                       : 12
#      VCC                         : 1
#      XORCY                       : 13
# FlipFlops/Latches                : 42
#      FD                          : 28
#      FDE                         : 14
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 30
#      IBUF                        : 7
#      OBUF                        : 23
 
Device utilization summary:
---------------------------
 
Selected Device : 6slx45csg324-2
 
 
Slice Logic Utilization:
 Number of Slice Registers:              42  out of  54576     0%
 Number of Slice LUTs:                   46  out of  27288     0%
    Number used as Logic:                46  out of  27288     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     67
   Number with an unused Flip Flop:      25  out of     67    37%
   Number with an unused LUT:            21  out of     67    31%
   Number of fully used LUT-FF pairs:    21  out of     67    31%
   Number of unique control sets:         3
 
IO Utilization:
 Number of IOs:                          31
 Number of bonded IOBs:                  31  out of    218    14%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
Timing Report
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
gclk_i                             | BUFGP                  | 42    |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
 
Timing Summary:
---------------
Speed Grade: -2
 
   Minimum period: 4.717ns (Maximum Frequency: 211.999MHz)
   Minimum input arrival time before clock: 2.127ns
   Maximum output required time after clock: 4.380ns
   Maximum combinational path delay: 4.965ns
 
Timing Details:
---------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'gclk_i'
  Clock period: 4.717ns (frequency: 211.999MHz)
  Total number of paths / destination ports: 713 / 49
-------------------------------------------------------------------------
Delay:               4.717ns (Levels of Logic = 3)
  Source:            Inst_sw_debouncer/cnt_reg_0 (FF)
  Destination:       Inst_sw_debouncer/strb_reg (FF)
  Source Clock:      gclk_i rising
  Destination Clock: gclk_i rising
 
  Data Path: Inst_sw_debouncer/cnt_reg_0 to Inst_sw_debouncer/strb_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.525   1.181  Inst_sw_debouncer/cnt_reg_0 (Inst_sw_debouncer/cnt_reg_0)
     LUT6:I0->O            8   0.254   1.052  Inst_sw_debouncer/dat_strb<12>1 (Inst_sw_debouncer/dat_strb<12>)
     LUT3:I1->O           14   0.250   1.127  Inst_sw_debouncer/dat_strb<12>3 (Inst_sw_debouncer/dat_strb)
     LUT6:I5->O            1   0.254   0.000  Inst_sw_debouncer/strb_next6 (Inst_sw_debouncer/strb_next)
     FD:D                      0.074          Inst_sw_debouncer/strb_reg
    ----------------------------------------
    Total                      4.717ns (1.357ns logic, 3.360ns route)
                                       (28.8% logic, 71.2% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
  Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Offset:              2.127ns (Levels of Logic = 1)
  Source:            sw_i<6> (PAD)
  Destination:       Inst_sw_debouncer/reg_A_6 (FF)
  Destination Clock: gclk_i rising
 
  Data Path: sw_i<6> to Inst_sw_debouncer/reg_A_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.328   0.725  sw_i_6_IBUF (dbg_o_6_OBUF)
     FD:D                      0.074          Inst_sw_debouncer/reg_A_6
    ----------------------------------------
    Total                      2.127ns (1.402ns logic, 0.725ns route)
                                       (65.9% logic, 34.1% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
  Total number of paths / destination ports: 15 / 15
-------------------------------------------------------------------------
Offset:              4.380ns (Levels of Logic = 1)
  Source:            Inst_sw_debouncer/strb_reg (FF)
  Destination:       dbg_o<14> (PAD)
  Source Clock:      gclk_i rising
 
  Data Path: Inst_sw_debouncer/strb_reg to dbg_o<14>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               8   0.525   0.943  Inst_sw_debouncer/strb_reg (Inst_sw_debouncer/strb_reg)
     OBUF:I->O                 2.912          dbg_o_14_OBUF (dbg_o<14>)
    ----------------------------------------
    Total                      4.380ns (3.437ns logic, 0.943ns route)
                                       (78.5% logic, 21.5% route)
 
=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Delay:               4.965ns (Levels of Logic = 2)
  Source:            sw_i<6> (PAD)
  Destination:       dbg_o<6> (PAD)
 
  Data Path: sw_i<6> to dbg_o<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.328   0.725  sw_i_6_IBUF (dbg_o_6_OBUF)
     OBUF:I->O                 2.912          dbg_o_6_OBUF (dbg_o<6>)
    ----------------------------------------
    Total                      4.965ns (4.240ns logic, 0.725ns route)
                                       (85.4% logic, 14.6% route)
 
=========================================================================
 
Cross Clock Domains Report:
--------------------------
 
Clock to Setup on destination clock gclk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i         |    4.717|         |         |         |
---------------+---------+---------+---------+---------+
 
=========================================================================
 
 
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.57 secs
 
-->
 
Total memory usage is 185320 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)
 

Line No.	Rev	Author	Line
1	6	jdoin	`Release 13.1 - xst O.40d (nt)`
2			`Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.`
3			`--> Parameter TMPDIR set to xst/projnav.tmp`
4
5
6			`Total REAL time to Xst completion: 0.00 secs`
7			`Total CPU time to Xst completion: 0.08 secs`
8
9			`--> Parameter xsthdpdir set to xst`
10
11
12			`Total REAL time to Xst completion: 0.00 secs`
13			`Total CPU time to Xst completion: 0.08 secs`
14
15			`--> Reading design: debounce_atlys_top.prj`
16
17			`TABLE OF CONTENTS`
18			`1) Synthesis Options Summary`
19			`2) HDL Parsing`
20			`3) HDL Elaboration`
21			`4) HDL Synthesis`
22			`4.1) HDL Synthesis Report`
23			`5) Advanced HDL Synthesis`
24			`5.1) Advanced HDL Synthesis Report`
25			`6) Low Level Synthesis`
26			`7) Partition Report`
27			`8) Design Summary`
28			`8.1) Primitive and Black Box Usage`
29			`8.2) Device utilization summary`
30			`8.3) Partition Resource Summary`
31			`8.4) Timing Report`
32			`8.4.1) Clock Information`
33			`8.4.2) Asynchronous Control Signals Information`
34			`8.4.3) Timing Summary`
35			`8.4.4) Timing Details`
36			`8.4.5) Cross Clock Domains Report`
37
38
39			`=========================================================================`
40			`* Synthesis Options Summary *`
41			`=========================================================================`
42			`---- Source Parameters`
43			`Input File Name : "debounce_atlys_top.prj"`
44			`Input Format : mixed`
45			`Ignore Synthesis Constraint File : NO`
46
47			`---- Target Parameters`
48			`Output File Name : "debounce_atlys_top"`
49			`Output Format : NGC`
50			`Target Device : xc6slx45-2-csg324`
51
52			`---- Source Options`
53			`Top Module Name : debounce_atlys_top`
54			`Automatic FSM Extraction : YES`
55			`FSM Encoding Algorithm : Gray`
56			`Safe Implementation : No`
57			`FSM Style : LUT`
58			`RAM Extraction : No`
59			`ROM Extraction : No`
60			`Shift Register Extraction : NO`
61			`Resource Sharing : YES`
62			`Asynchronous To Synchronous : NO`
63			`Shift Register Minimum Size : 2`
64			`Use DSP Block : Auto`
65			`Automatic Register Balancing : No`
66
67			`---- Target Options`
68			`LUT Combining : Area`
69			`Reduce Control Sets : Auto`
70			`Add IO Buffers : YES`
71			`Global Maximum Fanout : 100000`
72			`Add Generic Clock Buffer(BUFG) : 16`
73			`Register Duplication : YES`
74			`Optimize Instantiated Primitives : NO`
75			`Use Clock Enable : Auto`
76			`Use Synchronous Set : Auto`
77			`Use Synchronous Reset : Auto`
78			`Pack IO Registers into IOBs : Auto`
79			`Equivalent register Removal : YES`
80
81			`---- General Options`
82			`Optimization Goal : Speed`
83			`Optimization Effort : 2`
84			`Power Reduction : NO`
85			`Keep Hierarchy : No`
86			`Netlist Hierarchy : As_Optimized`
87			`RTL Output : Yes`
88			`Global Optimization : AllClockNets`
89			`Read Cores : YES`
90			`Write Timing Constraints : NO`
91			`Cross Clock Analysis : NO`
92			`Hierarchy Separator : /`
93			`Bus Delimiter : <>`
94			`Case Specifier : Maintain`
95			`Slice Utilization Ratio : 100`
96			`BRAM Utilization Ratio : 100`
97			`DSP48 Utilization Ratio : 100`
98			`Auto BRAM Packing : NO`
99			`Slice Utilization Ratio Delta : 5`
100
101			`=========================================================================`
102
103
104			`=========================================================================`
105			`* HDL Parsing *`
106			`=========================================================================`
107			`Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\grp_debouncer.vhd" into library work`
108			`Parsing entity .`
109			`Parsing architecture of entity .`
110			`Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" into library work`
111			`Parsing entity .`
112			`Parsing architecture of entity .`
113
114			`=========================================================================`
115			`* HDL Elaboration *`
116			`=========================================================================`
117
118			`Elaborating entity (architecture ) from library .`
119
120			`Elaborating entity (architecture ) with generics from library .`
121	7	jdoin	`WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" Line 71: Net does not have a driver.`
122	6	jdoin
123			`=========================================================================`
124			`* HDL Synthesis *`
125			`=========================================================================`
126
127			`Synthesizing Unit .`
128			`Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/debounce_atlys_top.vhd".`
129	7	jdoin	`WARNING:Xst:2935 - Signal 'dbg<15>', unconnected in block 'debounce_atlys_top', is tied to its initial value (0).`
130			`Found 7-bit register for signal .`
131	6	jdoin	`Summary:`
132	7	jdoin	`inferred 7 D-type flip-flop(s).`
133	6	jdoin	`Unit synthesized.`
134
135			`Synthesizing Unit .`
136			`Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/grp_debouncer.vhd".`
137	7	jdoin	`N = 7`
138	6	jdoin	`CNT_VAL = 5000`
139	7	jdoin	`Found 7-bit register for signal .`
140			`Found 7-bit register for signal .`
141	6	jdoin	`Found 1-bit register for signal .`
142	7	jdoin	`Found 7-bit register for signal .`
143	6	jdoin	`Found 13-bit register for signal .`
144			`Found 14-bit adder for signal created at line 167.`
145	7	jdoin	`Found 7-bit comparator not equal for signal created at line 192`
146			`Found 7-bit comparator not equal for signal created at line 194`
147	6	jdoin	`Summary:`
148			`inferred 1 Adder/Subtractor(s).`
149	7	jdoin	`inferred 35 D-type flip-flop(s).`
150	6	jdoin	`inferred 2 Comparator(s).`
151			`Unit synthesized.`
152
153			`=========================================================================`
154			`HDL Synthesis Report`
155
156			`Macro Statistics`
157			`# Adders/Subtractors : 1`
158			`14-bit adder : 1`
159			`# Registers : 6`
160			`1-bit register : 1`
161			`13-bit register : 1`
162	7	jdoin	`7-bit register : 4`
163	6	jdoin	`# Comparators : 2`
164	7	jdoin	`7-bit comparator not equal : 2`
165	6	jdoin
166			`=========================================================================`
167
168			`=========================================================================`
169			`* Advanced HDL Synthesis *`
170			`=========================================================================`
171
172
173			`Synthesizing (advanced) Unit .`
174			`The following registers are absorbed into counter : 1 register on signal .`
175			`Unit synthesized (advanced).`
176
177			`=========================================================================`
178			`Advanced HDL Synthesis Report`
179
180			`Macro Statistics`
181			`# Counters : 1`
182			`13-bit up counter : 1`
183	7	jdoin	`# Registers : 29`
184			`Flip-Flops : 29`
185	6	jdoin	`# Comparators : 2`
186	7	jdoin	`7-bit comparator not equal : 2`
187	6	jdoin
188			`=========================================================================`
189
190			`=========================================================================`
191			`* Low Level Synthesis *`
192			`=========================================================================`
193
194			`Optimizing unit ...`
195
196			`Optimizing unit ...`
197
198			`Mapping all equations...`
199			`Building and optimizing final netlist ...`
200			`Found area constraint ratio of 100 (+ 5) on block debounce_atlys_top, actual ratio is 0.`
201
202			`Final Macro Processing ...`
203
204			`=========================================================================`
205			`Final Register Report`
206
207			`Macro Statistics`
208	7	jdoin	`# Registers : 42`
209			`Flip-Flops : 42`
210	6	jdoin
211			`=========================================================================`
212
213			`=========================================================================`
214			`* Partition Report *`
215			`=========================================================================`
216
217			`Partition Implementation Status`
218			`-------------------------------`
219
220			`No Partitions were found in this design.`
221
222			`-------------------------------`
223
224			`=========================================================================`
225			`* Design Summary *`
226			`=========================================================================`
227
228			`Top Level Output File Name : debounce_atlys_top.ngc`
229
230			`Primitive and Black Box Usage:`
231			`------------------------------`
232	7	jdoin	`# BELS : 73`
233	6	jdoin	`# GND : 1`
234			`# INV : 1`
235			`# LUT1 : 12`
236	7	jdoin	`# LUT3 : 1`
237			`# LUT4 : 9`
238			`# LUT6 : 23`
239	6	jdoin	`# MUXCY : 12`
240			`# VCC : 1`
241			`# XORCY : 13`
242	7	jdoin	`# FlipFlops/Latches : 42`
243			`# FD : 28`
244			`# FDE : 14`
245	6	jdoin	`# Clock Buffers : 1`
246			`# BUFGP : 1`
247	7	jdoin	`# IO Buffers : 30`
248			`# IBUF : 7`
249			`# OBUF : 23`
250	6	jdoin
251			`Device utilization summary:`
252			`---------------------------`
253
254			`Selected Device : 6slx45csg324-2`
255
256
257			`Slice Logic Utilization:`
258	7	jdoin	`Number of Slice Registers: 42 out of 54576 0%`
259			`Number of Slice LUTs: 46 out of 27288 0%`
260			`Number used as Logic: 46 out of 27288 0%`
261	6	jdoin
262			`Slice Logic Distribution:`
263	7	jdoin	`Number of LUT Flip Flop pairs used: 67`
264			`Number with an unused Flip Flop: 25 out of 67 37%`
265			`Number with an unused LUT: 21 out of 67 31%`
266			`Number of fully used LUT-FF pairs: 21 out of 67 31%`
267	6	jdoin	`Number of unique control sets: 3`
268
269			`IO Utilization:`
270	7	jdoin	`Number of IOs: 31`
271			`Number of bonded IOBs: 31 out of 218 14%`
272	6	jdoin
273			`Specific Feature Utilization:`
274			`Number of BUFG/BUFGCTRLs: 1 out of 16 6%`
275
276			`---------------------------`
277			`Partition Resource Summary:`
278			`---------------------------`
279
280			`No Partitions were found in this design.`
281
282			`---------------------------`
283
284
285			`=========================================================================`
286			`Timing Report`
287
288			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
289			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
290			`GENERATED AFTER PLACE-and-ROUTE.`
291
292			`Clock Information:`
293			`------------------`
294			`-----------------------------------+------------------------+-------+`
295			`Clock Signal \| Clock buffer(FF name) \| Load \|`
296			`-----------------------------------+------------------------+-------+`
297	7	jdoin	`gclk_i \| BUFGP \| 42 \|`
298	6	jdoin	`-----------------------------------+------------------------+-------+`
299
300			`Asynchronous Control Signals Information:`
301			`----------------------------------------`
302			`No asynchronous control signals found in this design`
303
304			`Timing Summary:`
305			`---------------`
306			`Speed Grade: -2`
307
308	7	jdoin	`Minimum period: 4.717ns (Maximum Frequency: 211.999MHz)`
309	6	jdoin	`Minimum input arrival time before clock: 2.127ns`
310	7	jdoin	`Maximum output required time after clock: 4.380ns`
311	6	jdoin	`Maximum combinational path delay: 4.965ns`
312
313			`Timing Details:`
314			`---------------`
315			`All values displayed in nanoseconds (ns)`
316
317			`=========================================================================`
318			`Timing constraint: Default period analysis for Clock 'gclk_i'`
319	7	jdoin	`Clock period: 4.717ns (frequency: 211.999MHz)`
320			`Total number of paths / destination ports: 713 / 49`
321	6	jdoin	`-------------------------------------------------------------------------`
322	7	jdoin	`Delay: 4.717ns (Levels of Logic = 3)`
323	6	jdoin	`Source: Inst_sw_debouncer/cnt_reg_0 (FF)`
324			`Destination: Inst_sw_debouncer/strb_reg (FF)`
325			`Source Clock: gclk_i rising`
326			`Destination Clock: gclk_i rising`
327
328			`Data Path: Inst_sw_debouncer/cnt_reg_0 to Inst_sw_debouncer/strb_reg`
329			`Gate Net`
330			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
331			`---------------------------------------- ------------`
332			`FD:C->Q 2 0.525 1.181 Inst_sw_debouncer/cnt_reg_0 (Inst_sw_debouncer/cnt_reg_0)`
333	7	jdoin	`LUT6:I0->O 8 0.254 1.052 Inst_sw_debouncer/dat_strb<12>1 (Inst_sw_debouncer/dat_strb<12>)`
334	6	jdoin	`LUT3:I1->O 14 0.250 1.127 Inst_sw_debouncer/dat_strb<12>3 (Inst_sw_debouncer/dat_strb)`
335	7	jdoin	`LUT6:I5->O 1 0.254 0.000 Inst_sw_debouncer/strb_next6 (Inst_sw_debouncer/strb_next)`
336	6	jdoin	`FD:D 0.074 Inst_sw_debouncer/strb_reg`
337			`----------------------------------------`
338	7	jdoin	`Total 4.717ns (1.357ns logic, 3.360ns route)`
339			`(28.8% logic, 71.2% route)`
340	6	jdoin
341			`=========================================================================`
342			`Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'`
343	7	jdoin	`Total number of paths / destination ports: 7 / 7`
344	6	jdoin	`-------------------------------------------------------------------------`
345			`Offset: 2.127ns (Levels of Logic = 1)`
346	7	jdoin	`Source: sw_i<6> (PAD)`
347			`Destination: Inst_sw_debouncer/reg_A_6 (FF)`
348	6	jdoin	`Destination Clock: gclk_i rising`
349
350	7	jdoin	`Data Path: sw_i<6> to Inst_sw_debouncer/reg_A_6`
351	6	jdoin	`Gate Net`
352			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
353			`---------------------------------------- ------------`
354	7	jdoin	`IBUF:I->O 2 1.328 0.725 sw_i_6_IBUF (dbg_o_6_OBUF)`
355			`FD:D 0.074 Inst_sw_debouncer/reg_A_6`
356	6	jdoin	`----------------------------------------`
357			`Total 2.127ns (1.402ns logic, 0.725ns route)`
358			`(65.9% logic, 34.1% route)`
359
360			`=========================================================================`
361			`Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'`
362	7	jdoin	`Total number of paths / destination ports: 15 / 15`
363	6	jdoin	`-------------------------------------------------------------------------`
364	7	jdoin	`Offset: 4.380ns (Levels of Logic = 1)`
365	6	jdoin	`Source: Inst_sw_debouncer/strb_reg (FF)`
366	7	jdoin	`Destination: dbg_o<14> (PAD)`
367	6	jdoin	`Source Clock: gclk_i rising`
368
369	7	jdoin	`Data Path: Inst_sw_debouncer/strb_reg to dbg_o<14>`
370	6	jdoin	`Gate Net`
371			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
372			`---------------------------------------- ------------`
373	7	jdoin	`FD:C->Q 8 0.525 0.943 Inst_sw_debouncer/strb_reg (Inst_sw_debouncer/strb_reg)`
374			`OBUF:I->O 2.912 dbg_o_14_OBUF (dbg_o<14>)`
375	6	jdoin	`----------------------------------------`
376	7	jdoin	`Total 4.380ns (3.437ns logic, 0.943ns route)`
377			`(78.5% logic, 21.5% route)`
378	6	jdoin
379			`=========================================================================`
380			`Timing constraint: Default path analysis`
381	7	jdoin	`Total number of paths / destination ports: 7 / 7`
382	6	jdoin	`-------------------------------------------------------------------------`
383			`Delay: 4.965ns (Levels of Logic = 2)`
384	7	jdoin	`Source: sw_i<6> (PAD)`
385			`Destination: dbg_o<6> (PAD)`
386	6	jdoin
387	7	jdoin	`Data Path: sw_i<6> to dbg_o<6>`
388	6	jdoin	`Gate Net`
389			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
390			`---------------------------------------- ------------`
391	7	jdoin	`IBUF:I->O 2 1.328 0.725 sw_i_6_IBUF (dbg_o_6_OBUF)`
392			`OBUF:I->O 2.912 dbg_o_6_OBUF (dbg_o<6>)`
393	6	jdoin	`----------------------------------------`
394			`Total 4.965ns (4.240ns logic, 0.725ns route)`
395			`(85.4% logic, 14.6% route)`
396
397			`=========================================================================`
398
399			`Cross Clock Domains Report:`
400			`--------------------------`
401
402			`Clock to Setup on destination clock gclk_i`
403			`---------------+---------+---------+---------+---------+`
404			`\| Src:Rise\| Src:Fall\| Src:Rise\| Src:Fall\|`
405			`Source Clock \|Dest:Rise\|Dest:Rise\|Dest:Fall\|Dest:Fall\|`
406			`---------------+---------+---------+---------+---------+`
407	7	jdoin	`gclk_i \| 4.717\| \| \| \|`
408	6	jdoin	`---------------+---------+---------+---------+---------+`
409
410			`=========================================================================`
411
412
413			`Total REAL time to Xst completion: 4.00 secs`
414	7	jdoin	`Total CPU time to Xst completion: 4.57 secs`
415	6	jdoin
416			`-->`
417
418	7	jdoin	`Total memory usage is 185320 kilobytes`
419	6	jdoin
420			`Number of errors : 0 ( 0 filtered)`
421	7	jdoin	`Number of warnings : 2 ( 0 filtered)`
422	6	jdoin	`Number of infos : 0 ( 0 filtered)`
423

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