OpenCores
URL https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk

Subversion Repositories debouncer_vhdl

[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys_top.twr] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 jdoin 
--------------------------------------------------------------------------------
2 
Release 13.1 Trace  (nt)
3 
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
4 
 
5 
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
6 
3 -fastpaths -xml debounce_atlys_top.twx debounce_atlys_top.ncd -o
7 
debounce_atlys_top.twr debounce_atlys_top.pcf -ucf debounce_atlys.ucf
8 
 
9 
Design file:              debounce_atlys_top.ncd
10 
Physical constraint file: debounce_atlys_top.pcf
11 
Device,package,speed:     xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
12 
Report level:             verbose report
13 
 
14 
Environment Variable      Effect
15 
--------------------      ------
16 
NONE                      No environment variables were set
17 
--------------------------------------------------------------------------------
18 
 
19 
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
20 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
21 
   option. All paths that are not constrained will be reported in the
22 
   unconstrained paths section(s) of the report.
23 
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
24 
   a 50 Ohm transmission line loading model.  For the details of this model,
25 
   and for more information on accounting for different loading conditions,
26 
   please see the device datasheet.
27 
 
28 
 
29 
 
30 
Data Sheet report:
31 
-----------------
32 
All values displayed in nanoseconds (ns)
33 
 
34 
Setup/Hold to clock gclk_i
35 
------------+------------+------------+------------+------------+------------------+--------+
36 
            |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
37 
Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
38 
------------+------------+------------+------------+------------+------------------+--------+
39 
sw_i<0>     |    5.038(R)|      SLOW  |   -2.761(R)|      FAST  |gclk_i_BUFGP      |   0.000|
40 
sw_i<1>     |    5.576(R)|      SLOW  |   -3.098(R)|      FAST  |gclk_i_BUFGP      |   0.000|
41 
sw_i<2>     |    5.317(R)|      SLOW  |   -2.953(R)|      FAST  |gclk_i_BUFGP      |   0.000|
42 
sw_i<3>     |    4.491(R)|      SLOW  |   -2.388(R)|      FAST  |gclk_i_BUFGP      |   0.000|
43 
sw_i<4>     |    2.742(R)|      SLOW  |   -1.466(R)|      FAST  |gclk_i_BUFGP      |   0.000|
44 
sw_i<5>     |    4.819(R)|      SLOW  |   -2.715(R)|      FAST  |gclk_i_BUFGP      |   0.000|
45 
sw_i<6>     |    4.336(R)|      SLOW  |   -2.454(R)|      FAST  |gclk_i_BUFGP      |   0.000|
46 
sw_i<7>     |    5.893(R)|      SLOW  |   -3.333(R)|      FAST  |gclk_i_BUFGP      |   0.000|
47 
------------+------------+------------+------------+------------+------------------+--------+
48 
 
49 
Clock gclk_i to Pad
50 
------------+-----------------+------------+-----------------+------------+------------------+--------+
51 
            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
52 
Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
53 
------------+-----------------+------------+-----------------+------------+------------------+--------+
54 
dbg_o<8>    |        11.232(R)|      SLOW  |         4.814(R)|      FAST  |gclk_i_BUFGP      |   0.000|
55 
dbg_o<9>    |        11.480(R)|      SLOW  |         4.979(R)|      FAST  |gclk_i_BUFGP      |   0.000|
56 
dbg_o<10>   |        11.254(R)|      SLOW  |         4.861(R)|      FAST  |gclk_i_BUFGP      |   0.000|
57 
dbg_o<11>   |        11.049(R)|      SLOW  |         4.732(R)|      FAST  |gclk_i_BUFGP      |   0.000|
58 
dbg_o<12>   |        11.559(R)|      SLOW  |         5.013(R)|      FAST  |gclk_i_BUFGP      |   0.000|
59 
dbg_o<13>   |        11.939(R)|      SLOW  |         5.209(R)|      FAST  |gclk_i_BUFGP      |   0.000|
60 
dbg_o<14>   |        12.377(R)|      SLOW  |         5.519(R)|      FAST  |gclk_i_BUFGP      |   0.000|
61 
dbg_o<15>   |        12.060(R)|      SLOW  |         5.330(R)|      FAST  |gclk_i_BUFGP      |   0.000|
62 
led_o<0>    |         9.814(R)|      SLOW  |         4.065(R)|      FAST  |gclk_i_BUFGP      |   0.000|
63 
led_o<1>    |         9.656(R)|      SLOW  |         3.955(R)|      FAST  |gclk_i_BUFGP      |   0.000|
64 
led_o<2>    |         9.469(R)|      SLOW  |         3.865(R)|      FAST  |gclk_i_BUFGP      |   0.000|
65 
led_o<3>    |         9.929(R)|      SLOW  |         4.132(R)|      FAST  |gclk_i_BUFGP      |   0.000|
66 
led_o<4>    |         9.577(R)|      SLOW  |         3.889(R)|      FAST  |gclk_i_BUFGP      |   0.000|
67 
led_o<5>    |        17.272(R)|      SLOW  |         8.413(R)|      FAST  |gclk_i_BUFGP      |   0.000|
68 
led_o<6>    |        11.323(R)|      SLOW  |         4.861(R)|      FAST  |gclk_i_BUFGP      |   0.000|
69 
led_o<7>    |        10.605(R)|      SLOW  |         4.453(R)|      FAST  |gclk_i_BUFGP      |   0.000|
70 
strb_o      |        13.397(R)|      SLOW  |         6.237(R)|      FAST  |gclk_i_BUFGP      |   0.000|
71 
------------+-----------------+------------+-----------------+------------+------------------+--------+
72 
 
73 
Clock to Setup on destination clock gclk_i
74 
---------------+---------+---------+---------+---------+
75 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
76 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
77 
---------------+---------+---------+---------+---------+
78 
gclk_i         |    4.464|         |         |         |
79 
---------------+---------+---------+---------+---------+
80 
 
81 
Pad to Pad
82 
---------------+---------------+---------+
83 
Source Pad     |Destination Pad|  Delay  |
84 
---------------+---------------+---------+
85 
sw_i<0>        |dbg_o<0>       |   16.209|
86 
sw_i<1>        |dbg_o<1>       |   16.941|
87 
sw_i<2>        |dbg_o<2>       |   16.803|
88 
sw_i<3>        |dbg_o<3>       |    9.229|
89 
sw_i<4>        |dbg_o<4>       |    7.980|
90 
sw_i<5>        |dbg_o<5>       |    8.917|
91 
sw_i<6>        |dbg_o<6>       |    9.026|
92 
sw_i<7>        |dbg_o<7>       |   15.558|
93 
---------------+---------------+---------+
94 
 
95 
 
96 
Analysis completed Thu Aug 11 00:07:33 2011
97 
--------------------------------------------------------------------------------
98 
 
99 
Trace Settings:
100 
-------------------------
101 
Trace Settings
102 
 
103 
Peak Memory Usage: 178 MB
104 
 
105 
 
106 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.