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[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys_top_map.map] - Blame information for rev 6

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Release 13.1 Map O.40d (nt)
Xilinx Map Application Log File for Design 'debounce_atlys_top'
 
Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
off -o debounce_atlys_top_map.ncd debounce_atlys_top.ngd debounce_atlys_top.pcf
Target Device  : xc6slx45
Target Package : csg324
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Thu Aug 11 00:07:05 2011
 
Running global optimization...
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 7 secs
Total CPU  time at the beginning of Placer: 7 secs
 
Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:74f3dbc5) REAL time: 8 secs
 
Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:74f3dbc5) REAL time: 8 secs
 
Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:74f3dbc5) REAL time: 8 secs
 
Phase 4.2  Initial Placement for Architecture Specific Features
 
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:d6fae235) REAL time: 10 secs
 
Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
 
Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:d6fae235) REAL time: 10 secs
 
Phase 7.3  Local Placement Optimization
Phase 7.3  Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
 
Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
 
Phase 9.8  Global Placement
...
..
Phase 9.8  Global Placement (Checksum:2b00d50b) REAL time: 10 secs
 
Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:2b00d50b) REAL time: 10 secs
 
Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:1f5fecef) REAL time: 11 secs
 
Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:1f5fecef) REAL time: 11 secs
 
Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:1bfd6a39) REAL time: 11 secs
 
Total REAL time to Placer completion: 11 secs
Total CPU  time to Placer completion: 11 secs
Running post-placement packing...
Writing output files...
 
Design Summary
--------------
 
Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                    46 out of  54,576    1%
    Number used as Flip Flops:                  46
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                         43 out of  27,288    1%
    Number used as logic:                       38 out of  27,288    1%
      Number using O6 output only:              18
      Number using O5 output only:              12
      Number using O5 and O6:                    8
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   6,408    0%
    Number used exclusively as route-thrus:      5
      Number with same-slice register load:      4
      Number with same-slice carry load:         1
      Number with other load:                    0
 
Slice Logic Distribution:
  Number of occupied Slices:                    17 out of   6,822    1%
  Number of LUT Flip Flop pairs used:           57
    Number with an unused Flip Flop:            21 out of      57   36%
    Number with an unused LUT:                  14 out of      57   24%
    Number of fully used LUT-FF pairs:          22 out of      57   38%
    Number of unique control sets:               3
    Number of slice register sites lost
      to control set restrictions:               2 out of  54,576    1%
 
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
  Number of bonded IOBs:                        34 out of     218   15%
    Number of LOCed IOBs:                       34 out of      34  100%
 
Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
    Number used as BUFGs:                        1
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%
 
Average Fanout of Non-Clock Nets:                2.57
 
Peak Memory Usage:  299 MB
Total REAL time to MAP completion:  11 secs
Total CPU time to MAP completion (all processors):   11 secs
 
Mapping completed.
See MAP report file "debounce_atlys_top_map.mrp" for details.

Line No.	Rev	Author	Line
1	6	jdoin	`Release 13.1 Map O.40d (nt)`
2			`Xilinx Map Application Log File for Design 'debounce_atlys_top'`
3
4			`Design Information`
5			`------------------`
6			`Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol`
7			`high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area`
8			`-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power`
9			`off -o debounce_atlys_top_map.ncd debounce_atlys_top.ngd debounce_atlys_top.pcf`
10			`Target Device : xc6slx45`
11			`Target Package : csg324`
12			`Target Speed : -2`
13			`Mapper Version : spartan6 -- $Revision: 1.55 $`
14			`Mapped Date : Thu Aug 11 00:07:05 2011`
15
16			`Running global optimization...`
17			`Mapping design into LUTs...`
18			`Running directed packing...`
19			`Running delay-based LUT packing...`
20			`Updating timing models...`
21			`INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report`
22			`(.mrp).`
23			`Running timing-driven placement...`
24			`Total REAL time at the beginning of Placer: 7 secs`
25			`Total CPU time at the beginning of Placer: 7 secs`
26
27			`Phase 1.1 Initial Placement Analysis`
28			`Phase 1.1 Initial Placement Analysis (Checksum:74f3dbc5) REAL time: 8 secs`
29
30			`Phase 2.7 Design Feasibility Check`
31			`Phase 2.7 Design Feasibility Check (Checksum:74f3dbc5) REAL time: 8 secs`
32
33			`Phase 3.31 Local Placement Optimization`
34			`Phase 3.31 Local Placement Optimization (Checksum:74f3dbc5) REAL time: 8 secs`
35
36			`Phase 4.2 Initial Placement for Architecture Specific Features`
37
38			`Phase 4.2 Initial Placement for Architecture Specific Features`
39			`(Checksum:d6fae235) REAL time: 10 secs`
40
41			`Phase 5.36 Local Placement Optimization`
42			`Phase 5.36 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs`
43
44			`Phase 6.30 Global Clock Region Assignment`
45			`Phase 6.30 Global Clock Region Assignment (Checksum:d6fae235) REAL time: 10 secs`
46
47			`Phase 7.3 Local Placement Optimization`
48			`Phase 7.3 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs`
49
50			`Phase 8.5 Local Placement Optimization`
51			`Phase 8.5 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs`
52
53			`Phase 9.8 Global Placement`
54			`...`
55			`..`
56			`Phase 9.8 Global Placement (Checksum:2b00d50b) REAL time: 10 secs`
57
58			`Phase 10.5 Local Placement Optimization`
59			`Phase 10.5 Local Placement Optimization (Checksum:2b00d50b) REAL time: 10 secs`
60
61			`Phase 11.18 Placement Optimization`
62			`Phase 11.18 Placement Optimization (Checksum:1f5fecef) REAL time: 11 secs`
63
64			`Phase 12.5 Local Placement Optimization`
65			`Phase 12.5 Local Placement Optimization (Checksum:1f5fecef) REAL time: 11 secs`
66
67			`Phase 13.34 Placement Validation`
68			`Phase 13.34 Placement Validation (Checksum:1bfd6a39) REAL time: 11 secs`
69
70			`Total REAL time to Placer completion: 11 secs`
71			`Total CPU time to Placer completion: 11 secs`
72			`Running post-placement packing...`
73			`Writing output files...`
74
75			`Design Summary`
76			`--------------`
77
78			`Design Summary:`
79			`Number of errors: 0`
80			`Number of warnings: 0`
81			`Slice Logic Utilization:`
82			`Number of Slice Registers: 46 out of 54,576 1%`
83			`Number used as Flip Flops: 46`
84			`Number used as Latches: 0`
85			`Number used as Latch-thrus: 0`
86			`Number used as AND/OR logics: 0`
87			`Number of Slice LUTs: 43 out of 27,288 1%`
88			`Number used as logic: 38 out of 27,288 1%`
89			`Number using O6 output only: 18`
90			`Number using O5 output only: 12`
91			`Number using O5 and O6: 8`
92			`Number used as ROM: 0`
93			`Number used as Memory: 0 out of 6,408 0%`
94			`Number used exclusively as route-thrus: 5`
95			`Number with same-slice register load: 4`
96			`Number with same-slice carry load: 1`
97			`Number with other load: 0`
98
99			`Slice Logic Distribution:`
100			`Number of occupied Slices: 17 out of 6,822 1%`
101			`Number of LUT Flip Flop pairs used: 57`
102			`Number with an unused Flip Flop: 21 out of 57 36%`
103			`Number with an unused LUT: 14 out of 57 24%`
104			`Number of fully used LUT-FF pairs: 22 out of 57 38%`
105			`Number of unique control sets: 3`
106			`Number of slice register sites lost`
107			`to control set restrictions: 2 out of 54,576 1%`
108
109			`A LUT Flip Flop pair for this architecture represents one LUT paired with`
110			`one Flip Flop within a slice. A control set is a unique combination of`
111			`clock, reset, set, and enable signals for a registered element.`
112			`The Slice Logic Distribution report is not meaningful if the design is`
113			`over-mapped for a non-slice resource or if Placement fails.`
114
115			`IO Utilization:`
116			`Number of bonded IOBs: 34 out of 218 15%`
117			`Number of LOCed IOBs: 34 out of 34 100%`
118
119			`Specific Feature Utilization:`
120			`Number of RAMB16BWERs: 0 out of 116 0%`
121			`Number of RAMB8BWERs: 0 out of 232 0%`
122			`Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%`
123			`Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%`
124			`Number of BUFG/BUFGMUXs: 1 out of 16 6%`
125			`Number used as BUFGs: 1`
126			`Number used as BUFGMUX: 0`
127			`Number of DCM/DCM_CLKGENs: 0 out of 8 0%`
128			`Number of ILOGIC2/ISERDES2s: 0 out of 376 0%`
129			`Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%`
130			`Number of OLOGIC2/OSERDES2s: 0 out of 376 0%`
131			`Number of BSCANs: 0 out of 4 0%`
132			`Number of BUFHs: 0 out of 256 0%`
133			`Number of BUFPLLs: 0 out of 8 0%`
134			`Number of BUFPLL_MCBs: 0 out of 4 0%`
135			`Number of DSP48A1s: 0 out of 58 0%`
136			`Number of ICAPs: 0 out of 1 0%`
137			`Number of MCBs: 0 out of 2 0%`
138			`Number of PCILOGICSEs: 0 out of 2 0%`
139			`Number of PLL_ADVs: 0 out of 4 0%`
140			`Number of PMVs: 0 out of 1 0%`
141			`Number of STARTUPs: 0 out of 1 0%`
142			`Number of SUSPEND_SYNCs: 0 out of 1 0%`
143
144			`Average Fanout of Non-Clock Nets: 2.57`
145
146			`Peak Memory Usage: 299 MB`
147			`Total REAL time to MAP completion: 11 secs`
148			`Total CPU time to MAP completion (all processors): 11 secs`
149
150			`Mapping completed.`
151			`See MAP report file "debounce_atlys_top_map.mrp" for details.`

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[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys_top_map.map] - Blame information for rev 6