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jdoin |
Release 13.1 Map O.40d (nt)
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Xilinx Mapping Report File for Design 'debounce_atlys_top'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
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high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
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-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
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off -o debounce_atlys_top_map.ncd debounce_atlys_top.ngd debounce_atlys_top.pcf
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Target Device : xc6slx45
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Target Package : csg324
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Target Speed : -2
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Mapper Version : spartan6 -- $Revision: 1.55 $
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Mapped Date : Thu Aug 11 00:07:05 2011
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Design Summary
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--------------
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Number of errors: 0
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Number of warnings: 0
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Slice Logic Utilization:
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Number of Slice Registers: 46 out of 54,576 1%
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Number used as Flip Flops: 46
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 43 out of 27,288 1%
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Number used as logic: 38 out of 27,288 1%
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Number using O6 output only: 18
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Number using O5 output only: 12
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Number using O5 and O6: 8
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Number used as ROM: 0
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Number used as Memory: 0 out of 6,408 0%
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Number used exclusively as route-thrus: 5
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Number with same-slice register load: 4
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Number with same-slice carry load: 1
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 17 out of 6,822 1%
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Number of LUT Flip Flop pairs used: 57
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Number with an unused Flip Flop: 21 out of 57 36%
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Number with an unused LUT: 14 out of 57 24%
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Number of fully used LUT-FF pairs: 22 out of 57 38%
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Number of unique control sets: 3
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Number of slice register sites lost
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to control set restrictions: 2 out of 54,576 1%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 34 out of 218 15%
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Number of LOCed IOBs: 34 out of 34 100%
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 116 0%
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Number of RAMB8BWERs: 0 out of 232 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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Number of BUFG/BUFGMUXs: 1 out of 16 6%
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Number used as BUFGs: 1
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 8 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
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Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 256 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 58 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 0 out of 4 0%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Average Fanout of Non-Clock Nets: 2.57
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Peak Memory Usage: 299 MB
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Total REAL time to MAP completion: 11 secs
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Total CPU time to MAP completion (all processors): 11 secs
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group and Partition Summary
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Section 10 - Timing Report
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Section 11 - Configuration String Information
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Section 12 - Control Set Information
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Section 13 - Utilization by Hierarchy
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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Section 3 - Informational
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-------------------------
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INFO:Map:284 - Map is running with the multi-threading option on. Map currently
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supports the use of up to 2 processors. Based on the the user options and
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machine load, Map will use 2 processors during this run.
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INFO:LIT:243 - Logical network gclk_i_BUFGP/N2 has no load.
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INFO:LIT:243 - Logical network gclk_i_BUFGP/N3 has no load.
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INFO:MapLib:562 - No environment variables are currently set.
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INFO:LIT:244 - All of the single ended outputs in this design are using slew
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rate limited output drivers. The delay on speed critical single ended outputs
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can be dramatically reduced by designating them as fast outputs.
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INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
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0.000 to 85.000 Celsius)
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INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
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1.260 Volts)
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INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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(.mrp).
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INFO:Pack:1650 - Map created a placed design.
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Section 4 - Removed Logic Summary
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---------------------------------
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2 block(s) removed
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2 block(s) optimized away
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2 signal(s) removed
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12 Block(s) redundant
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Section 5 - Removed Logic
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-------------------------
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The trimmed logic report below shows the logic removed from your design due to
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sourceless or loadless signals, and VCC or ground connections. If the removal
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of a signal or symbol results in the subsequent removal of an additional signal
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or symbol, the message explaining that second removal will be indented. This
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indentation will be repeated as a chain of related logic is removed.
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To quickly locate the original cause for the removal of a chain of logic, look
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above the place where that logic is listed in the trimming report, then locate
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the lines that are least indented (begin at the leftmost edge).
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The signal "gclk_i_BUFGP/N2" is sourceless and has been removed.
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The signal "gclk_i_BUFGP/N3" is sourceless and has been removed.
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Unused block "gclk_i_BUFGP/XST_GND" (ZERO) removed.
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Unused block "gclk_i_BUFGP/XST_VCC" (ONE) removed.
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Optimized Block(s):
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TYPE BLOCK
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GND XST_GND
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VCC XST_VCC
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Redundant Block(s):
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TYPE BLOCK
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<11>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<10>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<9>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<8>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<7>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
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LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<12>_rt
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Section 6 - IOB Properties
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--------------------------
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
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| | | | | Term | Strength | Rate | | | Delay |
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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| dbg_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| dbg_o<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| gclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
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| led_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| led_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| led_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| led_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| led_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| led_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| led_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| led_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| strb_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| sw_i<0> | IOB | INPUT | LVCMOS25 | | | | | | |
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| sw_i<1> | IOB | INPUT | LVCMOS25 | | | | | | |
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| sw_i<2> | IOB | INPUT | LVCMOS25 | | | | | | |
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| sw_i<3> | IOB | INPUT | LVCMOS25 | | | | | | |
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| sw_i<4> | IOB | INPUT | LVCMOS25 | | | | | | |
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| sw_i<5> | IOB | INPUT | LVCMOS25 | | | | | | |
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| sw_i<6> | IOB | INPUT | LVCMOS25 | | | | | | |
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| sw_i<7> | IOB | INPUT | LVCMOS25 | | | | | | |
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group and Partition Summary
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--------------------------------------------
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Area Group Information
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----------------------
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No area groups were found in this design.
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----------------------
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Section 10 - Timing Report
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--------------------------
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A logic-level (pre-route) timing report can be generated by using Xilinx static
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timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
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mapped NCD and PCF files. Please note that this timing report will be generated
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using estimated delay information. For accurate numbers, please generate a
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timing report with the post Place and Route NCD file.
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For more information about the Timing Analyzer, consult the Xilinx Timing
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Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
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Command Line Tools User Guide "TRACE" chapter.
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| 253 |
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Section 11 - Configuration String Details
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-----------------------------------------
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| 256 |
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Section 12 - Control Set Information
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------------------------------------
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+-----------------------------------------------------------------------------------------------------------+
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| Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count |
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+-----------------------------------------------------------------------------------------------------------+
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| gclk_i_BUFGP | | | | 7 | 30 |
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| gclk_i_BUFGP | | | Inst_sw_debouncer/strb_reg | 2 | 8 |
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| gclk_i_BUFGP | | | lut119_33 | 3 | 8 |
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+-----------------------------------------------------------------------------------------------------------+
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Section 13 - Utilization by Hierarchy
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-------------------------------------
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name |
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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| debounce_atlys_top/ | | 12/26 | 8/46 | 26/27 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | debounce_atlys_top |
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| +Inst_sw_debouncer | | 14/14 | 38/38 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | debounce_atlys_top/Inst_sw_debouncer |
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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* Slices can be packed with basic elements from multiple hierarchies.
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Therefore, a slice will be counted in every hierarchical module
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that each of its packed basic elements belong to.
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** For each column, there are two numbers reported /.
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is the number of elements that belong to that specific hierarchical module.
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is the total number of elements from that hierarchical module and any lower level
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hierarchical modules below.
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*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
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