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jdoin |
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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jdoin |
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status (08/15/2011 - 23:26:18)</B></TD></TR>
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jdoin |
<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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<TD>debounce_vhdl_bench.xise</TD>
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<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
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jdoin |
<TD> No Errors </TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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<TD>debounce_atlys_top</TD>
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<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
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jdoin |
<TD>Programming File Generated</TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
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<TD>xc6slx45-2csg324</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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jdoin |
<TD>
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No Errors</TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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jdoin |
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/*.xmsgs?&DataKey=Warning'>3 Warnings (3 new)</A></TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
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<TD>Balanced</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
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<TD>
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jdoin |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.unroutes'>All Signals Completely Routed</A></TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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jdoin |
<TD>
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<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
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jdoin |
<TD>
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<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_envsettings.html'>
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System Settings</A>
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</TD>
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jdoin |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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jdoin |
<TD>0 <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
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jdoin |
</TR>
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</TABLE>
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jdoin |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
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<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
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jdoin |
<TD ALIGN=RIGHT>42</TD>
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jdoin |
<TD ALIGN=RIGHT>54,576</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
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jdoin |
<TD ALIGN=RIGHT>42</TD>
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jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
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jdoin |
<TD ALIGN=RIGHT>37</TD>
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jdoin |
<TD ALIGN=RIGHT>27,288</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
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jdoin |
<TD ALIGN=RIGHT>36</TD>
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jdoin |
<TD ALIGN=RIGHT>27,288</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
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<TD ALIGN=RIGHT>18</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
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7 |
jdoin |
<TD ALIGN=RIGHT>11</TD>
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112 |
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jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
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117 |
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jdoin |
<TD ALIGN=RIGHT>7</TD>
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118 |
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jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD ALIGN=RIGHT>6,408</TD>
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<TD ALIGN=RIGHT>0%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
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jdoin |
<TD ALIGN=RIGHT>1</TD>
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jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
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jdoin |
<TD ALIGN=RIGHT>0</TD>
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142 |
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jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
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147 |
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<TD ALIGN=RIGHT>1</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
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jdoin |
<TD ALIGN=RIGHT>19</TD>
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jdoin |
<TD ALIGN=RIGHT>6,822</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
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165 |
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jdoin |
<TD ALIGN=RIGHT>56</TD>
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166 |
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jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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170 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
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171 |
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jdoin |
<TD ALIGN=RIGHT>20</TD>
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172 |
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<TD ALIGN=RIGHT>56</TD>
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<TD ALIGN=RIGHT>35%</TD>
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jdoin |
<TD COLSPAN='2'> </TD>
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</TR>
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176 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
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177 |
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jdoin |
<TD ALIGN=RIGHT>19</TD>
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<TD ALIGN=RIGHT>56</TD>
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<TD ALIGN=RIGHT>33%</TD>
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jdoin |
<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
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183 |
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jdoin |
<TD ALIGN=RIGHT>17</TD>
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<TD ALIGN=RIGHT>56</TD>
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<TD ALIGN=RIGHT>30%</TD>
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jdoin |
<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
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189 |
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<TD ALIGN=RIGHT>3</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
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195 |
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jdoin |
<TD ALIGN=RIGHT>6</TD>
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196 |
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jdoin |
<TD ALIGN=RIGHT>54,576</TD>
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197 |
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<TD ALIGN=RIGHT>1%</TD>
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198 |
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<TD COLSPAN='2'> </TD>
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199 |
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
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jdoin |
<TD ALIGN=RIGHT>31</TD>
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202 |
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jdoin |
<TD ALIGN=RIGHT>218</TD>
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203 |
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jdoin |
<TD ALIGN=RIGHT>14%</TD>
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204 |
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jdoin |
<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD>
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207 |
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jdoin |
<TD ALIGN=RIGHT>31</TD>
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208 |
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<TD ALIGN=RIGHT>31</TD>
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209 |
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jdoin |
<TD ALIGN=RIGHT>100%</TD>
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210 |
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<TD COLSPAN='2'> </TD>
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211 |
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</TR>
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212 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
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213 |
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<TD ALIGN=RIGHT>0</TD>
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214 |
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<TD ALIGN=RIGHT>116</TD>
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215 |
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<TD ALIGN=RIGHT>0%</TD>
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216 |
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<TD COLSPAN='2'> </TD>
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217 |
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</TR>
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218 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
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219 |
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<TD ALIGN=RIGHT>0</TD>
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220 |
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<TD ALIGN=RIGHT>232</TD>
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221 |
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<TD ALIGN=RIGHT>0%</TD>
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222 |
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<TD COLSPAN='2'> </TD>
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223 |
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</TR>
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224 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
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225 |
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<TD ALIGN=RIGHT>0</TD>
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226 |
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<TD ALIGN=RIGHT>32</TD>
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227 |
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<TD ALIGN=RIGHT>0%</TD>
|
228 |
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<TD COLSPAN='2'> </TD>
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229 |
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</TR>
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230 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
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231 |
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<TD ALIGN=RIGHT>0</TD>
|
232 |
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<TD ALIGN=RIGHT>32</TD>
|
233 |
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<TD ALIGN=RIGHT>0%</TD>
|
234 |
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<TD COLSPAN='2'> </TD>
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235 |
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</TR>
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236 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
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237 |
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<TD ALIGN=RIGHT>1</TD>
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238 |
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<TD ALIGN=RIGHT>16</TD>
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239 |
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<TD ALIGN=RIGHT>6%</TD>
|
240 |
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<TD COLSPAN='2'> </TD>
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241 |
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</TR>
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242 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
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243 |
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<TD ALIGN=RIGHT>1</TD>
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244 |
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<TD> </TD>
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245 |
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<TD> </TD>
|
246 |
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<TD COLSPAN='2'> </TD>
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247 |
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</TR>
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248 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD>
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249 |
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<TD ALIGN=RIGHT>0</TD>
|
250 |
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<TD> </TD>
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251 |
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<TD> </TD>
|
252 |
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<TD COLSPAN='2'> </TD>
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253 |
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</TR>
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254 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
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255 |
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<TD ALIGN=RIGHT>0</TD>
|
256 |
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<TD ALIGN=RIGHT>8</TD>
|
257 |
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<TD ALIGN=RIGHT>0%</TD>
|
258 |
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<TD COLSPAN='2'> </TD>
|
259 |
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</TR>
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260 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
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261 |
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<TD ALIGN=RIGHT>0</TD>
|
262 |
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<TD ALIGN=RIGHT>376</TD>
|
263 |
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<TD ALIGN=RIGHT>0%</TD>
|
264 |
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<TD COLSPAN='2'> </TD>
|
265 |
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</TR>
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266 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
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267 |
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<TD ALIGN=RIGHT>0</TD>
|
268 |
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<TD ALIGN=RIGHT>376</TD>
|
269 |
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<TD ALIGN=RIGHT>0%</TD>
|
270 |
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<TD COLSPAN='2'> </TD>
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271 |
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</TR>
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272 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
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273 |
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<TD ALIGN=RIGHT>0</TD>
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274 |
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<TD ALIGN=RIGHT>376</TD>
|
275 |
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<TD ALIGN=RIGHT>0%</TD>
|
276 |
|
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<TD COLSPAN='2'> </TD>
|
277 |
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</TR>
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278 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
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279 |
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<TD ALIGN=RIGHT>0</TD>
|
280 |
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<TD ALIGN=RIGHT>4</TD>
|
281 |
|
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<TD ALIGN=RIGHT>0%</TD>
|
282 |
|
|
<TD COLSPAN='2'> </TD>
|
283 |
|
|
</TR>
|
284 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
|
285 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
286 |
|
|
<TD ALIGN=RIGHT>256</TD>
|
287 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
288 |
|
|
<TD COLSPAN='2'> </TD>
|
289 |
|
|
</TR>
|
290 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
|
291 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
292 |
|
|
<TD ALIGN=RIGHT>8</TD>
|
293 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
294 |
|
|
<TD COLSPAN='2'> </TD>
|
295 |
|
|
</TR>
|
296 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
|
297 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
298 |
|
|
<TD ALIGN=RIGHT>4</TD>
|
299 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
300 |
|
|
<TD COLSPAN='2'> </TD>
|
301 |
|
|
</TR>
|
302 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
|
303 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
304 |
|
|
<TD ALIGN=RIGHT>58</TD>
|
305 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
306 |
|
|
<TD COLSPAN='2'> </TD>
|
307 |
|
|
</TR>
|
308 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
|
309 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
310 |
|
|
<TD ALIGN=RIGHT>1</TD>
|
311 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
312 |
|
|
<TD COLSPAN='2'> </TD>
|
313 |
|
|
</TR>
|
314 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
|
315 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
316 |
|
|
<TD ALIGN=RIGHT>2</TD>
|
317 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
318 |
|
|
<TD COLSPAN='2'> </TD>
|
319 |
|
|
</TR>
|
320 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
|
321 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
322 |
|
|
<TD ALIGN=RIGHT>2</TD>
|
323 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
324 |
|
|
<TD COLSPAN='2'> </TD>
|
325 |
|
|
</TR>
|
326 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
|
327 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
328 |
|
|
<TD ALIGN=RIGHT>4</TD>
|
329 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
330 |
|
|
<TD COLSPAN='2'> </TD>
|
331 |
|
|
</TR>
|
332 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
|
333 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
334 |
|
|
<TD ALIGN=RIGHT>1</TD>
|
335 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
336 |
|
|
<TD COLSPAN='2'> </TD>
|
337 |
|
|
</TR>
|
338 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
|
339 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
340 |
|
|
<TD ALIGN=RIGHT>1</TD>
|
341 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
342 |
|
|
<TD COLSPAN='2'> </TD>
|
343 |
|
|
</TR>
|
344 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
|
345 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
346 |
|
|
<TD ALIGN=RIGHT>1</TD>
|
347 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
348 |
|
|
<TD COLSPAN='2'> </TD>
|
349 |
|
|
</TR>
|
350 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
351 |
7 |
jdoin |
<TD ALIGN=RIGHT>2.37</TD>
|
352 |
6 |
jdoin |
<TD> </TD>
|
353 |
|
|
<TD> </TD>
|
354 |
|
|
<TD COLSPAN='2'> </TD>
|
355 |
|
|
</TR>
|
356 |
|
|
</TABLE>
|
357 |
3 |
jdoin |
|
358 |
|
|
|
359 |
|
|
|
360 |
6 |
jdoin |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
361 |
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
|
362 |
|
|
<TR ALIGN=LEFT>
|
363 |
|
|
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
|
364 |
|
|
<TD>0 (Setup: 0, Hold: 0)</TD>
|
365 |
|
|
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
|
366 |
|
|
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
|
367 |
|
|
</TR>
|
368 |
|
|
<TR ALIGN=LEFT>
|
369 |
|
|
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
|
370 |
|
|
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.unroutes'>All Signals Completely Routed</A></TD>
|
371 |
|
|
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
|
372 |
|
|
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
|
373 |
|
|
</TR>
|
374 |
|
|
<TR ALIGN=LEFT>
|
375 |
|
|
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
|
376 |
|
|
<TD>
|
377 |
|
|
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
378 |
|
|
<TD BGCOLOR='#FFFF99'><B> </B></TD>
|
379 |
|
|
<TD COLSPAN='2'> </TD>
|
380 |
|
|
</TABLE>
|
381 |
3 |
jdoin |
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
385 |
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
386 |
|
|
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
387 |
|
|
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
388 |
8 |
jdoin |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:02 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/xst.xmsgs?&DataKey=Warning'>2 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
389 |
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:16 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
390 |
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:36 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (9 new)</A></TD></TR>
|
391 |
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:47 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
|
392 |
3 |
jdoin |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
393 |
8 |
jdoin |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:54 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
|
394 |
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:26:11 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
395 |
3 |
jdoin |
</TABLE>
|
396 |
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
397 |
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
398 |
|
|
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
399 |
8 |
jdoin |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Aug 15 23:25:35 2011</TD></TR>
|
400 |
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon Aug 15 23:26:12 2011</TD></TR>
|
401 |
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon Aug 15 23:26:18 2011</TD></TR>
|
402 |
3 |
jdoin |
</TABLE>
|
403 |
|
|
|
404 |
|
|
|
405 |
8 |
jdoin |
<br><center><b>Date Generated:</b> 08/15/2011 - 23:26:18</center>
|
406 |
3 |
jdoin |
</BODY></HTML>
|