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###############################################################################
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#
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# Design Specification
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#
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# Author: Rudolf Usselmann
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#         rudi@asics.ws
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#
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# Revision:
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# 5/10/01 RU Initial Sript
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#
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#
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###############################################################################
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# ==============================================
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# Setup Design Parameters
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set design_files {sbox2 sbox4 sbox6 sbox8 sbox1 sbox3 sbox5 sbox7 crp key_sel des}
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set design_name des
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set active_design des
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# Next Statement defines all clocks and resets in the design
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set special_net {clk}
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set hdl_src_dir {../../rtl/verilog/common ../../rtl/verilog/perf_opt}
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