| 1 |
2 |
entactogen |
##############################################################
|
| 2 |
|
|
#
|
| 3 |
|
|
# Xilinx Core Generator version 14.4
|
| 4 |
|
|
# Date: Wed Feb 20 10:22:51 2013
|
| 5 |
|
|
#
|
| 6 |
|
|
##############################################################
|
| 7 |
|
|
#
|
| 8 |
|
|
# This file contains the customisation parameters for a
|
| 9 |
|
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
| 10 |
|
|
# that you do not manually alter this file as it may cause
|
| 11 |
|
|
# unexpected and unsupported behavior.
|
| 12 |
|
|
#
|
| 13 |
|
|
##############################################################
|
| 14 |
|
|
#
|
| 15 |
|
|
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
|
| 16 |
|
|
#
|
| 17 |
|
|
##############################################################
|
| 18 |
|
|
#
|
| 19 |
|
|
# BEGIN Project Options
|
| 20 |
|
|
SET addpads = false
|
| 21 |
|
|
SET asysymbol = true
|
| 22 |
|
|
SET busformat = BusFormatAngleBracketNotRipped
|
| 23 |
|
|
SET createndf = false
|
| 24 |
|
|
SET designentry = VHDL
|
| 25 |
|
|
SET device = xc7a200t
|
| 26 |
|
|
SET devicefamily = artix7
|
| 27 |
|
|
SET flowvendor = Other
|
| 28 |
|
|
SET formalverification = false
|
| 29 |
|
|
SET foundationsym = false
|
| 30 |
|
|
SET implementationfiletype = Ngc
|
| 31 |
|
|
SET package = fbg484
|
| 32 |
|
|
SET removerpms = false
|
| 33 |
|
|
SET simulationfiles = Behavioral
|
| 34 |
|
|
SET speedgrade = -3
|
| 35 |
|
|
SET verilogsim = false
|
| 36 |
|
|
SET vhdlsim = true
|
| 37 |
|
|
# END Project Options
|
| 38 |
|
|
# BEGIN Select
|
| 39 |
|
|
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
|
| 40 |
|
|
# END Select
|
| 41 |
|
|
# BEGIN Parameters
|
| 42 |
|
|
CSET ce_overrides=ce_overrides_sync_controls
|
| 43 |
|
|
CSET coefficient_file=s_box_v_5.coe
|
| 44 |
|
|
CSET common_output_ce=false
|
| 45 |
|
|
CSET common_output_clk=false
|
| 46 |
|
|
CSET component_name=s_box_dram_5
|
| 47 |
|
|
CSET data_width=4
|
| 48 |
|
|
CSET default_data=0
|
| 49 |
|
|
CSET default_data_radix=16
|
| 50 |
|
|
CSET depth=64
|
| 51 |
|
|
CSET dual_port_address=non_registered
|
| 52 |
|
|
CSET dual_port_output_clock_enable=false
|
| 53 |
|
|
CSET input_clock_enable=false
|
| 54 |
|
|
CSET input_options=non_registered
|
| 55 |
|
|
CSET memory_type=rom
|
| 56 |
|
|
CSET output_options=non_registered
|
| 57 |
|
|
CSET pipeline_stages=0
|
| 58 |
|
|
CSET qualify_we_with_i_ce=false
|
| 59 |
|
|
CSET reset_qdpo=false
|
| 60 |
|
|
CSET reset_qsdpo=false
|
| 61 |
|
|
CSET reset_qspo=false
|
| 62 |
|
|
CSET simple_dual_port_address=non_registered
|
| 63 |
|
|
CSET simple_dual_port_output_clock_enable=false
|
| 64 |
|
|
CSET single_port_output_clock_enable=false
|
| 65 |
|
|
CSET sync_reset_qdpo=false
|
| 66 |
|
|
CSET sync_reset_qsdpo=false
|
| 67 |
|
|
CSET sync_reset_qspo=false
|
| 68 |
|
|
# END Parameters
|
| 69 |
|
|
# BEGIN Extra information
|
| 70 |
|
|
MISC pkg_timestamp=2012-11-21T20:07:40Z
|
| 71 |
|
|
# END Extra information
|
| 72 |
|
|
GENERATE
|
| 73 |
|
|
# CRC: 3bb20429
|
