Subversion Repositories diogenes

"/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 219: Unconnected output port 'nrts' of component 'sc_uart'.

"/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 237: Instantiating black box module <pmem>.

"/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 273: The following signals are missing in the process sensitivity list:

was_uart, was_button, button.

"/home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl" line 51: Instantiating black box module <video_ram>.

Register <curpc<31>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<30>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<29>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<28>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<27>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<26>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<25>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<24>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<23>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<22>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<21>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<20>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<19>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<18>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<17>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<16>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<15>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<14>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<13>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<12>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<11>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

Register <curpc<10>> in unit <fetch> has a constant value of 0 during circuit operation. The register is replaced by logic.

"/home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd" line 191: Mux is complete : default of case is discarded

"/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 64: Unconnected output port 'spo' of component 'dist_mem'.

"/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 64: Instantiating black box module <dist_mem>.

"/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 74: Unconnected output port 'spo' of component 'dist_mem'.

"/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 74: Instantiating black box module <dist_mem>.

"/home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd" line 96: Instantiating black box module <dmem>.

Property "use_dsp48" is not applicable for this technology.

Signal <pixel_buf<7:4>> is assigned but never used.

Signal <count> is never used or assigned.

Signal <pixel<3>> is assigned but never used.

Property "use_dsp48" is not applicable for this technology.

Signal <rp<0>> is assigned but never used.

Input <reset> is never used.

Property "use_dsp48" is not applicable for this technology.

Input <wr_data<31:8>> is never used.

Signal <tf_half> is assigned but never used.

Found 1-bit latch for signal <rd_data_0>.

Found 1-bit latch for signal <rd_data_1>.

Found 1-bit latch for signal <rd_data_2>.

Found 1-bit latch for signal <rd_data_3>.

Found 1-bit latch for signal <rd_data_4>.

Found 1-bit latch for signal <rd_data_5>.

Found 1-bit latch for signal <rd_data_6>.

Found 1-bit latch for signal <rd_data_7>.

Property "use_dsp48" is not applicable for this technology.

Property "use_dsp48" is not applicable for this technology.

Input <big_op<15>> is never used.

Signal <extaddr<13>> is assigned but never used.

Signal <urd_data<31:16>> is assigned but never used.

Found 16-bit latch for signal <extdin>.

HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

 FFs/Latches <big_op<15:15>> (without init value) have a constant value of 0 in block <decode>.

 FFs/Latches <brzero<2:2>> (without init value) have a constant value of 0 in block <decode>.

Node <pixel_buf_3> of sequential type is unconnected in block <vga>.

Node <pixel_buf_4> of sequential type is unconnected in block <vga>.

Node <pixel_buf_5> of sequential type is unconnected in block <vga>.

Node <pixel_buf_6> of sequential type is unconnected in block <vga>.

Node <pixel_buf_7> of sequential type is unconnected in block <vga>.

Node <pixel_3> of sequential type is unconnected in block <vga>.

FF/Latch  <big_op_9> (without init value) has a constant value of 0 in block <decode>.

Due to other FF/Latch trimming, FF/Latch  <big_op_10> (without init value) has a constant value of 0 in block <decode>.

FF/Latch  <0> (without init value) has a constant value of 0 in block <8>.

FF/Latch  <0> (without init value) has a constant value of 0 in block <9>.

FF/Latch  <0> (without init value) has a constant value of 0 in block <10>.

FF/Latch  <0> (without init value) has a constant value of 0 in block <11>.

FF/Latch  <0> (without init value) has a constant value of 0 in block <12>.

FF/Latch  <0> (without init value) has a constant value of 0 in block <13>.

FF/Latch  <0> (without init value) has a constant value of 0 in block <14>.

FF/Latch  <0> (without init value) has a constant value of 0 in block <15>.

Node <rd_prev> of sequential type is unconnected in block <g1[0].f1>.

Node <rd_prev> of sequential type is unconnected in block <g1[0].f1>.

Node <cmp_rf/g1[0].f1/rd_prev> of sequential type is unconnected in block <sc_uart>.

Node <cmp_tf/g1[0].f1/rd_prev> of sequential type is unconnected in block <sc_uart>.

FF/Latch  <extdin_8> (without init value) has a constant value of 0 in block <mysio>.

FF/Latch  <extdin_9> (without init value) has a constant value of 0 in block <mysio>.

FF/Latch  <extdin_10> (without init value) has a constant value of 0 in block <mysio>.

FF/Latch  <extdin_11> (without init value) has a constant value of 0 in block <mysio>.

FF/Latch  <extdin_12> (without init value) has a constant value of 0 in block <mysio>.

FF/Latch  <extdin_13> (without init value) has a constant value of 0 in block <mysio>.

FF/Latch  <extdin_14> (without init value) has a constant value of 0 in block <mysio>.

FF/Latch  <extdin_15> (without init value) has a constant value of 0 in block <mysio>.

HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.