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#

# Xilinx Core Generator version J.36

# Date: Wed Nov 21 14:17:31 2007

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

# BEGIN Project Options

SET addpads = False

SET asysymbol = False

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = False

SET designentry = VHDL

SET device = xc3s500e

SET devicefamily = spartan3e

SET flowvendor = Other

SET formalverification = False

SET foundationsym = False

SET implementationfiletype = Ngc

SET package = fg320

SET removerpms = False

SET simulationfiles = Behavioral

SET speedgrade = -5

SET verilogsim = False

SET vhdlsim = True

# END Project Options

# BEGIN Select

SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2

# END Select

# BEGIN Parameters

CSET active_clock_edge=Rising_Edge_Triggered

CSET additional_output_pipe_stages=0

CSET component_name=dmem

CSET depth=1024

CSET disable_warning_messages=true

CSET enable_pin=false

CSET enable_pin_polarity=Active_High

CSET global_init_value=0

CSET handshaking_pins=false

CSET has_limit_data_pitch=false

CSET init_pin=false

CSET init_value=0

CSET initialization_pin_polarity=Active_High

CSET limit_data_pitch=18

CSET load_init_file=false

CSET port_configuration=Read_And_Write

CSET primitive_selection=Optimize_For_Area

CSET register_inputs=false

CSET select_primitive=16kx1

CSET width=32

CSET write_enable_polarity=Active_High

CSET write_mode=Read_After_Write

# END Parameters

GENERATE

# CRC: 7fa4fc1e