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[/] [diogenes/] [tags/] [initial/] [vhdl/] [mysio_isim_beh.wfs] - Blame information for rev 237

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1 154 fellnhofer 
version 3
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CLOCK_LIST_BEGIN
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CLOCK_LIST_END
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SIGNAL_LIST_BEGIN
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SIGNAL_LIST_END
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SIGNALS_NOT_ON_DISPLAY
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SIGNALS_NOT_ON_DISPLAY_END
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MARKER_LIST_BEGIN
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MARKER_LIST_END
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MEASURE_LIST_BEGIN
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MEASURE_LIST_END
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SIGNAL_ORDER_BEGIN
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/mysio/gclk
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/mysio/reset
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/mysio/simulation
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/mysio/rx
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/mysio/tx
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/mysio/test
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/mysio/nreset
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/mysio/wr_gen
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/mysio/rd_gen
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/mysio/rd_data
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/mysio/wr_data
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/mysio/addr
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/mysio/mem_addr
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/mysio/mem_dout
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/mysio/mem_hi
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/mysio/pmem_addr
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/mysio/pmem_din
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/mysio/pmem_dout
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/mysio/pmem_we
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/mysio/pmem_clk
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/mysio/testout
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/mysio/clk_cpu
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/mysio/count
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/mysio/extaddr
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/mysio/extdin
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/mysio/extdout
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/mysio/mem_addr_cpu
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/mysio/mem_dout_cpu
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/mysio/reset_cpu
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/mysio/cpu_running
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/mysio/state
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/mysio/mode
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SIGNAL_ORDER_END
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DIFFERENTIAL_CLKS_BEGIN
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DIVIDERS_BEGIN
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DIVIDERS_END
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SIGPROPS_BEGIN
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/mysio/gclk
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/mysio/clk_cpu
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/mysio/count
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/mysio/extaddr
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/mysio/extdin
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/mysio/extdout
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/mysio/extwr
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/mysio/extrd
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/mysio/mem_addr_cpu
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/mysio/state
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/mysio/mode
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SIGPROPS_END

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