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Release 9.2i par J.36

Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

thoreau::  Tue Nov 13 12:05:47 2007

par -w -intstyle ise -ol std -t 1 sio_map.ncd sio.ncd sio.pcf

Constraints file: sio.pcf.

Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/Xilinx92.

   "sio" is an NCD, version 3.1, device xc3s500e, package fg320, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

Device speed data version:  "PRODUCTION 1.26 2007-04-13".

Design Summary Report:

 Number of External IOBs                          12 out of 232     5%

   Number of External Input IOBs                  3

      Number of External Input IBUFs              3

        Number of LOCed External Input IBUFs      3 out of 3     100%

   Number of External Output IOBs                 9

      Number of External Output IOBs              9

        Number of LOCed External Output IOBs      9 out of 9     100%

   Number of External Bidir IOBs                  0

   Number of BUFGMUXs                        1 out of 24      4%

   Number of RAMB16s                         1 out of 20      5%

   Number of Slices                        140 out of 4656    3%

      Number of SLICEMs                      1 out of 2328    1%

Overall effort level (-ol):   Standard

Placer effort level (-pl):    High

Placer cost table entry (-t): 1

Router effort level (-rl):    Standard

Starting initial Timing Analysis.  REAL time: 2 secs

Finished initial Timing Analysis.  REAL time: 2 secs

Starting Placer

Phase 1.1

Phase 1.1 (Checksum:989b23) REAL time: 3 secs

Phase 2.7

Phase 2.7 (Checksum:1312cfe) REAL time: 3 secs

Phase 3.31

Phase 3.31 (Checksum:1c9c37d) REAL time: 3 secs

Phase 4.2

......

Phase 4.2 (Checksum:989e4f) REAL time: 3 secs

Phase 5.30

Phase 5.30 (Checksum:2faf07b) REAL time: 3 secs

Phase 6.8

.......................

....

.......................

....

....

..............

Phase 6.8 (Checksum:9d4a03) REAL time: 7 secs

Phase 7.5

Phase 7.5 (Checksum:42c1d79) REAL time: 7 secs

Phase 8.18

Phase 8.18 (Checksum:4c4b3f8) REAL time: 8 secs

Phase 9.5

Phase 9.5 (Checksum:55d4a77) REAL time: 8 secs

REAL time consumed by placer: 8 secs

CPU  time consumed by placer: 8 secs

Writing design to file sio.ncd

Total REAL time to Placer completion: 8 secs

Total CPU time to Placer completion: 8 secs

Starting Router

Phase 1: 955 unrouted;       REAL time: 11 secs

Phase 2: 842 unrouted;       REAL time: 12 secs

Phase 3: 130 unrouted;       REAL time: 12 secs

Phase 4: 130 unrouted; (0)      REAL time: 12 secs

Phase 5: 130 unrouted; (0)      REAL time: 12 secs

Phase 6: 130 unrouted; (0)      REAL time: 12 secs

Phase 7: 0 unrouted; (0)      REAL time: 12 secs

Phase 8: 0 unrouted; (0)      REAL time: 12 secs

Total REAL time to Router completion: 12 secs

Total CPU time to Router completion: 12 secs

Partition Implementation Status

-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************

Generating Clock Report

**************************

+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|           clk_BUFGP | BUFGMUX_X1Y11| No   |  103 |  0.062     |  0.164      |

+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.

   The Delay Summary Report

The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.854

   The MAXIMUM PIN DELAY IS:                               4.670

   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.523

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00

   ---------   ---------   ---------   ---------   ---------   ---------

         638         257          38           6           2           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------

  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing

                                            |         |    Slack   | Achievable | Errors |    Score

------------------------------------------------------------------------------------------------------

  NET "clk_BUFGP/IBUFG" PERIOD = 25 ns HIGH | SETUP   |    18.382ns|     6.618ns|       0|           0

   50%                                      | HOLD    |     0.803ns|            |       0|           0

------------------------------------------------------------------------------------------------------

All constraints were met.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 13 secs

Total CPU time to PAR completion: 13 secs

Peak Memory Usage:  130 MB

Placement: Completed - No errors found.

Routing: Completed - No errors found.

Timing: Completed - No errors found.

Number of error messages: 0

Number of warning messages: 0

Number of info messages: 0

Writing design to file sio.ncd

PAR done!