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[/] [diogenes/] [tags/] [initial/] [vhdl/] [sio.twr] - Blame information for rev 237

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Line No. Rev Author Line
1 154 fellnhofer
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Release 9.2i Trace
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Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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trce -ise /home/andi/xilinx/rs232/rs232.ise -intstyle ise -e 3 -s 5 -xml sio
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sio.ncd -o sio.twr sio.pcf -ucf sio.ucf
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Design file:              sio.ncd
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Physical constraint file: sio.pcf
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Device,package,speed:     xc3s500e,fg320,-5 (PRODUCTION 1.26 2007-04-13)
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Report level:             error report
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Environment Variable      Effect
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--------------------      ------
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NONE                      No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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   option. All paths that are not constrained will be reported in the
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   unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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   a 50 Ohm transmission line loading model.  For the details of this model,
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   and for more information on accounting for different loading conditions,
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   please see the device datasheet.
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================================================================================
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Timing constraint: NET "clk_BUFGP/IBUFG" PERIOD = 25 ns HIGH 50%;
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 3094 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
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 Minimum period is   6.618ns.
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--------------------------------------------------------------------------------
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All constraints were met.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Clock to Setup on destination clock clk
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---------------+---------+---------+---------+---------+
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               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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clk            |    6.618|         |         |         |
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---------------+---------+---------+---------+---------+
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Timing summary:
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---------------
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Timing errors: 0  Score: 0
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Constraints cover 3094 paths, 0 nets, and 842 connections
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Design statistics:
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   Minimum period:   6.618ns   (Maximum frequency: 151.103MHz)
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Analysis completed Tue Nov 13 12:06:05 2007
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 92 MB
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