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[/] [diogenes/] [tags/] [initial/] [vhdl/] [types.vhd] - Blame information for rev 236

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Line No. Rev Author Line
1 154 fellnhofer
--      Package File Template
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--
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--      Purpose: This package defines supplemental types, subtypes, 
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--               constants, and functions 
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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package types is
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        subtype slv_36 is std_logic_VECTOR(35 downto 0);
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        subtype slv_32 is std_logic_VECTOR(31 downto 0);
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        subtype slv_16 is std_logic_VECTOR(15 downto 0);
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        subtype slv_8 is std_logic_VECTOR(7 downto 0);
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        subtype slv_4 is std_logic_VECTOR(3 downto 0);
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        type slv_32_array is array (integer range <>) of slv_32;
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-- Declare constants
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--      constant op_add : bit_8 := X"00";
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--      constant op_sub : bit_8 := X"01";
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-- Declare functions and procedure
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        function bits_to_natural (lv : in std_logic_vector) return natural;
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end types;
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package body types is
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        function bits_to_natural (lv : in std_logic_vector) return natural is
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                variable result : natural := 0;
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                variable bits : bit_vector(lv'range);
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                begin
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                        bits := To_bitvector(lv);
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                        for index in bits'range loop
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                                        result := result * 2 + bit'pos(bits(index));
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                        end loop;
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                        return result;
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                end bits_to_natural;
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end types;

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