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[/] [diogenes/] [tags/] [initial/] [vhdl/] [vga/] [vga.vhdl] - Blame information for rev 236

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Line No. Rev Author Line
1 164 fellnhofer 
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity vga is
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  port(reset      : in std_logic;
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                 clk50_in  : in std_logic;
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       red_out   : out std_logic;
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       green_out : out std_logic;
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       blue_out  : out std_logic;
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       hs_out    : out std_logic;
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       vs_out    : out std_logic;
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                 addrb: IN std_logic_VECTOR(12 downto 0);
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                 dinb: IN std_logic_VECTOR(7 downto 0);
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                 web: IN std_logic
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                 );
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end vga;
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architecture Behavioral of vga is
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component video_ram is
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        port (
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        addra: IN std_logic_VECTOR(12 downto 0);
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        addrb: IN std_logic_VECTOR(12 downto 0);
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        clka: IN std_logic;
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        clkb: IN std_logic;
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        dinb: IN std_logic_VECTOR(7 downto 0);
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        douta: OUT std_logic_VECTOR(7 downto 0);
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        web: IN std_logic
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        );
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end component;
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signal clk25              : std_logic;
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signal horizontal_counter : std_logic_vector (9 downto 0);
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signal vertical_counter   : std_logic_vector (9 downto 0);
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signal count : std_logic_vector (9 downto 0);
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signal v_addr : std_logic_VECTOR(12 downto 0);
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signal v_data : std_logic_VECTOR(7 downto 0);
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signal pixel : std_logic_vector(3 downto 0);
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signal pixel_buf : std_logic_vector(7 downto 0);
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begin
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video_ram_c: video_ram
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  port map(
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                addra => v_addr,
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                addrb => addrb,
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                clka => clk50_in,
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                clkb => clk50_in,
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                dinb => dinb,
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                douta => v_data,
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                web => web
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        );
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-- generate a 25Mhz clock
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process (clk50_in, reset)
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        variable temp: std_logic_vector(9 downto 0) := (others => '0');
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begin
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        if reset='0' then
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                clk25 <= '1';
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--              horizontal_counter <= (others => '0'); --"1101110000";
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--              vertical_counter <= (others => '0'); --"1111011001";
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                hs_out <= '1';
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                vs_out <= '1';
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                blue_out <= '0';
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                red_out <= '0';
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                green_out <= '0';
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--              pixel_buf <= (others => '0');
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--              pixel <= (others => '0');
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                v_addr <= (others => '0');
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        elsif rising_edge(clk50_in) then
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    if (clk25 = '0') then ----------- 25mhz rising edge
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                clk25 <= '1';
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                if (horizontal_counter < "1010000000" ) -- 640
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                and (vertical_counter < "0111100000" )  -- 480
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                and (horizontal_counter >= "0000000000" )
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                and (vertical_counter >= "0000000000" ) then
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                        red_out <= pixel(0);
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                        green_out <= pixel(1);
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                        blue_out <= pixel(2);
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                else
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                        red_out <= '0';
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                        green_out <= '0';
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                        blue_out <= '0';
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                end if;
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                if (horizontal_counter >    "1101110000" )
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                and (horizontal_counter < "1111010001" ) then -- 96+1
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                        hs_out <= '0';
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                else
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                        hs_out <= '1';
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                end if;
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                if (vertical_counter >    "1111011001" )
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                and (vertical_counter < "1111011100" ) then -- 2+1
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                        vs_out <= '0';
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                else
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                        vs_out <= '1';
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                end if;
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                horizontal_counter <= horizontal_counter+"0000000001";
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                if (horizontal_counter="1010010000") then              -- 800 - 144
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                        vertical_counter <= vertical_counter+"0000000001";
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                        horizontal_counter <= "1101110000";
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                end if;
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                if (vertical_counter="0111101110") then                    -- 521 - 39
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                        vertical_counter <= "1111011001";
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                end if;
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    else                 ----------- 25mhz falling edge
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                clk25 <= '0';
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           -- tile index:   0yyy xxxx
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           -- tile address: yyyVVV 1xxxxHH
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                if horizontal_counter(0) = '0' then
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                        temp := horizontal_counter(9 downto 0) + "0000000010";
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                        v_addr <= vertical_counter(8 downto 3) & temp(9 downto 3);
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                        pixel_buf <= v_data;
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                        pixel <= v_data(7 downto 4);
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                elsif horizontal_counter(0) = '1' then
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                        temp := horizontal_counter(9 downto 0) + "0000000001";
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                        v_addr <= v_data(6 downto 4) & vertical_counter(2 downto 0) & "1" & v_data(3 downto 0) & temp(2 downto 1);
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                        pixel <= pixel_buf(3 downto 0);
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                end if;
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         end if;
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  end if;
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end process;
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-- 144 horizontal blank interval + 16 before incrementing vsync
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-- 39 vertical blank interval + 2 before reseting
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end Behavioral;

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