OpenCores
URL https://opencores.org/ocsvn/diogenes/diogenes/trunk

Subversion Repositories diogenes

[/] [diogenes/] [trunk/] [old/] [bootloader_rc2.asm] - Blame information for rev 236

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 124 fellnhofer
@ l0 : temp
2
@ l1 : constant 1
3
@ l2 : current address for memwrites
4
@ l3 : temp, holds the value received from uart
5
@ h1 : toggle bit = 0 zero, when a full 16 Bit word was received
6
@ h2 : holds the bitmask of the invalid instruction 0xffff = special with
7
@ l4 : temp, used for branch condition
8
 
9
80:
10
  ldi   l2, 0x80
11
  lsi   l2, 0x40     @ start of user program
12
 
13
  ldi   h2, 0xff
14
  lsi   h2, 0xff     @ h2 = 0xffff
15
 
16
  ldi   l1, 1        @ constant 1
17
  ldi   h1, 0        @ toggle bit (hi low)
18
  stio  h2, [h1]     @ leds echo
19
 
20
 
21
1: @ wait for byte
22
  ldi   l0, 0x80     @ uart status address
23
  ldio  l3, [l0]
24
  ldi   h0, 2        @ uart data ready bit
25
  and   l4, l3, h0
26
  brz   l4, :1
27
  ldi   h0, 0x81     @ uart data address
28
 
29
 
30
  ldio  l3, [h0]     @ uart rcv
31
  xor   h1, h1, l1   @ toggle state (16 bit Ready)
32
  stio  l3, [h0]     @ uart echo (uart should be ready at this point)
33
  ldi   h0, 0x00         @ leds address
34
  stio  l3, [h0]     @ leds echo
35
  brz   h1, :2
36
  nop                @ hier könnte leds echo sein (nop wegen evtl.  Simulator bug)
37
 
38
 
39
  @ olny first half (LSB) of instruction was received
40
  brnz  h1, :1
41
  mov   h3, l3       @ h3: holds 16-bit instr (here LSB are set)
42
 
43
 
44
2: @ full 16-Bit instruction is ready
45
  shi   l3, 8        @ move received 8 bits
46
  or    h3, h3, l3   @ merge the two instructionbytes
47
  stio  h3, [l2]     @ write instruction to programm-mem
48
  xor   l4, h3, h2   @ check if the instruction writen to pmem is 0xffff
49
  brnz  l4, :1
50
  adi   l2, 1        @ increase program-write address
51
 
52
@@ programm loaded
53
 
54
@ jump to begin of loaded program
55
  ldi   l0, 0x40
56
  jump  
57
  nop
58
 
59
 
60
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.