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https://opencores.org/ocsvn/diogenes/diogenes/trunk
[/] [diogenes/] [trunk/] [vhdl/] [_xmsgs/] [map.xmsgs] - Blame information for rev 236
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fellnhofer |
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Logical network diogenes_cpu/pipestage2/rf/reg1/N1 has no load.
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The above warning message base_net_load_rule is repeated 136 more times for the following (max. 5 shown):
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diogenes_cpu/pipestage2/rf/reg1/N0,
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diogenes_cpu/pipestage2/rf/reg1/BU2/qdpo<0>,
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diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/qspo_int<31>,
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diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/qspo_int<30>,
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diogenes_cpu/pipestage2/rf/reg1/BU2/U0/gen_dp_ram.dpram_inst/qspo_int<29>
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To see the details of these warning messages, please use the -detail switch.
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No environment variables are currently set.
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The following Virtex BUFG(s) is/are being retargeted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
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BUFGP symbol "gclk_BUFGP" (output signal=gclk_BUFGP)
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| 27 |
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Net Timing constraints on signal gclk are pushed forward through input buffer.
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| 30 |
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Dangling pin <DOA14> on block:<diogenes_cpu/pipestage3/cdmem/B10/diogenes_cpu/pipestage3/cdmem/B10.A>:<RAMB16_RAMB16A>.
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Dangling pin <DOA15> on block:<diogenes_cpu/pipestage3/cdmem/B10/diogenes_cpu/pipestage3/cdmem/B10.A>:<RAMB16_RAMB16A>.
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