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[/] [diogenes/] [trunk/] [vhdl/] [cpu/] [coregen.cgp] - Blame information for rev 236

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Line No. Rev Author Line
1 154 fellnhofer
# Date: Mon Jan 14 13:39:07 2008
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SET addpads = False
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SET asysymbol = False
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc3s500e
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SET devicefamily = spartan3e
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SET flowvendor = Other
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = fg320
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -5
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SET verilogsim = False
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SET vhdlsim = True
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SET workingdirectory = /tmp
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