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[/] [diogenes/] [trunk/] [vhdl/] [cpu/] [coregen.log] - Blame information for rev 154
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Rev |
Author |
Line |
| 1 |
154 |
fellnhofer |
Welcome to Xilinx CORE Generator.
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Opened project file /home/andi/xilinx/rs232/cpu/coregen.cgp.
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Created directory /home/andi/xilinx/rs232/vga/coregen.
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Closed project file.
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Wrote project file /home/andi/xilinx/rs232/vga/coregen/coregen.cgp.
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Customizing IP...
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Finished Customizing.
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Generating IP...
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ERROR:coreutil - Failure to set parameters on core: Some initial values do not
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match either the Memory Initialization Radix or Data Width. Press the Show
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| 11 |
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Values button to view them.
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ERROR:coreutil - Failure to generate output products
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ERROR:coreutil - An error occurred while running Java. Please examine the
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console or coregen log file for a specific IP related error.
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If there is no specific error the problem may be due to memory limitations.
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For more information please consult solution record 21955 available from:
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http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Generating.
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ERROR:sim:57 - Error found during generation
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Customizing IP...
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Cancelled Customization.
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Customizing IP...
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ERROR:coreutil - Must enter a component name.
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Finished Customizing.
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Generating IP...
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Generating Implementation files.
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Generating the VHDL wrapper.
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Generating the VHDL instantiation template.
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Generating NGC file.
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| 29 |
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Finished Generating.
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| 30 |
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Successfully generated video_ram.
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| 31 |
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Closed project file.
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