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fellnhofer |
Release 9.2i - xst J.36
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Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.05 s | Elapsed : 0.00 / 0.00 s
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-->
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Parameter xsthdpdir set to ./xst
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CPU : 0.00 / 0.05 s | Elapsed : 0.00 / 0.00 s
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-->
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Reading design: mysio.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "mysio.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "mysio"
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Output Format : NGC
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Target Device : xc3s500e-4-fg320
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---- Source Options
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Top Module Name : mysio
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 24
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Library Search Order : mysio.lso
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/types.vhd" in Library work.
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Architecture types of Entity types is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/barrel.vhd" in Library work.
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Architecture behavioral of Entity barrel is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.vhd" in Library work.
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Architecture dist_mem_a of Entity dist_mem is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/dmem.vhd" in Library work.
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Architecture dmem_a of Entity dmem is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/alu.vhd" in Library work.
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Architecture behavioral of Entity alu is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" in Library work.
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Architecture behavioral of Entity regfile is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/fetch.vhd" in Library work.
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Architecture behavioral of Entity fetch is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd" in Library work.
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Architecture behavioral of Entity decode is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd" in Library work.
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Architecture behavioral of Entity execute is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/fifo.vhd" in Library work.
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Architecture rtl of Entity fifo_elem is up to date.
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Architecture rtl of Entity fifo is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/video_ram.vhd" in Library work.
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Architecture video_ram_a of Entity video_ram is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl" in Library work.
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Architecture behavioral of Entity vga is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/sc_uart.vhd" in Library work.
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Architecture rtl of Entity sc_uart is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/pmem.vhd" in Library work.
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Architecture pmem_a of Entity pmem is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/cpu/cpu.vhd" in Library work.
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Architecture behavioral of Entity cpu is up to date.
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Compiling vhdl file "/home/andi/xilinx/diogenes/vhdl/sio.vhd" in Library work.
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Architecture behavioral of Entity mysio is up to date.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ) with generics.
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addr_bits = 1
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baud_rate = 115000
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clk_freq = 50000000
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rxf_depth = 1
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rxf_thres = 1
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txf_depth = 1
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txf_thres = 1
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ) with generics.
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depth = 1
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thres = 1
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width = 8
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ) with generics.
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width = 8
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity in library (Architecture ).
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WARNING:Xst:753 - "/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 219: Unconnected output port 'nrts' of component 'sc_uart'.
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WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 237: Instantiating black box module .
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WARNING:Xst:819 - "/home/andi/xilinx/diogenes/vhdl/sio.vhd" line 273: The following signals are missing in the process sensitivity list:
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was_uart, was_button, button.
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl" line 51: Instantiating black box module .
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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addr_bits = 1
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baud_rate = 115000
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clk_freq = 50000000
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rxf_depth = 1
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rxf_thres = 1
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txf_depth = 1
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txf_thres = 1
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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depth = 1
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thres = 1
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width = 8
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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width = 8
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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INFO:Xst:1561 - "/home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd" line 191: Mux is complete : default of case is discarded
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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WARNING:Xst:753 - "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 64: Unconnected output port 'spo' of component 'dist_mem'.
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WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 64: Instantiating black box module .
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WARNING:Xst:753 - "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 74: Unconnected output port 'spo' of component 'dist_mem'.
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WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd" line 74: Instantiating black box module .
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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WARNING:Xst:2211 - "/home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd" line 96: Instantiating black box module .
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "/home/andi/xilinx/diogenes/vhdl/fifo.vhd".
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Summary:
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inferred 10 D-type flip-flop(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/fetch.vhd".
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WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
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Found 32-bit register for signal .
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Found 32-bit 4-to-1 multiplexer for signal .
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Found 10-bit register for signal >.
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Found 10-bit adder for signal created at line 85.
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Found 1-bit register for signal .
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Summary:
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inferred 43 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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inferred 32 Multiplexer(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/barrel.vhd".
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Found 32-bit shifter logical left for signal .
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Found 32-bit 4-to-1 multiplexer for signal .
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Found 32-bit shifter logical right for signal .
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Found 32-bit 4-to-1 multiplexer for signal .
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Summary:
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inferred 64 Multiplexer(s).
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inferred 2 Combinational logic shifter(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "/home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl".
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WARNING:Xst:646 - Signal > is assigned but never used.
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WARNING:Xst:1780 - Signal is never used or assigned.
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WARNING:Xst:646 - Signal > is assigned but never used.
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WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
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Found 1-bit register for signal .
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|
|
Found 1-bit register for signal .
|
| 312 |
|
|
Found 1-bit register for signal .
|
| 313 |
|
|
Found 1-bit register for signal .
|
| 314 |
|
|
Found 1-bit register for signal .
|
| 315 |
|
|
Found 1-bit register for signal .
|
| 316 |
|
|
Found 10-bit up counter for signal .
|
| 317 |
|
|
Found 10-bit comparator greater for signal created at line 98.
|
| 318 |
|
|
Found 10-bit comparator less for signal created at line 98.
|
| 319 |
|
|
Found 4-bit register for signal .
|
| 320 |
|
|
Found 8-bit register for signal .
|
| 321 |
|
|
Found 10-bit comparator less for signal created at line 86.
|
| 322 |
|
|
Found 10-bit comparator less for signal created at line 86.
|
| 323 |
|
|
Found 10-bit adder for signal created at line 127.
|
| 324 |
|
|
Found 10-bit adder for signal created at line 132.
|
| 325 |
|
|
Found 13-bit register for signal .
|
| 326 |
|
|
Found 10-bit up counter for signal .
|
| 327 |
|
|
Found 10-bit comparator greater for signal created at line 104.
|
| 328 |
|
|
Found 10-bit comparator less for signal created at line 104.
|
| 329 |
|
|
Summary:
|
| 330 |
|
|
inferred 2 Counter(s).
|
| 331 |
|
|
inferred 31 D-type flip-flop(s).
|
| 332 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 333 |
|
|
inferred 6 Comparator(s).
|
| 334 |
|
|
Unit synthesized.
|
| 335 |
|
|
|
| 336 |
|
|
|
| 337 |
|
|
Synthesizing Unit .
|
| 338 |
|
|
Related source file is "/home/andi/xilinx/diogenes/vhdl/fifo.vhd".
|
| 339 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 340 |
|
|
Unit synthesized.
|
| 341 |
|
|
|
| 342 |
|
|
|
| 343 |
|
|
Synthesizing Unit .
|
| 344 |
|
|
Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd".
|
| 345 |
|
|
WARNING:Xst:647 - Input is never used.
|
| 346 |
|
|
Found 5-bit comparator equal for signal created at line 95.
|
| 347 |
|
|
Found 5-bit comparator equal for signal created at line 96.
|
| 348 |
|
|
Summary:
|
| 349 |
|
|
inferred 2 Comparator(s).
|
| 350 |
|
|
Unit synthesized.
|
| 351 |
|
|
|
| 352 |
|
|
|
| 353 |
|
|
Synthesizing Unit .
|
| 354 |
|
|
Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/alu.vhd".
|
| 355 |
|
|
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
|
| 356 |
|
|
Found 32-bit register for signal .
|
| 357 |
|
|
Found 32-bit addsub for signal .
|
| 358 |
|
|
Found 32-bit comparator less for signal created at line 102.
|
| 359 |
|
|
Found 32-bit comparator less for signal created at line 108.
|
| 360 |
|
|
Found 32-bit xor2 for signal created at line 98.
|
| 361 |
|
|
Summary:
|
| 362 |
|
|
inferred 32 D-type flip-flop(s).
|
| 363 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 364 |
|
|
inferred 2 Comparator(s).
|
| 365 |
|
|
Unit synthesized.
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
Synthesizing Unit .
|
| 369 |
|
|
Related source file is "/home/andi/xilinx/diogenes/vhdl/sc_uart.vhd".
|
| 370 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 371 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 372 |
|
|
Found finite state machine for signal .
|
| 373 |
|
|
-----------------------------------------------------------------------
|
| 374 |
|
|
| States | 3 |
|
| 375 |
|
|
| Transitions | 6 |
|
| 376 |
|
|
| Inputs | 3 |
|
| 377 |
|
|
| Outputs | 4 |
|
| 378 |
|
|
| Clock | clk (rising_edge) |
|
| 379 |
|
|
| Reset | reset (positive) |
|
| 380 |
|
|
| Reset type | asynchronous |
|
| 381 |
|
|
| Reset State | s0 |
|
| 382 |
|
|
| Power Up State | s0 |
|
| 383 |
|
|
| Encoding | automatic |
|
| 384 |
|
|
| Implementation | LUT |
|
| 385 |
|
|
-----------------------------------------------------------------------
|
| 386 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal .
|
| 387 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal .
|
| 388 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal .
|
| 389 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal .
|
| 390 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal .
|
| 391 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal .
|
| 392 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal .
|
| 393 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal .
|
| 394 |
|
|
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
|
| 395 |
|
|
Found 8x1-bit ROM for signal .
|
| 396 |
|
|
Found 32-bit up counter for signal .
|
| 397 |
|
|
Found 4-bit up counter for signal .
|
| 398 |
|
|
Found 4-bit up counter for signal .
|
| 399 |
|
|
Found 4-bit up counter for signal .
|
| 400 |
|
|
Found 4-bit register for signal .
|
| 401 |
|
|
Found 3-bit register for signal .
|
| 402 |
|
|
Found 1-bit register for signal .
|
| 403 |
|
|
Found 10-bit register for signal .
|
| 404 |
|
|
Found 3-bit register for signal .
|
| 405 |
|
|
Found 1-bit register for signal .
|
| 406 |
|
|
Found 4-bit adder for signal created at line 206.
|
| 407 |
|
|
Found 1-bit register for signal .
|
| 408 |
|
|
Found 3-bit register for signal .
|
| 409 |
|
|
Found 1-bit register for signal .
|
| 410 |
|
|
Found 10-bit register for signal .
|
| 411 |
|
|
Found 1-bit register for signal .
|
| 412 |
|
|
Found 4-bit adder for signal created at line 196.
|
| 413 |
|
|
Found 4-bit adder for signal created at line 344.
|
| 414 |
|
|
Found 1-bit register for signal >.
|
| 415 |
|
|
Found 4-bit adder for signal created at line 272.
|
| 416 |
|
|
Summary:
|
| 417 |
|
|
inferred 1 Finite State Machine(s).
|
| 418 |
|
|
inferred 1 ROM(s).
|
| 419 |
|
|
inferred 4 Counter(s).
|
| 420 |
|
|
inferred 39 D-type flip-flop(s).
|
| 421 |
|
|
inferred 4 Adder/Subtractor(s).
|
| 422 |
|
|
Unit synthesized.
|
| 423 |
|
|
|
| 424 |
|
|
|
| 425 |
|
|
Synthesizing Unit .
|
| 426 |
|
|
Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd".
|
| 427 |
|
|
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
|
| 428 |
|
|
Found 1-bit register for signal .
|
| 429 |
|
|
Found 1-bit register for signal .
|
| 430 |
|
|
Found 1-bit register for signal .
|
| 431 |
|
|
Found 16-bit register for signal .
|
| 432 |
|
|
Found 1-bit register for signal .
|
| 433 |
|
|
Found 3-bit register for signal .
|
| 434 |
|
|
Found 32-bit register for signal .
|
| 435 |
|
|
Found 4-bit comparator equal for signal created at line 165.
|
| 436 |
|
|
Found 4-bit comparator equal for signal created at line 168.
|
| 437 |
|
|
Found 4-bit comparator equal for signal created at line 247.
|
| 438 |
|
|
Found 4-bit comparator equal for signal created at line 209.
|
| 439 |
|
|
Found 4-bit register for signal .
|
| 440 |
|
|
Found 32-bit adder for signal created at line 236.
|
| 441 |
|
|
Found 1-bit xor2 for signal created at line 126.
|
| 442 |
|
|
Found 32-bit register for signal .
|
| 443 |
|
|
Found 32-bit register for signal .
|
| 444 |
|
|
Summary:
|
| 445 |
|
|
inferred 123 D-type flip-flop(s).
|
| 446 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 447 |
|
|
inferred 4 Comparator(s).
|
| 448 |
|
|
Unit synthesized.
|
| 449 |
|
|
|
| 450 |
|
|
|
| 451 |
|
|
Synthesizing Unit .
|
| 452 |
|
|
Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd".
|
| 453 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 454 |
|
|
Found 4-bit register for signal .
|
| 455 |
|
|
Found 32-bit 4-to-1 multiplexer for signal .
|
| 456 |
|
|
Found 1-bit register for signal .
|
| 457 |
|
|
Found 1-bit register for signal .
|
| 458 |
|
|
Summary:
|
| 459 |
|
|
inferred 6 D-type flip-flop(s).
|
| 460 |
|
|
inferred 32 Multiplexer(s).
|
| 461 |
|
|
Unit synthesized.
|
| 462 |
|
|
|
| 463 |
|
|
|
| 464 |
|
|
Synthesizing Unit .
|
| 465 |
|
|
Related source file is "/home/andi/xilinx/diogenes/vhdl/cpu/cpu.vhd".
|
| 466 |
|
|
Unit synthesized.
|
| 467 |
|
|
|
| 468 |
|
|
|
| 469 |
|
|
Synthesizing Unit .
|
| 470 |
|
|
Related source file is "/home/andi/xilinx/diogenes/vhdl/sio.vhd".
|
| 471 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 472 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 473 |
|
|
WARNING:Xst:737 - Found 16-bit latch for signal .
|
| 474 |
|
|
Found 4-bit register for signal .
|
| 475 |
|
|
Found 1-bit register for signal .
|
| 476 |
|
|
Found 1-bit register for signal .
|
| 477 |
|
|
Found 1-bit register for signal .
|
| 478 |
|
|
Found 10-bit register for signal .
|
| 479 |
|
|
Found 16-bit register for signal .
|
| 480 |
|
|
Found 1-bit register for signal .
|
| 481 |
|
|
Found 8-bit register for signal .
|
| 482 |
|
|
Found 13-bit register for signal .
|
| 483 |
|
|
Found 8-bit register for signal .
|
| 484 |
|
|
Found 1-bit register for signal .
|
| 485 |
|
|
Found 1-bit register for signal .
|
| 486 |
|
|
Found 1-bit register for signal .
|
| 487 |
|
|
Summary:
|
| 488 |
|
|
inferred 66 D-type flip-flop(s).
|
| 489 |
|
|
Unit synthesized.
|
| 490 |
|
|
|
| 491 |
|
|
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
|
| 492 |
|
|
|
| 493 |
|
|
=========================================================================
|
| 494 |
|
|
HDL Synthesis Report
|
| 495 |
|
|
|
| 496 |
|
|
Macro Statistics
|
| 497 |
|
|
# ROMs : 1
|
| 498 |
|
|
8x1-bit ROM : 1
|
| 499 |
|
|
# Adders/Subtractors : 9
|
| 500 |
|
|
10-bit adder : 3
|
| 501 |
|
|
32-bit adder : 1
|
| 502 |
|
|
32-bit addsub : 1
|
| 503 |
|
|
4-bit adder : 4
|
| 504 |
|
|
# Counters : 6
|
| 505 |
|
|
10-bit up counter : 2
|
| 506 |
|
|
32-bit up counter : 1
|
| 507 |
|
|
4-bit up counter : 3
|
| 508 |
|
|
# Registers : 152
|
| 509 |
|
|
1-bit register : 133
|
| 510 |
|
|
10-bit register : 1
|
| 511 |
|
|
13-bit register : 2
|
| 512 |
|
|
16-bit register : 2
|
| 513 |
|
|
3-bit register : 1
|
| 514 |
|
|
32-bit register : 3
|
| 515 |
|
|
4-bit register : 5
|
| 516 |
|
|
8-bit register : 5
|
| 517 |
|
|
# Latches : 9
|
| 518 |
|
|
1-bit latch : 8
|
| 519 |
|
|
16-bit latch : 1
|
| 520 |
|
|
# Comparators : 14
|
| 521 |
|
|
10-bit comparator greater : 2
|
| 522 |
|
|
10-bit comparator less : 4
|
| 523 |
|
|
32-bit comparator less : 2
|
| 524 |
|
|
4-bit comparator equal : 4
|
| 525 |
|
|
5-bit comparator equal : 2
|
| 526 |
|
|
# Multiplexers : 4
|
| 527 |
|
|
32-bit 4-to-1 multiplexer : 4
|
| 528 |
|
|
# Logic shifters : 2
|
| 529 |
|
|
32-bit shifter logical left : 1
|
| 530 |
|
|
32-bit shifter logical right : 1
|
| 531 |
|
|
# Xors : 2
|
| 532 |
|
|
1-bit xor2 : 1
|
| 533 |
|
|
32-bit xor2 : 1
|
| 534 |
|
|
|
| 535 |
|
|
=========================================================================
|
| 536 |
|
|
|
| 537 |
|
|
=========================================================================
|
| 538 |
|
|
* Advanced HDL Synthesis *
|
| 539 |
|
|
=========================================================================
|
| 540 |
|
|
|
| 541 |
|
|
Analyzing FSM for best encoding.
|
| 542 |
|
|
Optimizing FSM on signal with sequential encoding.
|
| 543 |
|
|
-------------------
|
| 544 |
|
|
State | Encoding
|
| 545 |
|
|
-------------------
|
| 546 |
|
|
s0 | 00
|
| 547 |
|
|
s1 | 01
|
| 548 |
|
|
s2 | 10
|
| 549 |
|
|
-------------------
|
| 550 |
|
|
Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/Xilinx92.
|
| 551 |
|
|
Reading core .
|
| 552 |
|
|
Loading core for timing and area information for instance .
|
| 553 |
|
|
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
|
| 554 |
|
|
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
|
| 555 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 556 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 557 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 558 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 559 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 560 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 561 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 562 |
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
|
| 563 |
|
|
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <8>.
|
| 564 |
|
|
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <9>.
|
| 565 |
|
|
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <10>.
|
| 566 |
|
|
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <11>.
|
| 567 |
|
|
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <12>.
|
| 568 |
|
|
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <13>.
|
| 569 |
|
|
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <14>.
|
| 570 |
|
|
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <15>.
|
| 571 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 572 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 573 |
|
|
|
| 574 |
|
|
=========================================================================
|
| 575 |
|
|
Advanced HDL Synthesis Report
|
| 576 |
|
|
|
| 577 |
|
|
Macro Statistics
|
| 578 |
|
|
# FSMs : 1
|
| 579 |
|
|
# ROMs : 1
|
| 580 |
|
|
8x1-bit ROM : 1
|
| 581 |
|
|
# Adders/Subtractors : 9
|
| 582 |
|
|
10-bit adder : 2
|
| 583 |
|
|
3-bit adder : 1
|
| 584 |
|
|
32-bit adder : 1
|
| 585 |
|
|
32-bit addsub : 1
|
| 586 |
|
|
4-bit adder : 4
|
| 587 |
|
|
# Counters : 6
|
| 588 |
|
|
10-bit up counter : 2
|
| 589 |
|
|
32-bit up counter : 1
|
| 590 |
|
|
4-bit up counter : 3
|
| 591 |
|
|
# Registers : 352
|
| 592 |
|
|
Flip-Flops : 352
|
| 593 |
|
|
# Latches : 9
|
| 594 |
|
|
1-bit latch : 8
|
| 595 |
|
|
16-bit latch : 1
|
| 596 |
|
|
# Comparators : 14
|
| 597 |
|
|
10-bit comparator greater : 2
|
| 598 |
|
|
10-bit comparator less : 4
|
| 599 |
|
|
32-bit comparator less : 2
|
| 600 |
|
|
4-bit comparator equal : 4
|
| 601 |
|
|
5-bit comparator equal : 2
|
| 602 |
|
|
# Multiplexers : 4
|
| 603 |
|
|
32-bit 4-to-1 multiplexer : 4
|
| 604 |
|
|
# Logic shifters : 2
|
| 605 |
|
|
32-bit shifter logical left : 1
|
| 606 |
|
|
32-bit shifter logical right : 1
|
| 607 |
|
|
# Xors : 2
|
| 608 |
|
|
1-bit xor2 : 1
|
| 609 |
|
|
32-bit xor2 : 1
|
| 610 |
|
|
|
| 611 |
|
|
=========================================================================
|
| 612 |
|
|
|
| 613 |
|
|
=========================================================================
|
| 614 |
|
|
* Low Level Synthesis *
|
| 615 |
|
|
=========================================================================
|
| 616 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 617 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 618 |
|
|
|
| 619 |
|
|
Optimizing unit ...
|
| 620 |
|
|
|
| 621 |
|
|
Optimizing unit ...
|
| 622 |
|
|
|
| 623 |
|
|
Optimizing unit ...
|
| 624 |
|
|
|
| 625 |
|
|
Optimizing unit ...
|
| 626 |
|
|
|
| 627 |
|
|
Optimizing unit ...
|
| 628 |
|
|
|
| 629 |
|
|
Optimizing unit ...
|
| 630 |
|
|
|
| 631 |
|
|
Optimizing unit ...
|
| 632 |
|
|
|
| 633 |
|
|
Optimizing unit ...
|
| 634 |
|
|
|
| 635 |
|
|
Optimizing unit ...
|
| 636 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 637 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 638 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 639 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 640 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 641 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 642 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 643 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
|
| 644 |
|
|
|
| 645 |
|
|
Mapping all equations...
|
| 646 |
|
|
Building and optimizing final netlist ...
|
| 647 |
|
|
Found area constraint ratio of 100 (+ 5) on block mysio, actual ratio is 15.
|
| 648 |
|
|
FlipFlop diogenes_cpu/pipestage1/first has been replicated 1 time(s)
|
| 649 |
|
|
FlipFlop diogenes_cpu/pipestage2/fwop1 has been replicated 1 time(s)
|
| 650 |
|
|
FlipFlop diogenes_cpu/pipestage2/fwop2 has been replicated 1 time(s)
|
| 651 |
|
|
FlipFlop diogenes_cpu/pipestage2/fwshiftop has been replicated 3 time(s)
|
| 652 |
|
|
|
| 653 |
|
|
Final Macro Processing ...
|
| 654 |
|
|
|
| 655 |
|
|
Processing Unit :
|
| 656 |
|
|
Found 3-bit shift register for signal .
|
| 657 |
|
|
Unit processed.
|
| 658 |
|
|
|
| 659 |
|
|
=========================================================================
|
| 660 |
|
|
Final Register Report
|
| 661 |
|
|
|
| 662 |
|
|
Macro Statistics
|
| 663 |
|
|
# Registers : 417
|
| 664 |
|
|
Flip-Flops : 417
|
| 665 |
|
|
# Shift Registers : 1
|
| 666 |
|
|
3-bit shift register : 1
|
| 667 |
|
|
|
| 668 |
|
|
=========================================================================
|
| 669 |
|
|
|
| 670 |
|
|
=========================================================================
|
| 671 |
|
|
* Partition Report *
|
| 672 |
|
|
=========================================================================
|
| 673 |
|
|
|
| 674 |
|
|
Partition Implementation Status
|
| 675 |
|
|
-------------------------------
|
| 676 |
|
|
|
| 677 |
|
|
No Partitions were found in this design.
|
| 678 |
|
|
|
| 679 |
|
|
-------------------------------
|
| 680 |
|
|
|
| 681 |
|
|
=========================================================================
|
| 682 |
|
|
* Final Report *
|
| 683 |
|
|
=========================================================================
|
| 684 |
|
|
Final Results
|
| 685 |
|
|
RTL Top Level Output File Name : mysio.ngr
|
| 686 |
|
|
Top Level Output File Name : mysio
|
| 687 |
|
|
Output Format : NGC
|
| 688 |
|
|
Optimization Goal : Speed
|
| 689 |
|
|
Keep Hierarchy : NO
|
| 690 |
|
|
|
| 691 |
|
|
Design Statistics
|
| 692 |
|
|
# IOs : 35
|
| 693 |
|
|
|
| 694 |
|
|
Cell Usage :
|
| 695 |
|
|
# BELS : 1740
|
| 696 |
|
|
# GND : 2
|
| 697 |
|
|
# INV : 10
|
| 698 |
|
|
# LUT1 : 57
|
| 699 |
|
|
# LUT2 : 123
|
| 700 |
|
|
# LUT2_D : 21
|
| 701 |
|
|
# LUT2_L : 6
|
| 702 |
|
|
# LUT3 : 335
|
| 703 |
|
|
# LUT3_D : 63
|
| 704 |
|
|
# LUT3_L : 46
|
| 705 |
|
|
# LUT4 : 570
|
| 706 |
|
|
# LUT4_D : 24
|
| 707 |
|
|
# LUT4_L : 71
|
| 708 |
|
|
# MUXCY : 200
|
| 709 |
|
|
# MUXF5 : 82
|
| 710 |
|
|
# VCC : 2
|
| 711 |
|
|
# XORCY : 128
|
| 712 |
|
|
# FlipFlops/Latches : 434
|
| 713 |
|
|
# FDC : 241
|
| 714 |
|
|
# FDCE : 120
|
| 715 |
|
|
# FDE : 36
|
| 716 |
|
|
# FDP : 4
|
| 717 |
|
|
# FDPE : 17
|
| 718 |
|
|
# LD : 8
|
| 719 |
|
|
# LDCP : 8
|
| 720 |
|
|
# RAMS : 4
|
| 721 |
|
|
# RAMB16_S2_S2 : 4
|
| 722 |
|
|
# Shift Registers : 1
|
| 723 |
|
|
# SRL16E : 1
|
| 724 |
|
|
# Clock Buffers : 1
|
| 725 |
|
|
# BUFGP : 1
|
| 726 |
|
|
# IO Buffers : 34
|
| 727 |
|
|
# IBUF : 10
|
| 728 |
|
|
# OBUF : 24
|
| 729 |
|
|
# Others : 4
|
| 730 |
|
|
# dist_mem : 2
|
| 731 |
|
|
# dmem : 1
|
| 732 |
|
|
# pmem : 1
|
| 733 |
|
|
=========================================================================
|
| 734 |
|
|
|
| 735 |
|
|
Device utilization summary:
|
| 736 |
|
|
---------------------------
|
| 737 |
|
|
|
| 738 |
|
|
Selected Device : 3s500efg320-4
|
| 739 |
|
|
|
| 740 |
|
|
Number of Slices: 691 out of 4656 14%
|
| 741 |
|
|
Number of Slice Flip Flops: 434 out of 9312 4%
|
| 742 |
|
|
Number of 4 input LUTs: 1327 out of 9312 14%
|
| 743 |
|
|
Number used as logic: 1326
|
| 744 |
|
|
Number used as Shift registers: 1
|
| 745 |
|
|
Number of IOs: 35
|
| 746 |
|
|
Number of bonded IOBs: 35 out of 232 15%
|
| 747 |
|
|
Number of BRAMs: 4 out of 20 20%
|
| 748 |
|
|
Number of GCLKs: 1 out of 24 4%
|
| 749 |
|
|
|
| 750 |
|
|
---------------------------
|
| 751 |
|
|
Partition Resource Summary:
|
| 752 |
|
|
---------------------------
|
| 753 |
|
|
|
| 754 |
|
|
No Partitions were found in this design.
|
| 755 |
|
|
|
| 756 |
|
|
---------------------------
|
| 757 |
|
|
|
| 758 |
|
|
|
| 759 |
|
|
=========================================================================
|
| 760 |
|
|
TIMING REPORT
|
| 761 |
|
|
|
| 762 |
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
| 763 |
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
| 764 |
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
| 765 |
|
|
|
| 766 |
|
|
Clock Information:
|
| 767 |
|
|
------------------
|
| 768 |
|
|
-----------------------------------+-------------------------+-------+
|
| 769 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 770 |
|
|
-----------------------------------+-------------------------+-------+
|
| 771 |
|
|
gclk | BUFGP | 423 |
|
| 772 |
|
|
was_button | NONE(extdin_0) | 8 |
|
| 773 |
|
|
diogenes_cpu/pipestage2/big_op_13 | NONE(sc_uartc/rd_data_0)| 8 |
|
| 774 |
|
|
-----------------------------------+-------------------------+-------+
|
| 775 |
|
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
| 776 |
|
|
|
| 777 |
|
|
Asynchronous Control Signals Information:
|
| 778 |
|
|
----------------------------------------
|
| 779 |
|
|
-----------------------------------------------------------+----------------------------------------+-------+
|
| 780 |
|
|
Control Signal | Buffer(FF name) | Load |
|
| 781 |
|
|
-----------------------------------------------------------+----------------------------------------+-------+
|
| 782 |
|
|
diogenes_cpu/pipestage1/reset_inv(vga_c/reset_inv1_INV_0:O)| NONE(diogenes_cpu/pipestage3/regaddr_1)| 382 |
|
| 783 |
|
|
extdin_0__and0000(extdin_0__and00001:O) | NONE(extdin_0) | 1 |
|
| 784 |
|
|
extdin_0__and0001(extdin_0__and00011:O) | NONE(extdin_0) | 1 |
|
| 785 |
|
|
extdin_4__and0000(extdin_4__and00001:O) | NONE(extdin_4) | 1 |
|
| 786 |
|
|
extdin_4__and0001(extdin_4__and00011:O) | NONE(extdin_4) | 1 |
|
| 787 |
|
|
extdin_7__and0000(extdin_7__and00001:O) | NONE(extdin_7) | 1 |
|
| 788 |
|
|
extdin_7__and0001(extdin_7__and00011:O) | NONE(extdin_7) | 1 |
|
| 789 |
|
|
extdin_2__and0000(extdin_2__and00001:O) | NONE(extdin_2) | 1 |
|
| 790 |
|
|
extdin_2__and0001(extdin_2__and00011:O) | NONE(extdin_2) | 1 |
|
| 791 |
|
|
extdin_6__and0000(extdin_6__and00001:O) | NONE(extdin_6) | 1 |
|
| 792 |
|
|
extdin_6__and0001(extdin_6__and00011:O) | NONE(extdin_6) | 1 |
|
| 793 |
|
|
extdin_1__and0000(extdin_1__and00001:O) | NONE(extdin_1) | 1 |
|
| 794 |
|
|
extdin_1__and0001(extdin_1__and00011:O) | NONE(extdin_1) | 1 |
|
| 795 |
|
|
extdin_3__and0000(extdin_3__and00001:O) | NONE(extdin_3) | 1 |
|
| 796 |
|
|
extdin_3__and0001(extdin_3__and00011:O) | NONE(extdin_3) | 1 |
|
| 797 |
|
|
extdin_5__and0000(extdin_5__and00001:O) | NONE(extdin_5) | 1 |
|
| 798 |
|
|
extdin_5__and0001(extdin_5__and00011:O) | NONE(extdin_5) | 1 |
|
| 799 |
|
|
-----------------------------------------------------------+----------------------------------------+-------+
|
| 800 |
|
|
|
| 801 |
|
|
Timing Summary:
|
| 802 |
|
|
---------------
|
| 803 |
|
|
Speed Grade: -4
|
| 804 |
|
|
|
| 805 |
|
|
Minimum period: 10.634ns (Maximum Frequency: 94.038MHz)
|
| 806 |
|
|
Minimum input arrival time before clock: 10.390ns
|
| 807 |
|
|
Maximum output required time after clock: 9.033ns
|
| 808 |
|
|
Maximum combinational path delay: 5.432ns
|
| 809 |
|
|
|
| 810 |
|
|
Timing Detail:
|
| 811 |
|
|
--------------
|
| 812 |
|
|
All values displayed in nanoseconds (ns)
|
| 813 |
|
|
|
| 814 |
|
|
=========================================================================
|
| 815 |
|
|
Timing constraint: Default period analysis for Clock 'gclk'
|
| 816 |
|
|
Clock period: 10.634ns (frequency: 94.038MHz)
|
| 817 |
|
|
Total number of paths / destination ports: 51871 / 697
|
| 818 |
|
|
-------------------------------------------------------------------------
|
| 819 |
|
|
Delay: 10.634ns (Levels of Logic = 16)
|
| 820 |
|
|
Source: diogenes_cpu/pipestage2/sop1_23 (FF)
|
| 821 |
|
|
Destination: diogenes_cpu/pipestage1/curpc_9 (FF)
|
| 822 |
|
|
Source Clock: gclk rising
|
| 823 |
|
|
Destination Clock: gclk rising
|
| 824 |
|
|
|
| 825 |
|
|
Data Path: diogenes_cpu/pipestage2/sop1_23 to diogenes_cpu/pipestage1/curpc_9
|
| 826 |
|
|
Gate Net
|
| 827 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 828 |
|
|
---------------------------------------- ------------
|
| 829 |
|
|
FDC:C->Q 2 0.591 0.622 diogenes_cpu/pipestage2/sop1_23 (diogenes_cpu/pipestage2/sop1_23)
|
| 830 |
|
|
LUT4:I0->O 1 0.704 0.499 diogenes_cpu/pipestage1/cpc_cmp_eq0002269 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map94)
|
| 831 |
|
|
LUT2:I1->O 1 0.704 0.455 diogenes_cpu/pipestage1/cpc_cmp_eq0002270 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map95)
|
| 832 |
|
|
LUT4:I2->O 5 0.704 0.637 diogenes_cpu/pipestage1/cpc_cmp_eq0002387 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map128)
|
| 833 |
|
|
LUT4:I3->O 18 0.704 1.103 diogenes_cpu/pipestage1/cpc_or00001 (diogenes_cpu/pipestage1/cpc_or0000)
|
| 834 |
|
|
LUT4_D:I2->O 1 0.704 0.455 diogenes_cpu/pipestage1/Mmux_cpc118 (diogenes_cpu/pipestage1/Mmux_cpc1_map7)
|
| 835 |
|
|
LUT4:I2->O 2 0.704 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_lut<0> (diogenes_cpu/pipestage1/N4)
|
| 836 |
|
|
MUXCY:S->O 1 0.464 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<0> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<0>)
|
| 837 |
|
|
MUXCY:CI->O 1 0.059 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<1> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<1>)
|
| 838 |
|
|
MUXCY:CI->O 1 0.059 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<2> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<2>)
|
| 839 |
|
|
MUXCY:CI->O 1 0.059 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<3> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<3>)
|
| 840 |
|
|
MUXCY:CI->O 1 0.059 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<4> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<4>)
|
| 841 |
|
|
MUXCY:CI->O 1 0.059 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<5> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<5>)
|
| 842 |
|
|
MUXCY:CI->O 1 0.059 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<6> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<6>)
|
| 843 |
|
|
MUXCY:CI->O 1 0.059 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<7> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<7>)
|
| 844 |
|
|
MUXCY:CI->O 0 0.059 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<8> (diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_cy<8>)
|
| 845 |
|
|
XORCY:CI->O 1 0.804 0.000 diogenes_cpu/pipestage1/Madd_curpc_9_0_add0000_xor<9> (diogenes_cpu/pipestage1/curpc_9_0_add0000<9>)
|
| 846 |
|
|
FDC:D 0.308 diogenes_cpu/pipestage1/curpc_9
|
| 847 |
|
|
----------------------------------------
|
| 848 |
|
|
Total 10.634ns (6.863ns logic, 3.771ns route)
|
| 849 |
|
|
(64.5% logic, 35.5% route)
|
| 850 |
|
|
|
| 851 |
|
|
=========================================================================
|
| 852 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk'
|
| 853 |
|
|
Total number of paths / destination ports: 7219 / 162
|
| 854 |
|
|
-------------------------------------------------------------------------
|
| 855 |
|
|
Offset: 10.390ns (Levels of Logic = 7)
|
| 856 |
|
|
Source: pmemc:douta<14> (PAD)
|
| 857 |
|
|
Destination: diogenes_cpu/pipestage2/sop2_30 (FF)
|
| 858 |
|
|
Destination Clock: gclk rising
|
| 859 |
|
|
|
| 860 |
|
|
Data Path: pmemc:douta<14> to diogenes_cpu/pipestage2/sop2_30
|
| 861 |
|
|
Gate Net
|
| 862 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 863 |
|
|
---------------------------------------- ------------
|
| 864 |
|
|
pmem:douta<14> 14 0.000 1.175 pmemc (mem_dout_cpu<14>)
|
| 865 |
|
|
LUT3:I0->O 14 0.704 1.004 diogenes_cpu/pipestage2/big_op_mux0010<12>11 (diogenes_cpu/pipestage2/N201)
|
| 866 |
|
|
LUT4:I3->O 3 0.704 0.610 diogenes_cpu/pipestage2/reg2full_0_mux000111 (diogenes_cpu/pipestage2/N2)
|
| 867 |
|
|
LUT4:I1->O 2 0.704 0.482 diogenes_cpu/pipestage2/reg2full_0_mux00012 (diogenes_cpu/pipestage2/reg2full<0>)
|
| 868 |
|
|
LUT4_D:I2->LO 1 0.704 0.104 diogenes_cpu/pipestage2/rf/dout2_cmp_eq0000553 (N4520)
|
| 869 |
|
|
LUT4:I3->O 32 0.704 1.297 diogenes_cpu/pipestage2/rf/dout2_cmp_eq0000555_1 (diogenes_cpu/pipestage2/rf/dout2_cmp_eq0000555)
|
| 870 |
|
|
LUT3_D:I2->O 2 0.704 0.482 diogenes_cpu/pipestage2/rf/dout2<9>1 (diogenes_cpu/pipestage2/rout2<9>)
|
| 871 |
|
|
LUT4:I2->O 1 0.704 0.000 diogenes_cpu/pipestage2/sop2_17_mux00041 (diogenes_cpu/pipestage2/sop2_17_mux0004)
|
| 872 |
|
|
FDC:D 0.308 diogenes_cpu/pipestage2/sop2_17
|
| 873 |
|
|
----------------------------------------
|
| 874 |
|
|
Total 10.390ns (5.236ns logic, 5.154ns route)
|
| 875 |
|
|
(50.4% logic, 49.6% route)
|
| 876 |
|
|
|
| 877 |
|
|
=========================================================================
|
| 878 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'was_button'
|
| 879 |
|
|
Total number of paths / destination ports: 8 / 8
|
| 880 |
|
|
-------------------------------------------------------------------------
|
| 881 |
|
|
Offset: 2.729ns (Levels of Logic = 2)
|
| 882 |
|
|
Source: button<0> (PAD)
|
| 883 |
|
|
Destination: extdin_0 (LATCH)
|
| 884 |
|
|
Destination Clock: was_button falling
|
| 885 |
|
|
|
| 886 |
|
|
Data Path: button<0> to extdin_0
|
| 887 |
|
|
Gate Net
|
| 888 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 889 |
|
|
---------------------------------------- ------------
|
| 890 |
|
|
IBUF:I->O 1 1.218 0.499 button_0_IBUF (button_0_IBUF)
|
| 891 |
|
|
LUT3:I1->O 1 0.704 0.000 extdin_mux0001<0>1 (extdin_mux0001<0>)
|
| 892 |
|
|
LDCP:D 0.308 extdin_0
|
| 893 |
|
|
----------------------------------------
|
| 894 |
|
|
Total 2.729ns (2.230ns logic, 0.499ns route)
|
| 895 |
|
|
(81.7% logic, 18.3% route)
|
| 896 |
|
|
|
| 897 |
|
|
=========================================================================
|
| 898 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk'
|
| 899 |
|
|
Total number of paths / destination ports: 2542 / 181
|
| 900 |
|
|
-------------------------------------------------------------------------
|
| 901 |
|
|
Offset: 9.033ns (Levels of Logic = 6)
|
| 902 |
|
|
Source: diogenes_cpu/pipestage2/sop1_23 (FF)
|
| 903 |
|
|
Destination: pmemc:addra<9> (PAD)
|
| 904 |
|
|
Source Clock: gclk rising
|
| 905 |
|
|
|
| 906 |
|
|
Data Path: diogenes_cpu/pipestage2/sop1_23 to pmemc:addra<9>
|
| 907 |
|
|
Gate Net
|
| 908 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 909 |
|
|
---------------------------------------- ------------
|
| 910 |
|
|
FDC:C->Q 2 0.591 0.622 diogenes_cpu/pipestage2/sop1_23 (diogenes_cpu/pipestage2/sop1_23)
|
| 911 |
|
|
LUT4:I0->O 1 0.704 0.499 diogenes_cpu/pipestage1/cpc_cmp_eq0002269 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map94)
|
| 912 |
|
|
LUT2:I1->O 1 0.704 0.455 diogenes_cpu/pipestage1/cpc_cmp_eq0002270 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map95)
|
| 913 |
|
|
LUT4:I2->O 5 0.704 0.637 diogenes_cpu/pipestage1/cpc_cmp_eq0002387 (diogenes_cpu/pipestage1/cpc_cmp_eq0002_map128)
|
| 914 |
|
|
LUT4:I3->O 18 0.704 1.103 diogenes_cpu/pipestage1/cpc_or00001 (diogenes_cpu/pipestage1/cpc_or0000)
|
| 915 |
|
|
LUT4:I2->O 2 0.704 0.482 diogenes_cpu/pipestage1/Mmux_cpc3222 (diogenes_cpu/pipestage1/Mmux_cpc32_map9)
|
| 916 |
|
|
LUT4:I2->O 1 0.704 0.420 diogenes_cpu/pipestage1/Mmux_cpc3228 (mem_addr_cpu<9>)
|
| 917 |
|
|
pmem:addra<9> 0.000 pmemc
|
| 918 |
|
|
----------------------------------------
|
| 919 |
|
|
Total 9.033ns (4.815ns logic, 4.218ns route)
|
| 920 |
|
|
(53.3% logic, 46.7% route)
|
| 921 |
|
|
|
| 922 |
|
|
=========================================================================
|
| 923 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'was_button'
|
| 924 |
|
|
Total number of paths / destination ports: 16 / 16
|
| 925 |
|
|
-------------------------------------------------------------------------
|
| 926 |
|
|
Offset: 2.366ns (Levels of Logic = 1)
|
| 927 |
|
|
Source: extdin_7 (LATCH)
|
| 928 |
|
|
Destination: diogenes_cpu/pipestage2/rf/reg1:d<7> (PAD)
|
| 929 |
|
|
Source Clock: was_button falling
|
| 930 |
|
|
|
| 931 |
|
|
Data Path: extdin_7 to diogenes_cpu/pipestage2/rf/reg1:d<7>
|
| 932 |
|
|
Gate Net
|
| 933 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 934 |
|
|
---------------------------------------- ------------
|
| 935 |
|
|
LDCP:G->Q 1 0.676 0.455 extdin_7 (extdin_7)
|
| 936 |
|
|
LUT3:I2->O 3 0.704 0.531 diogenes_cpu/pipestage3/Mmux_selected_r30 (diogenes_cpu/result<7>)
|
| 937 |
|
|
dist_mem:d<7> 0.000 diogenes_cpu/pipestage2/rf/reg1
|
| 938 |
|
|
----------------------------------------
|
| 939 |
|
|
Total 2.366ns (1.380ns logic, 0.986ns route)
|
| 940 |
|
|
(58.3% logic, 41.7% route)
|
| 941 |
|
|
|
| 942 |
|
|
=========================================================================
|
| 943 |
|
|
Timing constraint: Default path analysis
|
| 944 |
|
|
Total number of paths / destination ports: 140 / 77
|
| 945 |
|
|
-------------------------------------------------------------------------
|
| 946 |
|
|
Delay: 5.432ns (Levels of Logic = 3)
|
| 947 |
|
|
Source: pmemc:douta<14> (PAD)
|
| 948 |
|
|
Destination: diogenes_cpu/pipestage2/rf/reg2:dpra<1> (PAD)
|
| 949 |
|
|
|
| 950 |
|
|
Data Path: pmemc:douta<14> to diogenes_cpu/pipestage2/rf/reg2:dpra<1>
|
| 951 |
|
|
Gate Net
|
| 952 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 953 |
|
|
---------------------------------------- ------------
|
| 954 |
|
|
pmem:douta<14> 14 0.000 1.175 pmemc (mem_dout_cpu<14>)
|
| 955 |
|
|
LUT3:I0->O 14 0.704 1.004 diogenes_cpu/pipestage2/big_op_mux0010<12>11 (diogenes_cpu/pipestage2/N201)
|
| 956 |
|
|
LUT4:I3->O 3 0.704 0.610 diogenes_cpu/pipestage2/reg2full_0_mux000111 (diogenes_cpu/pipestage2/N2)
|
| 957 |
|
|
LUT4:I1->O 3 0.704 0.531 diogenes_cpu/pipestage2/reg2full_1_mux00011 (diogenes_cpu/pipestage2/reg2full<1>)
|
| 958 |
|
|
dist_mem:dpra<1> 0.000 diogenes_cpu/pipestage2/rf/reg2
|
| 959 |
|
|
----------------------------------------
|
| 960 |
|
|
Total 5.432ns (2.112ns logic, 3.320ns route)
|
| 961 |
|
|
(38.9% logic, 61.1% route)
|
| 962 |
|
|
|
| 963 |
|
|
=========================================================================
|
| 964 |
|
|
CPU : 44.92 / 44.99 s | Elapsed : 45.00 / 45.00 s
|
| 965 |
|
|
|
| 966 |
|
|
-->
|
| 967 |
|
|
|
| 968 |
|
|
|
| 969 |
|
|
Total memory usage is 159876 kilobytes
|
| 970 |
|
|
|
| 971 |
|
|
Number of errors : 0 ( 0 filtered)
|
| 972 |
|
|
Number of warnings : 63 ( 0 filtered)
|
| 973 |
|
|
Number of infos : 25 ( 0 filtered)
|
| 974 |
|
|
|
