1 |
212 |
fellnhofer |
--------------------------------------------------------------------------------
|
2 |
|
|
Release 9.2i Trace
|
3 |
|
|
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
|
4 |
|
|
|
5 |
|
|
trce -ise /home/andi/xilinx/diogenes/vhdl/rs232.ise -intstyle ise -e 3 -s 4
|
6 |
|
|
-xml mysio mysio.ncd -o mysio.twr mysio.pcf -ucf sio.ucf
|
7 |
|
|
|
8 |
|
|
Design file: mysio.ncd
|
9 |
|
|
Physical constraint file: mysio.pcf
|
10 |
|
|
Device,package,speed: xc3s500e,fg320,-4 (PRODUCTION 1.26 2007-04-13)
|
11 |
|
|
Report level: error report
|
12 |
|
|
|
13 |
|
|
Environment Variable Effect
|
14 |
|
|
-------------------- ------
|
15 |
|
|
NONE No environment variables were set
|
16 |
|
|
--------------------------------------------------------------------------------
|
17 |
|
|
|
18 |
|
|
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
19 |
|
|
option. All paths that are not constrained will be reported in the
|
20 |
|
|
unconstrained paths section(s) of the report.
|
21 |
|
|
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
22 |
|
|
a 50 Ohm transmission line loading model. For the details of this model,
|
23 |
|
|
and for more information on accounting for different loading conditions,
|
24 |
|
|
please see the device datasheet.
|
25 |
|
|
|
26 |
|
|
================================================================================
|
27 |
|
|
Timing constraint: NET "gclk_BUFGP/IBUFG" PERIOD = 12 ns HIGH 50%;
|
28 |
|
|
|
29 |
|
|
69212 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
|
30 |
|
|
Minimum period is 11.960ns.
|
31 |
|
|
--------------------------------------------------------------------------------
|
32 |
|
|
|
33 |
|
|
|
34 |
|
|
All constraints were met.
|
35 |
|
|
|
36 |
|
|
|
37 |
|
|
Data Sheet report:
|
38 |
|
|
-----------------
|
39 |
|
|
All values displayed in nanoseconds (ns)
|
40 |
|
|
|
41 |
|
|
Clock to Setup on destination clock gclk
|
42 |
|
|
---------------+---------+---------+---------+---------+
|
43 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
44 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
45 |
|
|
---------------+---------+---------+---------+---------+
|
46 |
|
|
gclk | 11.960| | | |
|
47 |
|
|
---------------+---------+---------+---------+---------+
|
48 |
|
|
|
49 |
|
|
|
50 |
|
|
Timing summary:
|
51 |
|
|
---------------
|
52 |
|
|
|
53 |
|
|
Timing errors: 0 Score: 0
|
54 |
|
|
|
55 |
|
|
Constraints cover 69212 paths, 0 nets, and 5856 connections
|
56 |
|
|
|
57 |
|
|
Design statistics:
|
58 |
|
|
Minimum period: 11.960ns (Maximum frequency: 83.612MHz)
|
59 |
|
|
|
60 |
|
|
|
61 |
|
|
Analysis completed Mon Jan 28 21:06:16 2008
|
62 |
|
|
--------------------------------------------------------------------------------
|
63 |
|
|
|
64 |
|
|
Trace Settings:
|
65 |
|
|
-------------------------
|
66 |
|
|
Trace Settings
|
67 |
|
|
|
68 |
|
|
Peak Memory Usage: 104 MB
|
69 |
|
|
|
70 |
|
|
|
71 |
|
|
|