OpenCores
URL https://opencores.org/ocsvn/diogenes/diogenes/trunk

Subversion Repositories diogenes

[/] [diogenes/] [trunk/] [vhdl/] [rs232.ise] - Blame information for rev 236

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 232 fellnhofer
PK
2
 
3
 
4
,,__REGISTRY__/idem/regkeysClientMessageOutputFile
5
_xmsgs/idem.xmsgs
6
 
7
PK
8
__REGISTRY__/hprep6/PK
9
a..__REGISTRY__/hprep6/regkeysClientMessageOutputFile
10
 
11
s
12
PK
13
__REGISTRY__/ngdbuild/PK
14
 
15
_xmsgs/ngdbuild.xmsgs
16
s
17
PK
18
 
19
++__REGISTRY__/xst/regkeysClientMessageOutputFile
20
_xmsgs/xst.xmsgs
21
s
22
PK
23
 __REGISTRY__/_ProjRepoInternal_/PK
24
I'__REGISTRY__/_ProjRepoInternal_/regkeysISE_VERSION_CREATED_WITH
25
9.1i
26
s
27
ISE_VERSION_LAST_SAVED_WITH
28
9.2i
29
s
30
LastRepoDir
31
/home/andi/xilinx/diogenes/vhdl/
32
s
33
OBJSTORE_VERSION
34
 
35
 
36
REGISTRY_VERSION
37
1.1
38
s
39
 
40
1.1
41
s
42
PK
43
 
44
 
45
9.2i
46
s
47
PK
48
 
49
OUś00__REGISTRY__/ngc2edif/regkeysClientMessageOutputFile
50
_xmsgs/ngc2edif.xmsgs
51
s
52
 
53
__REGISTRY__/map/PK
54
[++__REGISTRY__/map/regkeysClientMessageOutputFile
55
_xmsgs/map.xmsgs
56
 
57
PK
58
__REGISTRY__/xreport/PK
59
__REGISTRY__/xreport/regkeysPK
60
 
61
\-`,,__REGISTRY__/tsim/regkeysClientMessageOutputFile
62
_xmsgs/tsim.xmsgs
63
s
64
 
65
__REGISTRY__/fuse/PK
66
!6,,__REGISTRY__/fuse/regkeysClientMessageOutputFile
67
_xmsgs/fuse.xmsgs
68
 
69
PK
70
__REGISTRY__/par/PK
71
++__REGISTRY__/par/regkeysClientMessageOutputFile
72
 
73
s
74
PK
75
__REGISTRY__/vhpcomp/PK
76
Di//__REGISTRY__/vhpcomp/regkeysClientMessageOutputFile
77
_xmsgs/vhpcomp.xmsgs
78
s
79
PK
80
__REGISTRY__/bitgen/PK
81
6..__REGISTRY__/bitgen/regkeysClientMessageOutputFile
82
_xmsgs/bitgen.xmsgs
83
s
84
PK
85
__REGISTRY__/netgen/PK
86
e6~..__REGISTRY__/netgen/regkeysClientMessageOutputFile
87
_xmsgs/netgen.xmsgs
88
 
89
 
90
__REGISTRY__/runner/PK
91
p7..__REGISTRY__/runner/regkeysClientMessageOutputFile
92
_xmsgs/runner.xmsgs
93
s
94
PK
95
 
96
;-4__REGISTRY__/common/regkeysIncrementalMessagingEnabled
97
false
98
 
99
MessageCaptureEnabled
100
true
101
s
102
MessageFilterFile
103
filter.filter
104
 
105
MessageFilteringEnabled
106
false
107
 
108
RunOnce
109
#/PnAutoRun/Scripts/RunOnce_tcl
110
 
111
PK
112
 __REGISTRY__/HierarchicalDesign/PK
113
 
114
 
115
116
s
117
CommandLine-Ngdbuild
118
 
119
s
120
CommandLine-Par
121
122
 
123
 
124
125
s
126
 
127
 
128
s
129
Previous-NGM
130
131
s
132
Previous-Packed-NCD
133
134
 
135
Previous-Routed-NCD
136
137
s
138
 
139
'__REGISTRY__/HierarchicalDesign/regkeysPK
140
__REGISTRY__/SrcCtrl/PK
141
__REGISTRY__/SrcCtrl/regkeysPK
142
 
143

144
,,__REGISTRY__/trce/regkeysClientMessageOutputFile
145
_xmsgs/trce.xmsgs
146
 
147
 
148
__REGISTRY__/XSLTProcess/PK
149
q33 __REGISTRY__/XSLTProcess/regkeysClientMessageOutputFile
150
_xmsgs/XSLTProcess.xmsgs
151
 
152
 
153
!__REGISTRY__/ProjectNavigatorGui/PK
154
 
155
 
156
E00__REGISTRY__/ngcbuild/regkeysClientMessageOutputFile
157
_xmsgs/ngcbuild.xmsgs
158
s
159
PK
160
__REGISTRY__/WebTalk/PK
161
*__REGISTRY__/WebTalk/DesignDataCollection/PK
162
=<``1__REGISTRY__/WebTalk/DesignDataCollection/regkeysWebTalk-DataCollection-Next-Trigger-Date
163
 
164
s
165
 
166
 
167
s
168
PK
169
__REGISTRY__/WebTalk/regkeysPK
170
__REGISTRY__/cpldfit/PK
171
 
172
 
173
s
174
PK
175
__REGISTRY__/vlogcomp/PK
176
]00__REGISTRY__/vlogcomp/regkeysClientMessageOutputFile
177
_xmsgs/vlogcomp.xmsgs
178
s
179
PK
180
__REGISTRY__/dumpngdio/PK
181
 
182
_xmsgs/dumpngdio.xmsgs
183
s
184
PK
185
__REGISTRY__/ISimPlugin/PK
186
__REGISTRY__/ISimPlugin/regkeysPK
187
__REGISTRY__/taengine/PK
188
00__REGISTRY__/taengine/regkeysClientMessageOutputFile
189
 
190
 
191
PK
192

__OBJSTORE__/PK
193
 __OBJSTORE__/_ProjRepoInternal_/PK
194
__OBJSTORE__/ProjectNavigator/PK
195
/__OBJSTORE__/ProjectNavigator/dpm_project_main/PK
196
ȝ33F__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTblrs232aspartan3spartan3acr2spartan3ePK
197
71RR?__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_mainFyPK
198
aќќ7__OBJSTORE__/ProjectNavigator/__stored_objects___StrTbl
workverilogrs232unisimvcomponentsAND2B1|unisim|vcomponentsAND2B2|unisim|vcomponentsAND2|unisim|vcomponentsAND3B1|unisim|vcomponentsAND3B2|unisim|vcomponentsAND3B3|unisim|vcomponentsAND3|unisim|vcomponentsAND4B1|unisim|vcomponentsAND4B2|unisim|vcomponentsAND4B3|unisim|vcomponentsAND4B4|unisim|vcomponentsAND4|unisim|vcomponentsAND5B1|unisim|vcomponentsAND5B2|unisim|vcomponentsAND5B3|unisim|vcomponentsAND5B4|unisim|vcomponentsAND5B5|unisim|vcomponentsAND5|unisim|vcomponentsAND6|unisim|vcomponentsAND7|unisim|vcomponentsAND8|unisim|vcomponentsBSCAN_FPGACORE|unisim|vcomponentsBSCAN_SPARTAN2|unisim|vcomponentsBSCAN_SPARTAN3A|unisim|vcomponentsBSCAN_SPARTAN3|unisim|vcomponentsBSCAN_VIRTEX2|unisim|vcomponentsBSCAN_VIRTEX4|unisim|vcomponentsBSCAN_VIRTEX5|unisim|vcomponentsBSCAN_VIRTEX|unisim|vcomponentsBUFCF|unisim|vcomponentsBUFE|unisim|vcomponentsBUFFOE|unisim|vcomponentsBUFGCE_1|unisim|vcomponentsBUFGCE|unisim|vcomponentsBUFGCTRL|unisim|vcomponentsBUFGDLL|unisim|vcomponentsBUFGMUX_1|unisim|vcomponentsBUFGMUX_CTRL|unisim|vcomponentsBUFGMUX_VIRTEX4|unisim|vcomponentsBUFGMUX|unisim|vcomponentsBUFGP|unisim|vcomponentsBUFGSR|unisim|vcomponentsBUFGTS|unisim|vcomponentsBUFG|unisim|vcomponentsBUFIO|unisim|vcomponentsBUFR|unisim|vcomponentsBUFT|unisim|vcomponentsBUF|unisim|vcomponentsCAPTURE_FPGACORE|unisim|vcomponentsCAPTURE_SPARTAN2|unisim|vcomponentsCAPTURE_SPARTAN3A|unisim|vcomponentsCAPTURE_SPARTAN3|unisim|vcomponentsCAPTURE_VIRTEX2|unisim|vcomponentsCAPTURE_VIRTEX4|unisim|vcomponentsCAPTURE_VIRTEX5|unisim|vcomponentsCAPTURE_VIRTEX|unisim|vcomponentsCARRY4|unisim|vcomponentsCFGLUT5|unisim|vcomponentsCLKDLLE|unisim|vcomponentsCLKDLLHF|unisim|vcomponentsCLKDLL|unisim|vcomponentsCLK_DIV10RSD|unisim|vcomponentsCLK_DIV10R|unisim|vcomponentsCLK_DIV10SD|unisim|vcomponentsCLK_DIV10|unisim|vcomponentsCLK_DIV12RSD|unisim|vcomponentsCLK_DIV12R|unisim|vcomponentsCLK_DIV12SD|unisim|vcomponentsCLK_DIV12|unisim|vcomponentsCLK_DIV14RSD|unisim|vcomponentsCLK_DIV14R|unisim|vcomponentsCLK_DIV14SD|unisim|vcomponentsCLK_DIV14|unisim|vcomponentsCLK_DIV16RSD|unisim|vcomponentsCLK_DIV16R|unisim|vcomponentsCLK_DIV16SD|unisim|vcomponentsCLK_DIV16|unisim|vcomponentsCLK_DIV2RSD|unisim|vcomponentsCLK_DIV2R|unisim|vcomponentsCLK_DIV2SD|unisim|vcomponentsCLK_DIV2|unisim|vcomponentsCLK_DIV4RSD|unisim|vcomponentsCLK_DIV4R|unisim|vcomponentsCLK_DIV4SD|unisim|vcomponentsCLK_DIV4|unisim|vcomponentsCLK_DIV6RSD|unisim|vcomponentsCLK_DIV6R|unisim|vcomponentsCLK_DIV6SD|unisim|vcomponentsCLK_DIV6|unisim|vcomponentsCLK_DIV8RSD|unisim|vcomponentsCLK_DIV8R|unisim|vcomponentsCLK_DIV8SD|unisim|vcomponentsCLK_DIV8|unisim|vcomponentsCONFIG|unisim|vcomponentsCRC32|unisim|vcomponentsCRC64|unisim|vcomponentsDCC_FPGACORE|unisim|vcomponentsDCIRESET|unisim|vcomponentsDCM_ADV|unisim|vcomponentsDCM_BASE|unisim|vcomponentsDCM_PS|unisim|vcomponentsDCM_SP|unisim|vcomponentsDCM|unisim|vcomponentsDNA_PORT|unisim|vcomponentsDSP48A|unisim|vcomponentsDSP48E|unisim|vcomponentsDSP48|unisim|vcomponentsEMAC|unisim|vcomponentsFDCE_1|unisim|vcomponentsFDCE|unisim|vcomponentsFDCPE_1|unisim|vcomponentsFDCPE|unisim|vcomponentsFDCPX1|unisim|vcomponentsFDCP_1|unisim|vcomponentsFDCP|unisim|vcomponentsFDC_1|unisim|vcomponentsFDC|unisim|vcomponentsFDDCE|unisim|vcomponentsFDDCPE|unisim|vcomponentsFDDCP|unisim|vcomponentsFDDC|unisim|vcomponentsFDDPE|unisim|vcomponentsFDDP|unisim|vcomponentsFDDRCPE|unisim|vcomponentsFDDRRSE|unisim|vcomponentsFDD|unisim|vcomponentsFDE_1|unisim|vcomponentsFDE|unisim|vcomponentsFDPE_1|unisim|vcomponentsFDPE|unisim|vcomponentsFDP_1|unisim|vcomponentsFDP|unisim|vcomponentsFDRE_1|unisim|vcomponentsFDRE|unisim|vcomponentsFDRSE_1|unisim|vcomponentsFDRSE|unisim|vcomponentsFDRS_1|unisim|vcomponentsFDRS|unisim|vcomponentsFDR_1|unisim|vcomponentsFDR|unisim|vcomponentsFDSE_1|unisim|vcomponentsFDSE|unisim|vcomponentsFDS_1|unisim|vcomponentsFDS|unisim|vcomponentsFD_1|unisim|vcomponentsFD|unisim|vcomponentsFIFO16|unisim|vcomponentsFIFO18_36|unisim|vcomponentsFIFO18|unisim|vcomponentsFIFO36_72_EXP|unisim|vcomponentsFIFO36_72|unisim|vcomponentsFIFO36_EXP|unisim|vcomponentsFIFO36|unisim|vcomponentsFMAP|unisim|vcomponentsFRAME_ECC_VIRTEX4|unisim|vcomponentsFRAME_ECC_VIRTEX5|unisim|vcomponentsFTCP|unisim|vcomponentsFTC|unisim|vcomponentsFTP|unisim|vcomponentsGND|unisim|vcomponentsGT10_10GE_4|unisim|vcomponentsGT10_10GE_8|unisim|vcomponentsGT10_10GFC_4|unisim|vcomponentsGT10_10GFC_8|unisim|vcomponentsGT10_AURORAX_4|unisim|vcomponentsGT10_AURORAX_8|unisim|vcomponentsGT10_AURORA_1|unisim|vcomponentsGT10_AURORA_2|unisim|vcomponentsGT10_AURORA_4|unisim|vcomponentsGT10_CUSTOM|unisim|vcomponentsGT10_INFINIBAND_1|unisim|vcomponentsGT10_INFINIBAND_2|unisim|vcomponentsGT10_INFINIBAND_4|unisim|vcomponentsGT10_OC192_4|unisim|vcomponentsGT10_OC192_8|unisim|vcomponentsGT10_OC48_1|unisim|vcomponentsGT10_OC48_2|unisim|vcomponentsGT10_OC48_4|unisim|vcomponentsGT10_PCI_EXPRESS_1|unisim|vcomponentsGT10_PCI_EXPRESS_2|unisim|vcomponentsGT10_PCI_EXPRESS_4|unisim|vcomponentsGT10_XAUI_1|unisim|vcomponentsGT10_XAUI_2|unisim|vcomponentsGT10_XAUI_4|unisim|vcomponentsGT10|unisim|vcomponentsGT11CLK_MGT|unisim|vcomponentsGT11CLK|unisim|vcomponentsGT11_CUSTOM|unisim|vcomponentsGT11_DUAL|unisim|vcomponentsGT11|unisim|vcomponentsGTP_DUAL|unisim|vcomponentsGT_AURORA_1|unisim|vcomponentsGT_AURORA_2|unisim|vcomponentsGT_AURORA_4|unisim|vcomponentsGT_CUSTOM|unisim|vcomponentsGT_ETHERNET_1|unisim|vcomponentsGT_ETHERNET_2|unisim|vcomponentsGT_ETHERNET_4|unisim|vcomponentsGT_FIBRE_CHAN_1|unisim|vcomponentsGT_FIBRE_CHAN_2|unisim|vcomponentsGT_FIBRE_CHAN_4|unisim|vcomponentsGT_INFINIBAND_1|unisim|vcomponentsGT_INFINIBAND_2|unisim|vcomponentsGT_INFINIBAND_4|unisim|vcomponentsGT_XAUI_1|unisim|vcomponentsGT_XAUI_2|unisim|vcomponentsGT_XAUI_4|unisim|vcomponentsGT|unisim|vcomponentsIBUFDS_BLVDS_25|unisim|vcomponentsIBUFDS_DIFF_OUT|unisim|vcomponentsIBUFDS_DLY_ADJ|unisim|vcomponentsIBUFDS_LDT_25|unisim|vcomponentsIBUFDS_LVDSEXT_25_DCI|unisim|vcomponentsIBUFDS_LVDSEXT_25|unisim|vcomponentsIBUFDS_LVDSEXT_33_DCI|unisim|vcomponentsIBUFDS_LVDSEXT_33|unisim|vcomponentsIBUFDS_LVDS_25_DCI|unisim|vcomponentsIBUFDS_LVDS_25|unisim|vcomponentsIBUFDS_LVDS_33_DCI|unisim|vcomponentsIBUFDS_LVDS_33|unisim|vcomponentsIBUFDS_LVPECL_25|unisim|vcomponentsIBUFDS_LVPECL_33|unisim|vcomponentsIBUFDS_ULVDS_25|unisim|vcomponentsIBUFDS|unisim|vcomponentsIBUFGDS_BLVDS_25|unisim|vcomponentsIBUFGDS_DIFF_OUT|unisim|vcomponentsIBUFGDS_LDT_25|unisim|vcomponentsIBUFGDS_LVDSEXT_25_DCI|unisim|vcomponentsIBUFGDS_LVDSEXT_25|unisim|vcomponentsIBUFGDS_LVDSEXT_33_DCI|unisim|vcomponentsIBUFGDS_LVDSEXT_33|unisim|vcomponentsIBUFGDS_LVDS_25_DCI|unisim|vcomponentsIBUFGDS_LVDS_25|unisim|vcomponentsIBUFGDS_LVDS_33_DCI|unisim|vcomponentsIBUFGDS_LVDS_33|unisim|vcomponentsIBUFGDS_LVPECL_25|unisim|vcomponentsIBUFGDS_LVPECL_33|unisim|vcomponentsIBUFGDS_ULVDS_25|unisim|vcomponentsIBUFGDS|unisim|vcomponentsIBUFG_AGP|unisim|vcomponentsIBUFG_CTT|unisim|vcomponentsIBUFG_GTLP_DCI|unisim|vcomponentsIBUFG_GTLP|unisim|vcomponentsIBUFG_GTL_DCI|unisim|vcomponentsIBUFG_GTL|unisim|vcomponentsIBUFG_HSTL_III_18|unisim|vcomponentsIBUFG_HSTL_III_DCI_18|unisim|vcomponentsIBUFG_HSTL_III_DCI|unisim|vcomponentsIBUFG_HSTL_III|unisim|vcomponentsIBUFG_HSTL_II_18|unisim|vcomponentsIBUFG_HSTL_II_DCI_18|unisim|vcomponentsIBUFG_HSTL_II_DCI|unisim|vcomponentsIBUFG_HSTL_II|unisim|vcomponentsIBUFG_HSTL_IV_18|unisim|vcomponentsIBUFG_HSTL_IV_DCI_18|unisim|vcomponentsIBUFG_HSTL_IV_DCI|unisim|vcomponentsIBUFG_HSTL_IV|unisim|vcomponentsIBUFG_HSTL_I_18|unisim|vcomponentsIBUFG_HSTL_I_DCI_18|unisim|vcomponentsIBUFG_HSTL_I_DCI|unisim|vcomponentsIBUFG_HSTL_I|unisim|vcomponentsIBUFG_LVCMOS12|unisim|vcomponentsIBUFG_LVCMOS15|unisim|vcomponentsIBUFG_LVCMOS18|unisim|vcomponentsIBUFG_LVCMOS25|unisim|vcomponentsIBUFG_LVCMOS2|unisim|vcomponentsIBUFG_LVCMOS33|unisim|vcomponentsIBUFG_LVDCI_15|unisim|vcomponentsIBUFG_LVDCI_18|unisim|vcomponentsIBUFG_LVDCI_25|unisim|vcomponentsIBUFG_LVDCI_33|unisim|vcomponentsIBUFG_LVDCI_DV2_15|unisim|vcomponentsIBUFG_LVDCI_DV2_18|unisim|vcomponentsIBUFG_LVDCI_DV2_25|unisim|vcomponentsIBUFG_LVDCI_DV2_33|unisim|vcomponentsIBUFG_LVDS|unisim|vcomponentsIBUFG_LVPECL|unisim|vcomponentsIBUFG_LVTTL|unisim|vcomponentsIBUFG_PCI33_3|unisim|vcomponentsIBUFG_PCI33_5|unisim|vcomponentsIBUFG_PCI66_3|unisim|vcomponentsIBUFG_PCIX66_3|unisim|vcomponentsIBUFG_PCIX|unisim|vcomponentsIBUFG_SSTL18_II_DCI|unisim|vcomponentsIBUFG_SSTL18_II|unisim|vcomponentsIBUFG_SSTL18_I_DCI|unisim|vcomponentsIBUFG_SSTL18_I|unisim|vcomponentsIBUFG_SSTL2_II_DCI|unisim|vcomponentsIBUFG_SSTL2_II|unisim|vcomponentsIBUFG_SSTL2_I_DCI|unisim|vcomponentsIBUFG_SSTL2_I|unisim|vcomponentsIBUFG_SSTL3_II_DCI|unisim|vcomponentsIBUFG_SSTL3_II|unisim|vcomponentsIBUFG_SSTL3_I_DCI|unisim|vcomponentsIBUFG_SSTL3_I|unisim|vcomponentsIBUFG|unisim|vcomponentsIBUF_AGP|unisim|vcomponentsIBUF_CTT|unisim|vcomponentsIBUF_DLY_ADJ|unisim|vcomponentsIBUF_GTLP_DCI|unisim|vcomponentsIBUF_GTLP|unisim|vcomponentsIBUF_GTL_DCI|unisim|vcomponentsIBUF_GTL|unisim|vcomponentsIBUF_HSTL_III_18|unisim|vcomponentsIBUF_HSTL_III_DCI_18|unisim|vcomponentsIBUF_HSTL_III_DCI|unisim|vcomponentsIBUF_HSTL_III|unisim|vcomponentsIBUF_HSTL_II_18|unisim|vcomponentsIBUF_HSTL_II_DCI_18|unisim|vcomponentsIBUF_HSTL_II_DCI|unisim|vcomponentsIBUF_HSTL_II|unisim|vcomponentsIBUF_HSTL_IV_18|unisim|vcomponentsIBUF_HSTL_IV_DCI_18|unisim|vcomponentsIBUF_HSTL_IV_DCI|unisim|vcomponentsIBUF_HSTL_IV|unisim|vcomponentsIBUF_HSTL_I_18|unisim|vcomponentsIBUF_HSTL_I_DCI_18|unisim|vcomponentsIBUF_HSTL_I_DCI|unisim|vcomponentsIBUF_HSTL_I|unisim|vcomponentsIBUF_LVCMOS12|unisim|vcomponentsIBUF_LVCMOS15|unisim|vcomponentsIBUF_LVCMOS18|unisim|vcomponentsIBUF_LVCMOS25|unisim|vcomponentsIBUF_LVCMOS2|unisim|vcomponentsIBUF_LVCMOS33|unisim|vcomponentsIBUF_LVDCI_15|unisim|vcomponentsIBUF_LVDCI_18|unisim|vcomponentsIBUF_LVDCI_25|unisim|vcomponentsIBUF_LVDCI_33|unisim|vcomponentsIBUF_LVDCI_DV2_15|unisim|vcomponentsIBUF_LVDCI_DV2_18|unisim|vcomponentsIBUF_LVDCI_DV2_25|unisim|vcomponentsIBUF_LVDCI_DV2_33|unisim|vcomponentsIBUF_LVDS|unisim|vcomponentsIBUF_LVPECL|unisim|vcomponentsIBUF_LVTTL|unisim|vcomponentsIBUF_PCI33_3|unisim|vcomponentsIBUF_PCI33_5|unisim|vcomponentsIBUF_PCI66_3|unisim|vcomponentsIBUF_PCIX66_3|unisim|vcomponentsIBUF_PCIX|unisim|vcomponentsIBUF_SSTL18_II_DCI|unisim|vcomponentsIBUF_SSTL18_II|unisim|vcomponentsIBUF_SSTL18_I_DCI|unisim|vcomponentsIBUF_SSTL18_I|unisim|vcomponentsIBUF_SSTL2_II_DCI|unisim|vcomponentsIBUF_SSTL2_II|unisim|vcomponentsIBUF_SSTL2_I_DCI|unisim|vcomponentsIBUF_SSTL2_I|unisim|vcomponentsIBUF_SSTL3_II_DCI|unisim|vcomponentsIBUF_SSTL3_II|unisim|vcomponentsIBUF_SSTL3_I_DCI|unisim|vcomponentsIBUF_SSTL3_I|unisim|vcomponentsIBUF|unisim|vcomponentsICAP_SPARTAN3A|unisim|vcomponentsICAP_VIRTEX2|unisim|vcomponentsICAP_VIRTEX4|unisim|vcomponentsICAP_VIRTEX5|unisim|vcomponentsIDDR2|unisim|vcomponentsIDDR_2CLK|unisim|vcomponentsIDDR|unisim|vcomponentsIDELAYCTRL|unisim|vcomponentsIDELAY|unisim|vcomponentsIFDDRCPE|unisim|vcomponentsIFDDRRSE|unisim|vcomponentsILD|unisim|vcomponentsINV|unisim|vcomponentsIOBUFDS_BLVDS_25|unisim|vcomponentsIOBUFDS|unisim|vcomponentsIOBUFE_F|unisim|vcomponentsIOBUFE_S|unisim|vcomponentsIOBUFE|unisim|vcomponentsIOBUF_AGP|unisim|vcomponentsIOBUF_CTT|unisim|vcomponentsIOBUF_F_12|unisim|vcomponentsIOBUF_F_16|unisim|vcomponentsIOBUF_F_24|unisim|vcomponentsIOBUF_F_2|unisim|vcomponentsIOBUF_F_4|unisim|vcomponentsIOBUF_F_6|unisim|vcomponentsIOBUF_F_8|unisim|vcomponentsIOBUF_GTLP_DCI|unisim|vcomponentsIOBUF_GTLP|unisim|vcomponentsIOBUF_GTL_DCI|unisim|vcomponentsIOBUF_GTL|unisim|vcomponentsIOBUF_HSTL_III_18|unisim|vcomponentsIOBUF_HSTL_III|unisim|vcomponentsIOBUF_HSTL_II_18|unisim|vcomponentsIOBUF_HSTL_II_DCI_18|unisim|vcomponentsIOBUF_HSTL_II_DCI|unisim|vcomponentsIOBUF_HSTL_II|unisim|vcomponentsIOBUF_HSTL_IV_18|unisim|vcomponentsIOBUF_HSTL_IV_DCI_18|unisim|vcomponentsIOBUF_HSTL_IV_DCI|unisim|vcomponentsIOBUF_HSTL_IV|unisim|vcomponentsIOBUF_HSTL_I_18|unisim|vcomponentsIOBUF_HSTL_I|unisim|vcomponentsIOBUF_LVCMOS12_F_2|unisim|vcomponentsIOBUF_LVCMOS12_F_4|unisim|vcomponentsIOBUF_LVCMOS12_F_6|unisim|vcomponentsIOBUF_LVCMOS12_F_8|unisim|vcomponentsIOBUF_LVCMOS12_S_2|unisim|vcomponentsIOBUF_LVCMOS12_S_4|unisim|vcomponentsIOBUF_LVCMOS12_S_6|unisim|vcomponentsIOBUF_LVCMOS12_S_8|unisim|vcomponentsIOBUF_LVCMOS12|unisim|vcomponentsIOBUF_LVCMOS15_F_12|unisim|vcomponentsIOBUF_LVCMOS15_F_16|unisim|vcomponentsIOBUF_LVCMOS15_F_2|unisim|vcomponentsIOBUF_LVCMOS15_F_4|unisim|vcomponentsIOBUF_LVCMOS15_F_6|unisim|vcomponentsIOBUF_LVCMOS15_F_8|unisim|vcomponentsIOBUF_LVCMOS15_S_12|unisim|vcomponentsIOBUF_LVCMOS15_S_16|unisim|vcomponentsIOBUF_LVCMOS15_S_2|unisim|vcomponentsIOBUF_LVCMOS15_S_4|unisim|vcomponentsIOBUF_LVCMOS15_S_6|unisim|vcomponentsIOBUF_LVCMOS15_S_8|unisim|vcomponentsIOBUF_LVCMOS15|unisim|vcomponentsIOBUF_LVCMOS18_F_12|unisim|vcomponentsIOBUF_LVCMOS18_F_16|unisim|vcomponentsIOBUF_LVCMOS18_F_2|unisim|vcomponentsIOBUF_LVCMOS18_F_4|unisim|vcomponentsIOBUF_LVCMOS18_F_6|unisim|vcomponentsIOBUF_LVCMOS18_F_8|unisim|vcomponentsIOBUF_LVCMOS18_S_12|unisim|vcomponentsIOBUF_LVCMOS18_S_16|unisim|vcomponentsIOBUF_LVCMOS18_S_2|unisim|vcomponentsIOBUF_LVCMOS18_S_4|unisim|vcomponentsIOBUF_LVCMOS18_S_6|unisim|vcomponentsIOBUF_LVCMOS18_S_8|unisim|vcomponentsIOBUF_LVCMOS18|unisim|vcomponentsIOBUF_LVCMOS25_F_12|unisim|vcomponentsIOBUF_LVCMOS25_F_16|unisim|vcomponentsIOBUF_LVCMOS25_F_24|unisim|vcomponentsIOBUF_LVCMOS25_F_2|unisim|vcomponentsIOBUF_LVCMOS25_F_4|unisim|vcomponentsIOBUF_LVCMOS25_F_6|unisim|vcomponentsIOBUF_LVCMOS25_F_8|unisim|vcomponentsIOBUF_LVCMOS25_S_12|unisim|vcomponentsIOBUF_LVCMOS25_S_16|unisim|vcomponentsIOBUF_LVCMOS25_S_24|unisim|vcomponentsIOBUF_LVCMOS25_S_2|unisim|vcomponentsIOBUF_LVCMOS25_S_4|unisim|vcomponentsIOBUF_LVCMOS25_S_6|unisim|vcomponentsIOBUF_LVCMOS25_S_8|unisim|vcomponentsIOBUF_LVCMOS25|unisim|vcomponentsIOBUF_LVCMOS2|unisim|vcomponentsIOBUF_LVCMOS33_F_12|unisim|vcomponentsIOBUF_LVCMOS33_F_16|unisim|vcomponentsIOBUF_LVCMOS33_F_24|unisim|vcomponentsIOBUF_LVCMOS33_F_2|unisim|vcomponentsIOBUF_LVCMOS33_F_4|unisim|vcomponentsIOBUF_LVCMOS33_F_6|unisim|vcomponentsIOBUF_LVCMOS33_F_8|unisim|vcomponentsIOBUF_LVCMOS33_S_12|unisim|vcomponentsIOBUF_LVCMOS33_S_16|unisim|vcomponentsIOBUF_LVCMOS33_S_24|unisim|vcomponentsIOBUF_LVCMOS33_S_2|unisim|vcomponentsIOBUF_LVCMOS33_S_4|unisim|vcomponentsIOBUF_LVCMOS33_S_6|unisim|vcomponentsIOBUF_LVCMOS33_S_8|unisim|vcomponentsIOBUF_LVCMOS33|unisim|vcomponentsIOBUF_LVDCI_15|unisim|vcomponentsIOBUF_LVDCI_18|unisim|vcomponentsIOBUF_LVDCI_25|unisim|vcomponentsIOBUF_LVDCI_33|unisim|vcomponentsIOBUF_LVDCI_DV2_15|unisim|vcomponentsIOBUF_LVDCI_DV2_18|unisim|vcomponentsIOBUF_LVDCI_DV2_25|unisim|vcomponentsIOBUF_LVDCI_DV2_33|unisim|vcomponentsIOBUF_LVDS|unisim|vcomponentsIOBUF_LVPECL|unisim|vcomponentsIOBUF_LVTTL_F_12|unisim|vcomponentsIOBUF_LVTTL_F_16|unisim|vcomponentsIOBUF_LVTTL_F_24|unisim|vcomponentsIOBUF_LVTTL_F_2|unisim|vcomponentsIOBUF_LVTTL_F_4|unisim|vcomponentsIOBUF_LVTTL_F_6|unisim|vcomponentsIOBUF_LVTTL_F_8|unisim|vcomponentsIOBUF_LVTTL_S_12|unisim|vcomponentsIOBUF_LVTTL_S_16|unisim|vcomponentsIOBUF_LVTTL_S_24|unisim|vcomponentsIOBUF_LVTTL_S_2|unisim|vcomponentsIOBUF_LVTTL_S_4|unisim|vcomponentsIOBUF_LVTTL_S_6|unisim|vcomponentsIOBUF_LVTTL_S_8|unisim|vcomponentsIOBUF_LVTTL|unisim|vcomponentsIOBUF_PCI33_3|unisim|vcomponentsIOBUF_PCI33_5|unisim|vcomponentsIOBUF_PCI66_3|unisim|vcomponentsIOBUF_PCIX66_3|unisim|vcomponentsIOBUF_PCIX|unisim|vcomponentsIOBUF_SSTL18_II_DCI|unisim|vcomponentsIOBUF_SSTL18_II|unisim|vcomponentsIOBUF_SSTL18_I|unisim|vcomponentsIOBUF_SSTL2_II_DCI|unisim|vcomponentsIOBUF_SSTL2_II|unisim|vcomponentsIOBUF_SSTL2_I|unisim|vcomponentsIOBUF_SSTL3_II_DCI|unisim|vcomponentsIOBUF_SSTL3_II|unisim|vcomponentsIOBUF_SSTL3_I|unisim|vcomponentsIOBUF_S_12|unisim|vcomponentsIOBUF_S_16|unisim|vcomponentsIOBUF_S_24|unisim|vcomponentsIOBUF_S_2|unisim|vcomponentsIOBUF_S_4|unisim|vcomponentsIOBUF_S_6|unisim|vcomponentsIOBUF_S_8|unisim|vcomponentsIOBUF|unisim|vcomponentsIODELAY|unisim|vcomponentsISERDES_NODELAY|unisim|vcomponentsISERDES|unisim|vcomponentsJTAGPPC|unisim|vcomponentsKEEPER|unisim|vcomponentsKEEP|unisim|vcomponentsKEY_CLEAR|unisim|vcomponentsLDCE_1|unisim|vcomponentsLDCE|unisim|vcomponentsLDCPE_1|unisim|vcomponentsLDCPE|unisim|vcomponentsLDCP_1|unisim|vcomponentsLDCP|unisim|vcomponentsLDC_1|unisim|vcomponentsLDC|unisim|vcomponentsLDE_1|unisim|vcomponentsLDE|unisim|vcomponentsLDG|unisim|vcomponentsLDPE_1|unisim|vcomponentsLDPE|unisim|vcomponentsLDP_1|unisim|vcomponentsLDP|unisim|vcomponentsLD_1|unisim|vcomponentsLD|unisim|vcomponentsLUT1_D|unisim|vcomponentsLUT1_L|unisim|vcomponentsLUT1|unisim|vcomponentsLUT2_D|unisim|vcomponentsLUT2_L|unisim|vcomponentsLUT2|unisim|vcomponentsLUT3_D|unisim|vcomponentsLUT3_L|unisim|vcomponentsLUT3|unisim|vcomponentsLUT4_D|unisim|vcomponentsLUT4_L|unisim|vcomponentsLUT4|unisim|vcomponentsLUT5_D|unisim|vcomponentsLUT5_L|unisim|vcomponentsLUT5|unisim|vcomponentsLUT6_2|unisim|vcomponentsLUT6_D|unisim|vcomponentsLUT6_L|unisim|vcomponentsLUT6|unisim|vcomponentsMERGE|unisim|vcomponentsMIN_OFF|unisim|vcomponentsMULT18X18SIO|unisim|vcomponentsMULT18X18S|unisim|vcomponentsMULT18X18|unisim|vcomponentsMULT_AND|unisim|vcomponentsMUXCY_D|unisim|vcomponentsMUXCY_L|unisim|vcomponentsMUXCY|unisim|vcomponentsMUXF5_D|unisim|vcomponentsMUXF5_L|unisim|vcomponentsMUXF5|unisim|vcomponentsMUXF6_D|unisim|vcomponentsMUXF6_L|unisim|vcomponentsMUXF6|unisim|vcomponentsMUXF7_D|unisim|vcomponentsMUXF7_L|unisim|vcomponentsMUXF7|unisim|vcomponentsMUXF8_D|unisim|vcomponentsMUXF8_L|unisim|vcomponentsMUXF8|unisim|vcomponentsNAND2B1|unisim|vcomponentsNAND2B2|unisim|vcomponentsNAND2|unisim|vcomponentsNAND3B1|unisim|vcomponentsNAND3B2|unisim|vcomponentsNAND3B3|unisim|vcomponentsNAND3|unisim|vcomponentsNAND4B1|unisim|vcomponentsNAND4B2|unisim|vcomponentsNAND4B3|unisim|vcomponentsNAND4B4|unisim|vcomponentsNAND4|unisim|vcomponentsNAND5B1|unisim|vcomponentsNAND5B2|unisim|vcomponentsNAND5B3|unisim|vcomponentsNAND5B4|unisim|vcomponentsNAND5B5|unisim|vcomponentsNAND5|unisim|vcomponentsNOR2B1|unisim|vcomponentsNOR2B2|unisim|vcomponentsNOR2|unisim|vcomponentsNOR3B1|unisim|vcomponentsNOR3B2|unisim|vcomponentsNOR3B3|unisim|vcomponentsNOR3|unisim|vcomponentsNOR4B1|unisim|vcomponentsNOR4B2|unisim|vcomponentsNOR4B3|unisim|vcomponentsNOR4B4|unisim|vcomponentsNOR4|unisim|vcomponentsNOR5B1|unisim|vcomponentsNOR5B2|unisim|vcomponentsNOR5B3|unisim|vcomponentsNOR5B4|unisim|vcomponentsNOR5B5|unisim|vcomponentsNOR5|unisim|vcomponentsOBUFDS_BLVDS_25|unisim|vcomponentsOBUFDS_LDT_25|unisim|vcomponentsOBUFDS_LVDSEXT_25|unisim|vcomponentsOBUFDS_LVDSEXT_33|unisim|vcomponentsOBUFDS_LVDS_25|unisim|vcomponentsOBUFDS_LVDS_33|unisim|vcomponentsOBUFDS_LVPECL_25|unisim|vcomponentsOBUFDS_LVPECL_33|unisim|vcomponentsOBUFDS_ULVDS_25|unisim|vcomponentsOBUFDS|unisim|vcomponentsOBUFE|unisim|vcomponentsOBUFTDS_BLVDS_25|unisim|vcomponentsOBUFTDS_LDT_25|unisim|vcomponentsOBUFTDS_LVDSEXT_25|unisim|vcomponentsOBUFTDS_LVDSEXT_33|unisim|vcomponentsOBUFTDS_LVDS_25|unisim|vcomponentsOBUFTDS_LVDS_33|unisim|vcomponentsOBUFTDS_LVPECL_25|unisim|vcomponentsOBUFTDS_LVPECL_33|unisim|vcomponentsOBUFTDS_ULVDS_25|unisim|vcomponentsOBUFTDS|unisim|vcomponentsOBUFT_AGP|unisim|vcomponentsOBUFT_CTT|unisim|vcomponentsOBUFT_F_12|unisim|vcomponentsOBUFT_F_16|unisim|vcomponentsOBUFT_F_24|unisim|vcomponentsOBUFT_F_2|unisim|vcomponentsOBUFT_F_4|unisim|vcomponentsOBUFT_F_6|unisim|vcomponentsOBUFT_F_8|unisim|vcomponentsOBUFT_GTLP_DCI|unisim|vcomponentsOBUFT_GTLP|unisim|vcomponentsOBUFT_GTL_DCI|unisim|vcomponentsOBUFT_GTL|unisim|vcomponentsOBUFT_HSTL_III_18|unisim|vcomponentsOBUFT_HSTL_III_DCI_18|unisim|vcomponentsOBUFT_HSTL_III_DCI|unisim|vcomponentsOBUFT_HSTL_III|unisim|vcomponentsOBUFT_HSTL_II_18|unisim|vcomponentsOBUFT_HSTL_II_DCI_18|unisim|vcomponentsOBUFT_HSTL_II_DCI|unisim|vcomponentsOBUFT_HSTL_II|unisim|vcomponentsOBUFT_HSTL_IV_18|unisim|vcomponentsOBUFT_HSTL_IV_DCI_18|unisim|vcomponentsOBUFT_HSTL_IV_DCI|unisim|vcomponentsOBUFT_HSTL_IV|unisim|vcomponentsOBUFT_HSTL_I_18|unisim|vcomponentsOBUFT_HSTL_I_DCI_18|unisim|vcomponentsOBUFT_HSTL_I_DCI|unisim|vcomponentsOBUFT_HSTL_I|unisim|vcomponentsOBUFT_LVCMOS12_F_2|unisim|vcomponentsOBUFT_LVCMOS12_F_4|unisim|vcomponentsOBUFT_LVCMOS12_F_6|unisim|vcomponentsOBUFT_LVCMOS12_F_8|unisim|vcomponentsOBUFT_LVCMOS12_S_2|unisim|vcomponentsOBUFT_LVCMOS12_S_4|unisim|vcomponentsOBUFT_LVCMOS12_S_6|unisim|vcomponentsOBUFT_LVCMOS12_S_8|unisim|vcomponentsOBUFT_LVCMOS12|unisim|vcomponentsOBUFT_LVCMOS15_F_12|unisim|vcomponentsOBUFT_LVCMOS15_F_16|unisim|vcomponentsOBUFT_LVCMOS15_F_2|unisim|vcomponentsOBUFT_LVCMOS15_F_4|unisim|vcomponentsOBUFT_LVCMOS15_F_6|unisim|vcomponentsOBUFT_LVCMOS15_F_8|unisim|vcomponentsOBUFT_LVCMOS15_S_12|unisim|vcomponentsOBUFT_LVCMOS15_S_16|unisim|vcomponentsOBUFT_LVCMOS15_S_2|unisim|vcomponentsOBUFT_LVCMOS15_S_4|unisim|vcomponentsOBUFT_LVCMOS15_S_6|unisim|vcomponentsOBUFT_LVCMOS15_S_8|unisim|vcomponentsOBUFT_LVCMOS15|unisim|vcomponentsOBUFT_LVCMOS18_F_12|unisim|vcomponentsOBUFT_LVCMOS18_F_16|unisim|vcomponentsOBUFT_LVCMOS18_F_2|unisim|vcomponentsOBUFT_LVCMOS18_F_4|unisim|vcomponentsOBUFT_LVCMOS18_F_6|unisim|vcomponentsOBUFT_LVCMOS18_F_8|unisim|vcomponentsOBUFT_LVCMOS18_S_12|unisim|vcomponentsOBUFT_LVCMOS18_S_16|unisim|vcomponentsOBUFT_LVCMOS18_S_2|unisim|vcomponentsOBUFT_LVCMOS18_S_4|unisim|vcomponentsOBUFT_LVCMOS18_S_6|unisim|vcomponentsOBUFT_LVCMOS18_S_8|unisim|vcomponentsOBUFT_LVCMOS18|unisim|vcomponentsOBUFT_LVCMOS25_F_12|unisim|vcomponentsOBUFT_LVCMOS25_F_16|unisim|vcomponentsOBUFT_LVCMOS25_F_24|unisim|vcomponentsOBUFT_LVCMOS25_F_2|unisim|vcomponentsOBUFT_LVCMOS25_F_4|unisim|vcomponentsOBUFT_LVCMOS25_F_6|unisim|vcomponentsOBUFT_LVCMOS25_F_8|unisim|vcomponentsOBUFT_LVCMOS25_S_12|unisim|vcomponentsOBUFT_LVCMOS25_S_16|unisim|vcomponentsOBUFT_LVCMOS25_S_24|unisim|vcomponentsOBUFT_LVCMOS25_S_2|unisim|vcomponentsOBUFT_LVCMOS25_S_4|unisim|vcomponentsOBUFT_LVCMOS25_S_6|unisim|vcomponentsOBUFT_LVCMOS25_S_8|unisim|vcomponentsOBUFT_LVCMOS25|unisim|vcomponentsOBUFT_LVCMOS2|unisim|vcomponentsOBUFT_LVCMOS33_F_12|unisim|vcomponentsOBUFT_LVCMOS33_F_16|unisim|vcomponentsOBUFT_LVCMOS33_F_24|unisim|vcomponentsOBUFT_LVCMOS33_F_2|unisim|vcomponentsOBUFT_LVCMOS33_F_4|unisim|vcomponentsOBUFT_LVCMOS33_F_6|unisim|vcomponentsOBUFT_LVCMOS33_F_8|unisim|vcomponentsOBUFT_LVCMOS33_S_12|unisim|vcomponentsOBUFT_LVCMOS33_S_16|unisim|vcomponentsOBUFT_LVCMOS33_S_24|unisim|vcomponentsOBUFT_LVCMOS33_S_2|unisim|vcomponentsOBUFT_LVCMOS33_S_4|unisim|vcomponentsOBUFT_LVCMOS33_S_6|unisim|vcomponentsOBUFT_LVCMOS33_S_8|unisim|vcomponentsOBUFT_LVCMOS33|unisim|vcomponentsOBUFT_LVDCI_15|unisim|vcomponentsOBUFT_LVDCI_18|unisim|vcomponentsOBUFT_LVDCI_25|unisim|vcomponentsOBUFT_LVDCI_33|unisim|vcomponentsOBUFT_LVDCI_DV2_15|unisim|vcomponentsOBUFT_LVDCI_DV2_18|unisim|vcomponentsOBUFT_LVDCI_DV2_25|unisim|vcomponentsOBUFT_LVDCI_DV2_33|unisim|vcomponentsOBUFT_LVDS|unisim|vcomponentsOBUFT_LVPECL|unisim|vcomponentsOBUFT_LVTTL_F_12|unisim|vcomponentsOBUFT_LVTTL_F_16|unisim|vcomponentsOBUFT_LVTTL_F_24|unisim|vcomponentsOBUFT_LVTTL_F_2|unisim|vcomponentsOBUFT_LVTTL_F_4|unisim|vcomponentsOBUFT_LVTTL_F_6|unisim|vcomponentsOBUFT_LVTTL_F_8|unisim|vcomponentsOBUFT_LVTTL_S_12|unisim|vcomponentsOBUFT_LVTTL_S_16|unisim|vcomponentsOBUFT_LVTTL_S_24|unisim|vcomponentsOBUFT_LVTTL_S_2|unisim|vcomponentsOBUFT_LVTTL_S_4|unisim|vcomponentsOBUFT_LVTTL_S_6|unisim|vcomponentsOBUFT_LVTTL_S_8|unisim|vcomponentsOBUFT_LVTTL|unisim|vcomponentsOBUFT_PCI33_3|unisim|vcomponentsOBUFT_PCI33_5|unisim|vcomponentsOBUFT_PCI66_3|unisim|vcomponentsOBUFT_PCIX66_3|unisim|vcomponentsOBUFT_PCIX|unisim|vcomponentsOBUFT_SSTL18_II_DCI|unisim|vcomponentsOBUFT_SSTL18_II|unisim|vcomponentsOBUFT_SSTL18_I_DCI|unisim|vcomponentsOBUFT_SSTL18_I|unisim|vcomponentsOBUFT_SSTL2_II_DCI|unisim|vcomponentsOBUFT_SSTL2_II|unisim|vcomponentsOBUFT_SSTL2_I_DCI|unisim|vcomponentsOBUFT_SSTL2_I|unisim|vcomponentsOBUFT_SSTL3_II_DCI|unisim|vcomponentsOBUFT_SSTL3_II|unisim|vcomponentsOBUFT_SSTL3_I_DCI|unisim|vcomponentsOBUFT_SSTL3_I|unisim|vcomponentsOBUFT_S_12|unisim|vcomponentsOBUFT_S_16|unisim|vcomponentsOBUFT_S_24|unisim|vcomponentsOBUFT_S_2|unisim|vcomponentsOBUFT_S_4|unisim|vcomponentsOBUFT_S_6|unisim|vcomponentsOBUFT_S_8|unisim|vcomponentsOBUFT|unisim|vcomponentsOBUF_AGP|unisim|vcomponentsOBUF_CTT|unisim|vcomponentsOBUF_F_12|unisim|vcomponentsOBUF_F_16|unisim|vcomponentsOBUF_F_24|unisim|vcomponentsOBUF_F_2|unisim|vcomponentsOBUF_F_4|unisim|vcomponentsOBUF_F_6|unisim|vcomponentsOBUF_F_8|unisim|vcomponentsOBUF_GTLP_DCI|unisim|vcomponentsOBUF_GTLP|unisim|vcomponentsOBUF_GTL_DCI|unisim|vcomponentsOBUF_GTL|unisim|vcomponentsOBUF_HSTL_III_18|unisim|vcomponentsOBUF_HSTL_III_DCI_18|unisim|vcomponentsOBUF_HSTL_III_DCI|unisim|vcomponentsOBUF_HSTL_III|unisim|vcomponentsOBUF_HSTL_II_18|unisim|vcomponentsOBUF_HSTL_II_DCI_18|unisim|vcomponentsOBUF_HSTL_II_DCI|unisim|vcomponentsOBUF_HSTL_II|unisim|vcomponentsOBUF_HSTL_IV_18|unisim|vcomponentsOBUF_HSTL_IV_DCI_18|unisim|vcomponentsOBUF_HSTL_IV_DCI|unisim|vcomponentsOBUF_HSTL_IV|unisim|vcomponentsOBUF_HSTL_I_18|unisim|vcomponentsOBUF_HSTL_I_DCI_18|unisim|vcomponentsOBUF_HSTL_I_DCI|unisim|vcomponentsOBUF_HSTL_I|unisim|vcomponentsOBUF_LVCMOS12_F_2|unisim|vcomponentsOBUF_LVCMOS12_F_4|unisim|vcomponentsOBUF_LVCMOS12_F_6|unisim|vcomponentsOBUF_LVCMOS12_F_8|unisim|vcomponentsOBUF_LVCMOS12_S_2|unisim|vcomponentsOBUF_LVCMOS12_S_4|unisim|vcomponentsOBUF_LVCMOS12_S_6|unisim|vcomponentsOBUF_LVCMOS12_S_8|unisim|vcomponentsOBUF_LVCMOS12|unisim|vcomponentsOBUF_LVCMOS15_F_12|unisim|vcomponentsOBUF_LVCMOS15_F_16|unisim|vcomponentsOBUF_LVCMOS15_F_2|unisim|vcomponentsOBUF_LVCMOS15_F_4|unisim|vcomponentsOBUF_LVCMOS15_F_6|unisim|vcomponentsOBUF_LVCMOS15_F_8|unisim|vcomponentsOBUF_LVCMOS15_S_12|unisim|vcomponentsOBUF_LVCMOS15_S_16|unisim|vcomponentsOBUF_LVCMOS15_S_2|unisim|vcomponentsOBUF_LVCMOS15_S_4|unisim|vcomponentsOBUF_LVCMOS15_S_6|unisim|vcomponentsOBUF_LVCMOS15_S_8|unisim|vcomponentsOBUF_LVCMOS15|unisim|vcomponentsOBUF_LVCMOS18_F_12|unisim|vcomponentsOBUF_LVCMOS18_F_16|unisim|vcomponentsOBUF_LVCMOS18_F_2|unisim|vcomponentsOBUF_LVCMOS18_F_4|unisim|vcomponentsOBUF_LVCMOS18_F_6|unisim|vcomponentsOBUF_LVCMOS18_F_8|unisim|vcomponentsOBUF_LVCMOS18_S_12|unisim|vcomponentsOBUF_LVCMOS18_S_16|unisim|vcomponentsOBUF_LVCMOS18_S_2|unisim|vcomponentsOBUF_LVCMOS18_S_4|unisim|vcomponentsOBUF_LVCMOS18_S_6|unisim|vcomponentsOBUF_LVCMOS18_S_8|unisim|vcomponentsOBUF_LVCMOS18|unisim|vcomponentsOBUF_LVCMOS25_F_12|unisim|vcomponentsOBUF_LVCMOS25_F_16|unisim|vcomponentsOBUF_LVCMOS25_F_24|unisim|vcomponentsOBUF_LVCMOS25_F_2|unisim|vcomponentsOBUF_LVCMOS25_F_4|unisim|vcomponentsOBUF_LVCMOS25_F_6|unisim|vcomponentsOBUF_LVCMOS25_F_8|unisim|vcomponentsOBUF_LVCMOS25_S_12|unisim|vcomponentsOBUF_LVCMOS25_S_16|unisim|vcomponentsOBUF_LVCMOS25_S_24|unisim|vcomponentsOBUF_LVCMOS25_S_2|unisim|vcomponentsOBUF_LVCMOS25_S_4|unisim|vcomponentsOBUF_LVCMOS25_S_6|unisim|vcomponentsOBUF_LVCMOS25_S_8|unisim|vcomponentsOBUF_LVCMOS25|unisim|vcomponentsOBUF_LVCMOS2|unisim|vcomponentsOBUF_LVCMOS33_F_12|unisim|vcomponentsOBUF_LVCMOS33_F_16|unisim|vcomponentsOBUF_LVCMOS33_F_24|unisim|vcomponentsOBUF_LVCMOS33_F_2|unisim|vcomponentsOBUF_LVCMOS33_F_4|unisim|vcomponentsOBUF_LVCMOS33_F_6|unisim|vcomponentsOBUF_LVCMOS33_F_8|unisim|vcomponentsOBUF_LVCMOS33_S_12|unisim|vcomponentsOBUF_LVCMOS33_S_16|unisim|vcomponentsOBUF_LVCMOS33_S_24|unisim|vcomponentsOBUF_LVCMOS33_S_2|unisim|vcomponentsOBUF_LVCMOS33_S_4|unisim|vcomponentsOBUF_LVCMOS33_S_6|unisim|vcomponentsOBUF_LVCMOS33_S_8|unisim|vcomponentsOBUF_LVCMOS33|unisim|vcomponentsOBUF_LVDCI_15|unisim|vcomponentsOBUF_LVDCI_18|unisim|vcomponentsOBUF_LVDCI_25|unisim|vcomponentsOBUF_LVDCI_33|unisim|vcomponentsOBUF_LVDCI_DV2_15|unisim|vcomponentsOBUF_LVDCI_DV2_18|unisim|vcomponentsOBUF_LVDCI_DV2_25|unisim|vcomponentsOBUF_LVDCI_DV2_33|unisim|vcomponentsOBUF_LVDS|unisim|vcomponentsOBUF_LVPECL|unisim|vcomponentsOBUF_LVTTL_F_12|unisim|vcomponentsOBUF_LVTTL_F_16|unisim|vcomponentsOBUF_LVTTL_F_24|unisim|vcomponentsOBUF_LVTTL_F_2|unisim|vcomponentsOBUF_LVTTL_F_4|unisim|vcomponentsOBUF_LVTTL_F_6|unisim|vcomponentsOBUF_LVTTL_F_8|unisim|vcomponentsOBUF_LVTTL_S_12|unisim|vcomponentsOBUF_LVTTL_S_16|unisim|vcomponentsOBUF_LVTTL_S_24|unisim|vcomponentsOBUF_LVTTL_S_2|unisim|vcomponentsOBUF_LVTTL_S_4|unisim|vcomponentsOBUF_LVTTL_S_6|unisim|vcomponentsOBUF_LVTTL_S_8|unisim|vcomponentsOBUF_LVTTL|unisim|vcomponentsOBUF_PCI33_3|unisim|vcomponentsOBUF_PCI33_5|unisim|vcomponentsOBUF_PCI66_3|unisim|vcomponentsOBUF_PCIX66_3|unisim|vcomponentsOBUF_PCIX|unisim|vcomponentsOBUF_SSTL18_II_DCI|unisim|vcomponentsOBUF_SSTL18_II|unisim|vcomponentsOBUF_SSTL18_I_DCI|unisim|vcomponentsOBUF_SSTL18_I|unisim|vcomponentsOBUF_SSTL2_II_DCI|unisim|vcomponentsOBUF_SSTL2_II|unisim|vcomponentsOBUF_SSTL2_I_DCI|unisim|vcomponentsOBUF_SSTL2_I|unisim|vcomponentsOBUF_SSTL3_II_DCI|unisim|vcomponentsOBUF_SSTL3_II|unisim|vcomponentsOBUF_SSTL3_I_DCI|unisim|vcomponentsOBUF_SSTL3_I|unisim|vcomponentsOBUF_S_12|unisim|vcomponentsOBUF_S_16|unisim|vcomponentsOBUF_S_24|unisim|vcomponentsOBUF_S_2|unisim|vcomponentsOBUF_S_4|unisim|vcomponentsOBUF_S_6|unisim|vcomponentsOBUF_S_8|unisim|vcomponentsOBUF|unisim|vcomponentsODDR2|unisim|vcomponentsODDR|unisim|vcomponentsOFDDRCPE|unisim|vcomponentsOFDDRRSE|unisim|vcomponentsOFDDRTCPE|unisim|vcomponentsOFDDRTRSE|unisim|vcomponentsOPT_OFF|unisim|vcomponentsOPT_UIM|unisim|vcomponentsOR2B1|unisim|vcomponentsOR2B2|unisim|vcomponentsOR2|unisim|vcomponentsOR3B1|unisim|vcomponentsOR3B2|unisim|vcomponentsOR3B3|unisim|vcomponentsOR3|unisim|vcomponentsOR4B1|unisim|vcomponentsOR4B2|unisim|vcomponentsOR4B3|unisim|vcomponentsOR4B4|unisim|vcomponentsOR4|unisim|vcomponentsOR5B1|unisim|vcomponentsOR5B2|unisim|vcomponentsOR5B3|unisim|vcomponentsOR5B4|unisim|vcomponentsOR5B5|unisim|vcomponentsOR5|unisim|vcomponentsOR6|unisim|vcomponentsOR7|unisim|vcomponentsOR8|unisim|vcomponentsORCY|unisim|vcomponentsOSERDES|unisim|vcomponentsPCIE_EP|unisim|vcomponentsPCIE_INTERNAL_1_1|unisim|vcomponentsPLL_ADV|unisim|vcomponentsPLL_BASE|unisim|vcomponentsPMCD|unisim|vcomponentsPPC405_ADV|unisim|vcomponentsPPC405|unisim|vcomponentsPULLDOWN|unisim|vcomponentsPULLUP|unisim|vcomponentsRAM128X1D|unisim|vcomponentsRAM128X1S_1|unisim|vcomponentsRAM128X1S|unisim|vcomponentsRAM16X1D_1|unisim|vcomponentsRAM16X1D|unisim|vcomponentsRAM16X1S_1|unisim|vcomponentsRAM16X1S|unisim|vcomponentsRAM16X2S|unisim|vcomponentsRAM16X4S|unisim|vcomponentsRAM16X8S|unisim|vcomponentsRAM256X1S|unisim|vcomponentsRAM32M|unisim|vcomponentsRAM32X1D_1|unisim|vcomponentsRAM32X1D|unisim|vcomponentsRAM32X1S_1|unisim|vcomponentsRAM32X1S|unisim|vcomponentsRAM32X2S|unisim|vcomponentsRAM32X4S|unisim|vcomponentsRAM32X8S|unisim|vcomponentsRAM64M|unisim|vcomponentsRAM64X1D_1|unisim|vcomponentsRAM64X1D|unisim|vcomponentsRAM64X1S_1|unisim|vcomponentsRAM64X1S|unisim|vcomponentsRAM64X2S|unisim|vcomponentsRAMB16BWER|unisim|vcomponentsRAMB16BWE_S18_S18|unisim|vcomponentsRAMB16BWE_S18_S9|unisim|vcomponentsRAMB16BWE_S18|unisim|vcomponentsRAMB16BWE_S36_S18|unisim|vcomponentsRAMB16BWE_S36_S36|unisim|vcomponentsRAMB16BWE_S36_S9|unisim|vcomponentsRAMB16BWE_S36|unisim|vcomponentsRAMB16BWE|unisim|vcomponentsRAMB16_S18_S18|unisim|vcomponentsRAMB16_S18_S36|unisim|vcomponentsRAMB16_S18|unisim|vcomponentsRAMB16_S1_S18|unisim|vcomponentsRAMB16_S1_S1|unisim|vcomponentsRAMB16_S1_S2|unisim|vcomponentsRAMB16_S1_S36|unisim|vcomponentsRAMB16_S1_S4|unisim|vcomponentsRAMB16_S1_S9|unisim|vcomponentsRAMB16_S1|unisim|vcomponentsRAMB16_S2_S18|unisim|vcomponentsRAMB16_S2_S2|unisim|vcomponentsRAMB16_S2_S36|unisim|vcomponentsRAMB16_S2_S4|unisim|vcomponentsRAMB16_S2_S9|unisim|vcomponentsRAMB16_S2|unisim|vcomponentsRAMB16_S36_S36|unisim|vcomponentsRAMB16_S36|unisim|vcomponentsRAMB16_S4_S18|unisim|vcomponentsRAMB16_S4_S36|unisim|vcomponentsRAMB16_S4_S4|unisim|vcomponentsRAMB16_S4_S9|unisim|vcomponentsRAMB16_S4|unisim|vcomponentsRAMB16_S9_S18|unisim|vcomponentsRAMB16_S9_S36|unisim|vcomponentsRAMB16_S9_S9|unisim|vcomponentsRAMB16_S9|unisim|vcomponentsRAMB16|unisim|vcomponentsRAMB18SDP|unisim|vcomponentsRAMB18|unisim|vcomponentsRAMB32_S64_ECC|unisim|vcomponentsRAMB36SDP_EXP|unisim|vcomponentsRAMB36SDP|unisim|vcomponentsRAMB36_EXP|unisim|vcomponentsRAMB36|unisim|vcomponentsRAMB4_S16_S16|unisim|vcomponentsRAMB4_S16|unisim|vcomponentsRAMB4_S1_S16|unisim|vcomponentsRAMB4_S1_S1|unisim|vcomponentsRAMB4_S1_S2|unisim|vcomponentsRAMB4_S1_S4|unisim|vcomponentsRAMB4_S1_S8|unisim|vcomponentsRAMB4_S1|unisim|vcomponentsRAMB4_S2_S16|unisim|vcomponentsRAMB4_S2_S2|unisim|vcomponentsRAMB4_S2_S4|unisim|vcomponentsRAMB4_S2_S8|unisim|vcomponentsRAMB4_S2|unisim|vcomponentsRAMB4_S4_S16|unisim|vcomponentsRAMB4_S4_S4|unisim|vcomponentsRAMB4_S4_S8|unisim|vcomponentsRAMB4_S4|unisim|vcomponentsRAMB4_S8_S16|unisim|vcomponentsRAMB4_S8_S8|unisim|vcomponentsRAMB4_S8|unisim|vcomponentsROCBUF|unisim|vcomponentsROC|unisim|vcomponentsROM128X1|unisim|vcomponentsROM16X1|unisim|vcomponentsROM256X1|unisim|vcomponentsROM32X1|unisim|vcomponentsROM64X1|unisim|vcomponentsSPI_ACCESS|unisim|vcomponentsSRL16E_1|unisim|vcomponentsSRL16E|unisim|vcomponentsSRL16_1|unisim|vcomponentsSRL16|unisim|vcomponentsSRLC16E_1|unisim|vcomponentsSRLC16E|unisim|vcomponentsSRLC16_1|unisim|vcomponentsSRLC16|unisim|vcomponentsSRLC32E|unisim|vcomponentsSTARTBUF_FPGACORE|unisim|vcomponentsSTARTBUF_SPARTAN2|unisim|vcomponentsSTARTBUF_SPARTAN3|unisim|vcomponentsSTARTBUF_VIRTEX2|unisim|vcomponentsSTARTBUF_VIRTEX4|unisim|vcomponentsSTARTBUF_VIRTEX|unisim|vcomponentsSTARTUP_FPGACORE|unisim|vcomponentsSTARTUP_SPARTAN2|unisim|vcomponentsSTARTUP_SPARTAN3A|unisim|vcomponentsSTARTUP_SPARTAN3E|unisim|vcomponentsSTARTUP_SPARTAN3|unisim|vcomponentsSTARTUP_VIRTEX2|unisim|vcomponentsSTARTUP_VIRTEX4|unisim|vcomponentsSTARTUP_VIRTEX5|unisim|vcomponentsSTARTUP_VIRTEX|unisim|vcomponentsSYSMON|unisim|vcomponentsTBLOCK|unisim|vcomponentsTEMAC|unisim|vcomponentsTIMEGRP|unisim|vcomponentsTIMESPEC|unisim|vcomponentsTOCBUF|unisim|vcomponentsTOC|unisim|vcomponentsUSR_ACCESS_VIRTEX4|unisim|vcomponentsUSR_ACCESS_VIRTEX5|unisim|vcomponentsVCC|unisim|vcomponentsWIREAND|unisim|vcomponentsXNOR2|unisim|vcomponentsXNOR3|unisim|vcomponentsXNOR4|unisim|vcomponentsXNOR5|unisim|vcomponentsXOR2|unisim|vcomponentsXOR3|unisim|vcomponentsXOR4|unisim|vcomponentsXOR5|unisim|vcomponentsXORCY_D|unisim|vcomponentsXORCY_L|unisim|vcomponentsXORCY|unisim|vcomponentsand2b1|unisim|vcomponentsand2b2|unisim|vcomponentsand2|unisim|vcomponentsand3b1|unisim|vcomponentsand3b2|unisim|vcomponentsand3b3|unisim|vcomponentsand3|unisim|vcomponentsand4b1|unisim|vcomponentsand4b2|unisim|vcomponentsand4b3|unisim|vcomponentsand4b4|unisim|vcomponentsand4|unisim|vcomponentsand5b1|unisim|vcomponentsand5b2|unisim|vcomponentsand5b3|unisim|vcomponentsand5b4|unisim|vcomponentsand5b5|unisim|vcomponentsand5|unisim|vcomponentsand6|unisim|vcomponentsand7|unisim|vcomponentsand8|unisim|vcomponentsbscan_fpgacore|unisim|vcomponentsbscan_spartan2|unisim|vcomponentsbscan_spartan3a|unisim|vcomponentsbscan_spartan3|unisim|vcomponentsbscan_virtex2|unisim|vcomponentsbscan_virtex4|unisim|vcomponentsbscan_virtex5|unisim|vcomponentsbscan_virtex|unisim|vcomponentsbufcf|unisim|vcomponentsbufe|unisim|vcomponentsbuffoe|unisim|vcomponentsbufgce_1|unisim|vcomponentsbufgce|unisim|vcomponentsbufgctrl|unisim|vcomponentsbufgdll|unisim|vcomponentsbufgmux_1|unisim|vcomponentsbufgmux_ctrl|unisim|vcomponentsbufgmux_virtex4|unisim|vcomponentsbufgmux|unisim|vcomponentsbufgp|unisim|vcomponentsbufgsr|unisim|vcomponentsbufgts|unisim|vcomponentsbufg|unisim|vcomponentsbufio|unisim|vcomponentsbufr|unisim|vcomponentsbuft|unisim|vcomponentsbuf|unisim|vcomponentscapture_fpgacore|unisim|vcomponentscapture_spartan2|unisim|vcomponentscapture_spartan3a|unisim|vcomponentscapture_spartan3|unisim|vcomponentscapture_virtex2|unisim|vcomponentscapture_virtex4|unisim|vcomponentscapture_virtex5|unisim|vcomponentscapture_virtex|unisim|vcomponentscarry4|unisim|vcomponentscfglut5|unisim|vcomponentsclk_div10rsd|unisim|vcomponentsclk_div10r|unisim|vcomponentsclk_div10sd|unisim|vcomponentsclk_div10|unisim|vcomponentsclk_div12rsd|unisim|vcomponentsclk_div12r|unisim|vcomponentsclk_div12sd|unisim|vcomponentsclk_div12|unisim|vcomponentsclk_div14rsd|unisim|vcomponentsclk_div14r|unisim|vcomponentsclk_div14sd|unisim|vcomponentsclk_div14|unisim|vcomponentsclk_div16rsd|unisim|vcomponentsclk_div16r|unisim|vcomponentsclk_div16sd|unisim|vcomponentsclk_div16|unisim|vcomponentsclk_div2rsd|unisim|vcomponentsclk_div2r|unisim|vcomponentsclk_div2sd|unisim|vcomponentsclk_div2|unisim|vcomponentsclk_div4rsd|unisim|vcomponentsclk_div4r|unisim|vcomponentsclk_div4sd|unisim|vcomponentsclk_div4|unisim|vcomponentsclk_div6rsd|unisim|vcomponentsclk_div6r|unisim|vcomponentsclk_div6sd|unisim|vcomponentsclk_div6|unisim|vcomponentsclk_div8rsd|unisim|vcomponentsclk_div8r|unisim|vcomponentsclk_div8sd|unisim|vcomponentsclk_div8|unisim|vcomponentsclkdlle|unisim|vcomponentsclkdllhf|unisim|vcomponentsclkdll|unisim|vcomponentsconfig|unisim|vcomponentscrc32|unisim|vcomponentscrc64|unisim|vcomponentsdcc_fpgacore|unisim|vcomponentsdcireset|unisim|vcomponentsdcm_adv|unisim|vcomponentsdcm_base|unisim|vcomponentsdcm_ps|unisim|vcomponentsdcm_sp|unisim|vcomponentsdcm|unisim|vcomponentsdna_port|unisim|vcomponentsdsp48a|unisim|vcomponentsdsp48e|unisim|vcomponentsdsp48|unisim|vcomponentsemac|unisim|vcomponentsfd_1|unisim|vcomponentsfdc_1|unisim|vcomponentsfdce_1|unisim|vcomponentsfdce|unisim|vcomponentsfdcp_1|unisim|vcomponentsfdcpe_1|unisim|vcomponentsfdcpe|unisim|vcomponentsfdcpx1|unisim|vcomponentsfdcp|unisim|vcomponentsfdc|unisim|vcomponentsfddce|unisim|vcomponentsfddcpe|unisim|vcomponentsfddcp|unisim|vcomponentsfddc|unisim|vcomponentsfddpe|unisim|vcomponentsfddp|unisim|vcomponentsfddrcpe|unisim|vcomponentsfddrrse|unisim|vcomponentsfdd|unisim|vcomponentsfde_1|unisim|vcomponentsfde|unisim|vcomponentsfdp_1|unisim|vcomponentsfdpe_1|unisim|vcomponentsfdpe|unisim|vcomponentsfdp|unisim|vcomponentsfdr_1|unisim|vcomponentsfdre_1|unisim|vcomponentsfdre|unisim|vcomponentsfdrs_1|unisim|vcomponentsfdrse_1|unisim|vcomponentsfdrse|unisim|vcomponentsfdrs|unisim|vcomponentsfdr|unisim|vcomponentsfds_1|unisim|vcomponentsfdse_1|unisim|vcomponentsfdse|unisim|vcomponentsfds|unisim|vcomponentsfd|unisim|vcomponentsfifo16|unisim|vcomponentsfifo18_36|unisim|vcomponentsfifo18|unisim|vcomponentsfifo36_72_exp|unisim|vcomponentsfifo36_72|unisim|vcomponentsfifo36_exp|unisim|vcomponentsfifo36|unisim|vcomponentsfmap|unisim|vcomponentsframe_ecc_virtex4|unisim|vcomponentsframe_ecc_virtex5|unisim|vcomponentsftcp|unisim|vcomponentsftc|unisim|vcomponentsftp|unisim|vcomponentsgnd|unisim|vcomponentsgt10_10ge_4|unisim|vcomponentsgt10_10ge_8|unisim|vcomponentsgt10_10gfc_4|unisim|vcomponentsgt10_10gfc_8|unisim|vcomponentsgt10_aurora_1|unisim|vcomponentsgt10_aurora_2|unisim|vcomponentsgt10_aurora_4|unisim|vcomponentsgt10_aurorax_4|unisim|vcomponentsgt10_aurorax_8|unisim|vcomponentsgt10_custom|unisim|vcomponentsgt10_infiniband_1|unisim|vcomponentsgt10_infiniband_2|unisim|vcomponentsgt10_infiniband_4|unisim|vcomponentsgt10_oc192_4|unisim|vcomponentsgt10_oc192_8|unisim|vcomponentsgt10_oc48_1|unisim|vcomponentsgt10_oc48_2|unisim|vcomponentsgt10_oc48_4|unisim|vcomponentsgt10_pci_express_1|unisim|vcomponentsgt10_pci_express_2|unisim|vcomponentsgt10_pci_express_4|unisim|vcomponentsgt10_xaui_1|unisim|vcomponentsgt10_xaui_2|unisim|vcomponentsgt10_xaui_4|unisim|vcomponentsgt10|unisim|vcomponentsgt11_custom|unisim|vcomponentsgt11_dual|unisim|vcomponentsgt11clk_mgt|unisim|vcomponentsgt11clk|unisim|vcomponentsgt11|unisim|vcomponentsgt_aurora_1|unisim|vcomponentsgt_aurora_2|unisim|vcomponentsgt_aurora_4|unisim|vcomponentsgt_custom|unisim|vcomponentsgt_ethernet_1|unisim|vcomponentsgt_ethernet_2|unisim|vcomponentsgt_ethernet_4|unisim|vcomponentsgt_fibre_chan_1|unisim|vcomponentsgt_fibre_chan_2|unisim|vcomponentsgt_fibre_chan_4|unisim|vcomponentsgt_infiniband_1|unisim|vcomponentsgt_infiniband_2|unisim|vcomponentsgt_infiniband_4|unisim|vcomponentsgt_xaui_1|unisim|vcomponentsgt_xaui_2|unisim|vcomponentsgt_xaui_4|unisim|vcomponentsgtp_dual|unisim|vcomponentsgt|unisim|vcomponentsibuf_agp|unisim|vcomponentsibuf_ctt|unisim|vcomponentsibuf_dly_adj|unisim|vcomponentsibuf_gtl_dci|unisim|vcomponentsibuf_gtlp_dci|unisim|vcomponentsibuf_gtlp|unisim|vcomponentsibuf_gtl|unisim|vcomponentsibuf_hstl_i_18|unisim|vcomponentsibuf_hstl_i_dci_18|unisim|vcomponentsibuf_hstl_i_dci|unisim|vcomponentsibuf_hstl_ii_18|unisim|vcomponentsibuf_hstl_ii_dci_18|unisim|vcomponentsibuf_hstl_ii_dci|unisim|vcomponentsibuf_hstl_iii_18|unisim|vcomponentsibuf_hstl_iii_dci_18|unisim|vcomponentsibuf_hstl_iii_dci|unisim|vcomponentsibuf_hstl_iii|unisim|vcomponentsibuf_hstl_ii|unisim|vcomponentsibuf_hstl_iv_18|unisim|vcomponentsibuf_hstl_iv_dci_18|unisim|vcomponentsibuf_hstl_iv_dci|unisim|vcomponentsibuf_hstl_iv|unisim|vcomponentsibuf_hstl_i|unisim|vcomponentsibuf_lvcmos12|unisim|vcomponentsibuf_lvcmos15|unisim|vcomponentsibuf_lvcmos18|unisim|vcomponentsibuf_lvcmos25|unisim|vcomponentsibuf_lvcmos2|unisim|vcomponentsibuf_lvcmos33|unisim|vcomponentsibuf_lvdci_15|unisim|vcomponentsibuf_lvdci_18|unisim|vcomponentsibuf_lvdci_25|unisim|vcomponentsibuf_lvdci_33|unisim|vcomponentsibuf_lvdci_dv2_15|unisim|vcomponentsibuf_lvdci_dv2_18|unisim|vcomponentsibuf_lvdci_dv2_25|unisim|vcomponentsibuf_lvdci_dv2_33|unisim|vcomponentsibuf_lvds|unisim|vcomponentsibuf_lvpecl|unisim|vcomponentsibuf_lvttl|unisim|vcomponentsibuf_pci33_3|unisim|vcomponentsibuf_pci33_5|unisim|vcomponentsibuf_pci66_3|unisim|vcomponentsibuf_pcix66_3|unisim|vcomponentsibuf_pcix|unisim|vcomponentsibuf_sstl18_i_dci|unisim|vcomponentsibuf_sstl18_ii_dci|unisim|vcomponentsibuf_sstl18_ii|unisim|vcomponentsibuf_sstl18_i|unisim|vcomponentsibuf_sstl2_i_dci|unisim|vcomponentsibuf_sstl2_ii_dci|unisim|vcomponentsibuf_sstl2_ii|unisim|vcomponentsibuf_sstl2_i|unisim|vcomponentsibuf_sstl3_i_dci|unisim|vcomponentsibuf_sstl3_ii_dci|unisim|vcomponentsibuf_sstl3_ii|unisim|vcomponentsibuf_sstl3_i|unisim|vcomponentsibufds_blvds_25|unisim|vcomponentsibufds_diff_out|unisim|vcomponentsibufds_dly_adj|unisim|vcomponentsibufds_ldt_25|unisim|vcomponentsibufds_lvds_25_dci|unisim|vcomponentsibufds_lvds_25|unisim|vcomponentsibufds_lvds_33_dci|unisim|vcomponentsibufds_lvds_33|unisim|vcomponentsibufds_lvdsext_25_dci|unisim|vcomponentsibufds_lvdsext_25|unisim|vcomponentsibufds_lvdsext_33_dci|unisim|vcomponentsibufds_lvdsext_33|unisim|vcomponentsibufds_lvpecl_25|unisim|vcomponentsibufds_lvpecl_33|unisim|vcomponentsibufds_ulvds_25|unisim|vcomponentsibufds|unisim|vcomponentsibufg_agp|unisim|vcomponentsibufg_ctt|unisim|vcomponentsibufg_gtl_dci|unisim|vcomponentsibufg_gtlp_dci|unisim|vcomponentsibufg_gtlp|unisim|vcomponentsibufg_gtl|unisim|vcomponentsibufg_hstl_i_18|unisim|vcomponentsibufg_hstl_i_dci_18|unisim|vcomponentsibufg_hstl_i_dci|unisim|vcomponentsibufg_hstl_ii_18|unisim|vcomponentsibufg_hstl_ii_dci_18|unisim|vcomponentsibufg_hstl_ii_dci|unisim|vcomponentsibufg_hstl_iii_18|unisim|vcomponentsibufg_hstl_iii_dci_18|unisim|vcomponentsibufg_hstl_iii_dci|unisim|vcomponentsibufg_hstl_iii|unisim|vcomponentsibufg_hstl_ii|unisim|vcomponentsibufg_hstl_iv_18|unisim|vcomponentsibufg_hstl_iv_dci_18|unisim|vcomponentsibufg_hstl_iv_dci|unisim|vcomponentsibufg_hstl_iv|unisim|vcomponentsibufg_hstl_i|unisim|vcomponentsibufg_lvcmos12|unisim|vcomponentsibufg_lvcmos15|unisim|vcomponentsibufg_lvcmos18|unisim|vcomponentsibufg_lvcmos25|unisim|vcomponentsibufg_lvcmos2|unisim|vcomponentsibufg_lvcmos33|unisim|vcomponentsibufg_lvdci_15|unisim|vcomponentsibufg_lvdci_18|unisim|vcomponentsibufg_lvdci_25|unisim|vcomponentsibufg_lvdci_33|unisim|vcomponentsibufg_lvdci_dv2_15|unisim|vcomponentsibufg_lvdci_dv2_18|unisim|vcomponentsibufg_lvdci_dv2_25|unisim|vcomponentsibufg_lvdci_dv2_33|unisim|vcomponentsibufg_lvds|unisim|vcomponentsibufg_lvpecl|unisim|vcomponentsibufg_lvttl|unisim|vcomponentsibufg_pci33_3|unisim|vcomponentsibufg_pci33_5|unisim|vcomponentsibufg_pci66_3|unisim|vcomponentsibufg_pcix66_3|unisim|vcomponentsibufg_pcix|unisim|vcomponentsibufg_sstl18_i_dci|unisim|vcomponentsibufg_sstl18_ii_dci|unisim|vcomponentsibufg_sstl18_ii|unisim|vcomponentsibufg_sstl18_i|unisim|vcomponentsibufg_sstl2_i_dci|unisim|vcomponentsibufg_sstl2_ii_dci|unisim|vcomponentsibufg_sstl2_ii|unisim|vcomponentsibufg_sstl2_i|unisim|vcomponentsibufg_sstl3_i_dci|unisim|vcomponentsibufg_sstl3_ii_dci|unisim|vcomponentsibufg_sstl3_ii|unisim|vcomponentsibufg_sstl3_i|unisim|vcomponentsibufgds_blvds_25|unisim|vcomponentsibufgds_diff_out|unisim|vcomponentsibufgds_ldt_25|unisim|vcomponentsibufgds_lvds_25_dci|unisim|vcomponentsibufgds_lvds_25|unisim|vcomponentsibufgds_lvds_33_dci|unisim|vcomponentsibufgds_lvds_33|unisim|vcomponentsibufgds_lvdsext_25_dci|unisim|vcomponentsibufgds_lvdsext_25|unisim|vcomponentsibufgds_lvdsext_33_dci|unisim|vcomponentsibufgds_lvdsext_33|unisim|vcomponentsibufgds_lvpecl_25|unisim|vcomponentsibufgds_lvpecl_33|unisim|vcomponentsibufgds_ulvds_25|unisim|vcomponentsibufgds|unisim|vcomponentsibufg|unisim|vcomponentsibuf|unisim|vcomponentsicap_spartan3a|unisim|vcomponentsicap_virtex2|unisim|vcomponentsicap_virtex4|unisim|vcomponentsicap_virtex5|unisim|vcomponentsiddr2|unisim|vcomponentsiddr_2clk|unisim|vcomponentsiddr|unisim|vcomponentsidelayctrl|unisim|vcomponentsidelay|unisim|vcomponentsifddrcpe|unisim|vcomponentsifddrrse|unisim|vcomponentsild|unisim|vcomponentsinv|unisim|vcomponentsiobuf_agp|unisim|vcomponentsiobuf_ctt|unisim|vcomponentsiobuf_f_12|unisim|vcomponentsiobuf_f_16|unisim|vcomponentsiobuf_f_24|unisim|vcomponentsiobuf_f_2|unisim|vcomponentsiobuf_f_4|unisim|vcomponentsiobuf_f_6|unisim|vcomponentsiobuf_f_8|unisim|vcomponentsiobuf_gtl_dci|unisim|vcomponentsiobuf_gtlp_dci|unisim|vcomponentsiobuf_gtlp|unisim|vcomponentsiobuf_gtl|unisim|vcomponentsiobuf_hstl_i_18|unisim|vcomponentsiobuf_hstl_ii_18|unisim|vcomponentsiobuf_hstl_ii_dci_18|unisim|vcomponentsiobuf_hstl_ii_dci|unisim|vcomponentsiobuf_hstl_iii_18|unisim|vcomponentsiobuf_hstl_iii|unisim|vcomponentsiobuf_hstl_ii|unisim|vcomponentsiobuf_hstl_iv_18|unisim|vcomponentsiobuf_hstl_iv_dci_18|unisim|vcomponentsiobuf_hstl_iv_dci|unisim|vcomponentsiobuf_hstl_iv|unisim|vcomponentsiobuf_hstl_i|unisim|vcomponentsiobuf_lvcmos12_f_2|unisim|vcomponentsiobuf_lvcmos12_f_4|unisim|vcomponentsiobuf_lvcmos12_f_6|unisim|vcomponentsiobuf_lvcmos12_f_8|unisim|vcomponentsiobuf_lvcmos12_s_2|unisim|vcomponentsiobuf_lvcmos12_s_4|unisim|vcomponentsiobuf_lvcmos12_s_6|unisim|vcomponentsiobuf_lvcmos12_s_8|unisim|vcomponentsiobuf_lvcmos12|unisim|vcomponentsiobuf_lvcmos15_f_12|unisim|vcomponentsiobuf_lvcmos15_f_16|unisim|vcomponentsiobuf_lvcmos15_f_2|unisim|vcomponentsiobuf_lvcmos15_f_4|unisim|vcomponentsiobuf_lvcmos15_f_6|unisim|vcomponentsiobuf_lvcmos15_f_8|unisim|vcomponentsiobuf_lvcmos15_s_12|unisim|vcomponentsiobuf_lvcmos15_s_16|unisim|vcomponentsiobuf_lvcmos15_s_2|unisim|vcomponentsiobuf_lvcmos15_s_4|unisim|vcomponentsiobuf_lvcmos15_s_6|unisim|vcomponentsiobuf_lvcmos15_s_8|unisim|vcomponentsiobuf_lvcmos15|unisim|vcomponentsiobuf_lvcmos18_f_12|unisim|vcomponentsiobuf_lvcmos18_f_16|unisim|vcomponentsiobuf_lvcmos18_f_2|unisim|vcomponentsiobuf_lvcmos18_f_4|unisim|vcomponentsiobuf_lvcmos18_f_6|unisim|vcomponentsiobuf_lvcmos18_f_8|unisim|vcomponentsiobuf_lvcmos18_s_12|unisim|vcomponentsiobuf_lvcmos18_s_16|unisim|vcomponentsiobuf_lvcmos18_s_2|unisim|vcomponentsiobuf_lvcmos18_s_4|unisim|vcomponentsiobuf_lvcmos18_s_6|unisim|vcomponentsiobuf_lvcmos18_s_8|unisim|vcomponentsiobuf_lvcmos18|unisim|vcomponentsiobuf_lvcmos25_f_12|unisim|vcomponentsiobuf_lvcmos25_f_16|unisim|vcomponentsiobuf_lvcmos25_f_24|unisim|vcomponentsiobuf_lvcmos25_f_2|unisim|vcomponentsiobuf_lvcmos25_f_4|unisim|vcomponentsiobuf_lvcmos25_f_6|unisim|vcomponentsiobuf_lvcmos25_f_8|unisim|vcomponentsiobuf_lvcmos25_s_12|unisim|vcomponentsiobuf_lvcmos25_s_16|unisim|vcomponentsiobuf_lvcmos25_s_24|unisim|vcomponentsiobuf_lvcmos25_s_2|unisim|vcomponentsiobuf_lvcmos25_s_4|unisim|vcomponentsiobuf_lvcmos25_s_6|unisim|vcomponentsiobuf_lvcmos25_s_8|unisim|vcomponentsiobuf_lvcmos25|unisim|vcomponentsiobuf_lvcmos2|unisim|vcomponentsiobuf_lvcmos33_f_12|unisim|vcomponentsiobuf_lvcmos33_f_16|unisim|vcomponentsiobuf_lvcmos33_f_24|unisim|vcomponentsiobuf_lvcmos33_f_2|unisim|vcomponentsiobuf_lvcmos33_f_4|unisim|vcomponentsiobuf_lvcmos33_f_6|unisim|vcomponentsiobuf_lvcmos33_f_8|unisim|vcomponentsiobuf_lvcmos33_s_12|unisim|vcomponentsiobuf_lvcmos33_s_16|unisim|vcomponentsiobuf_lvcmos33_s_24|unisim|vcomponentsiobuf_lvcmos33_s_2|unisim|vcomponentsiobuf_lvcmos33_s_4|unisim|vcomponentsiobuf_lvcmos33_s_6|unisim|vcomponentsiobuf_lvcmos33_s_8|unisim|vcomponentsiobuf_lvcmos33|unisim|vcomponentsiobuf_lvdci_15|unisim|vcomponentsiobuf_lvdci_18|unisim|vcomponentsiobuf_lvdci_25|unisim|vcomponentsiobuf_lvdci_33|unisim|vcomponentsiobuf_lvdci_dv2_15|unisim|vcomponentsiobuf_lvdci_dv2_18|unisim|vcomponentsiobuf_lvdci_dv2_25|unisim|vcomponentsiobuf_lvdci_dv2_33|unisim|vcomponentsiobuf_lvds|unisim|vcomponentsiobuf_lvpecl|unisim|vcomponentsiobuf_lvttl_f_12|unisim|vcomponentsiobuf_lvttl_f_16|unisim|vcomponentsiobuf_lvttl_f_24|unisim|vcomponentsiobuf_lvttl_f_2|unisim|vcomponentsiobuf_lvttl_f_4|unisim|vcomponentsiobuf_lvttl_f_6|unisim|vcomponentsiobuf_lvttl_f_8|unisim|vcomponentsiobuf_lvttl_s_12|unisim|vcomponentsiobuf_lvttl_s_16|unisim|vcomponentsiobuf_lvttl_s_24|unisim|vcomponentsiobuf_lvttl_s_2|unisim|vcomponentsiobuf_lvttl_s_4|unisim|vcomponentsiobuf_lvttl_s_6|unisim|vcomponentsiobuf_lvttl_s_8|unisim|vcomponentsiobuf_lvttl|unisim|vcomponentsiobuf_pci33_3|unisim|vcomponentsiobuf_pci33_5|unisim|vcomponentsiobuf_pci66_3|unisim|vcomponentsiobuf_pcix66_3|unisim|vcomponentsiobuf_pcix|unisim|vcomponentsiobuf_s_12|unisim|vcomponentsiobuf_s_16|unisim|vcomponentsiobuf_s_24|unisim|vcomponentsiobuf_s_2|unisim|vcomponentsiobuf_s_4|unisim|vcomponentsiobuf_s_6|unisim|vcomponentsiobuf_s_8|unisim|vcomponentsiobuf_sstl18_ii_dci|unisim|vcomponentsiobuf_sstl18_ii|unisim|vcomponentsiobuf_sstl18_i|unisim|vcomponentsiobuf_sstl2_ii_dci|unisim|vcomponentsiobuf_sstl2_ii|unisim|vcomponentsiobuf_sstl2_i|unisim|vcomponentsiobuf_sstl3_ii_dci|unisim|vcomponentsiobuf_sstl3_ii|unisim|vcomponentsiobuf_sstl3_i|unisim|vcomponentsiobufds_blvds_25|unisim|vcomponentsiobufds|unisim|vcomponentsiobufe_f|unisim|vcomponentsiobufe_s|unisim|vcomponentsiobufe|unisim|vcomponentsiobuf|unisim|vcomponentsiodelay|unisim|vcomponentsiserdes_nodelay|unisim|vcomponentsiserdes|unisim|vcomponentsjtagppc|unisim|vcomponentskeeper|unisim|vcomponentskeep|unisim|vcomponentskey_clear|unisim|vcomponentsld_1|unisim|vcomponentsldc_1|unisim|vcomponentsldce_1|unisim|vcomponentsldce|unisim|vcomponentsldcp_1|unisim|vcomponentsldcpe_1|unisim|vcomponentsldcpe|unisim|vcomponentsldcp|unisim|vcomponentsldc|unisim|vcomponentslde_1|unisim|vcomponentslde|unisim|vcomponentsldg|unisim|vcomponentsldp_1|unisim|vcomponentsldpe_1|unisim|vcomponentsldpe|unisim|vcomponentsldp|unisim|vcomponentsld|unisim|vcomponentslut1_d|unisim|vcomponentslut1_l|unisim|vcomponentslut1|unisim|vcomponentslut2_d|unisim|vcomponentslut2_l|unisim|vcomponentslut2|unisim|vcomponentslut3_d|unisim|vcomponentslut3_l|unisim|vcomponentslut3|unisim|vcomponentslut4_d|unisim|vcomponentslut4_l|unisim|vcomponentslut4|unisim|vcomponentslut5_d|unisim|vcomponentslut5_l|unisim|vcomponentslut5|unisim|vcomponentslut6_2|unisim|vcomponentslut6_d|unisim|vcomponentslut6_l|unisim|vcomponentslut6|unisim|vcomponentsmerge|unisim|vcomponentsmin_off|unisim|vcomponentsmult18x18sio|unisim|vcomponentsmult18x18s|unisim|vcomponentsmult18x18|unisim|vcomponentsmult_and|unisim|vcomponentsmuxcy_d|unisim|vcomponentsmuxcy_l|unisim|vcomponentsmuxcy|unisim|vcomponentsmuxf5_d|unisim|vcomponentsmuxf5_l|unisim|vcomponentsmuxf5|unisim|vcomponentsmuxf6_d|unisim|vcomponentsmuxf6_l|unisim|vcomponentsmuxf6|unisim|vcomponentsmuxf7_d|unisim|vcomponentsmuxf7_l|unisim|vcomponentsmuxf7|unisim|vcomponentsmuxf8_d|unisim|vcomponentsmuxf8_l|unisim|vcomponentsmuxf8|unisim|vcomponentsnand2b1|unisim|vcomponentsnand2b2|unisim|vcomponentsnand2|unisim|vcomponentsnand3b1|unisim|vcomponentsnand3b2|unisim|vcomponentsnand3b3|unisim|vcomponentsnand3|unisim|vcomponentsnand4b1|unisim|vcomponentsnand4b2|unisim|vcomponentsnand4b3|unisim|vcomponentsnand4b4|unisim|vcomponentsnand4|unisim|vcomponentsnand5b1|unisim|vcomponentsnand5b2|unisim|vcomponentsnand5b3|unisim|vcomponentsnand5b4|unisim|vcomponentsnand5b5|unisim|vcomponentsnand5|unisim|vcomponentsnor2b1|unisim|vcomponentsnor2b2|unisim|vcomponentsnor2|unisim|vcomponentsnor3b1|unisim|vcomponentsnor3b2|unisim|vcomponentsnor3b3|unisim|vcomponentsnor3|unisim|vcomponentsnor4b1|unisim|vcomponentsnor4b2|unisim|vcomponentsnor4b3|unisim|vcomponentsnor4b4|unisim|vcomponentsnor4|unisim|vcomponentsnor5b1|unisim|vcomponentsnor5b2|unisim|vcomponentsnor5b3|unisim|vcomponentsnor5b4|unisim|vcomponentsnor5b5|unisim|vcomponentsnor5|unisim|vcomponentsobuf_agp|unisim|vcomponentsobuf_ctt|unisim|vcomponentsobuf_f_12|unisim|vcomponentsobuf_f_16|unisim|vcomponentsobuf_f_24|unisim|vcomponentsobuf_f_2|unisim|vcomponentsobuf_f_4|unisim|vcomponentsobuf_f_6|unisim|vcomponentsobuf_f_8|unisim|vcomponentsobuf_gtl_dci|unisim|vcomponentsobuf_gtlp_dci|unisim|vcomponentsobuf_gtlp|unisim|vcomponentsobuf_gtl|unisim|vcomponentsobuf_hstl_i_18|unisim|vcomponentsobuf_hstl_i_dci_18|unisim|vcomponentsobuf_hstl_i_dci|unisim|vcomponentsobuf_hstl_ii_18|unisim|vcomponentsobuf_hstl_ii_dci_18|unisim|vcomponentsobuf_hstl_ii_dci|unisim|vcomponentsobuf_hstl_iii_18|unisim|vcomponentsobuf_hstl_iii_dci_18|unisim|vcomponentsobuf_hstl_iii_dci|unisim|vcomponentsobuf_hstl_iii|unisim|vcomponentsobuf_hstl_ii|unisim|vcomponentsobuf_hstl_iv_18|unisim|vcomponentsobuf_hstl_iv_dci_18|unisim|vcomponentsobuf_hstl_iv_dci|unisim|vcomponentsobuf_hstl_iv|unisim|vcomponentsobuf_hstl_i|unisim|vcomponentsobuf_lvcmos12_f_2|unisim|vcomponentsobuf_lvcmos12_f_4|unisim|vcomponentsobuf_lvcmos12_f_6|unisim|vcomponentsobuf_lvcmos12_f_8|unisim|vcomponentsobuf_lvcmos12_s_2|unisim|vcomponentsobuf_lvcmos12_s_4|unisim|vcomponentsobuf_lvcmos12_s_6|unisim|vcomponentsobuf_lvcmos12_s_8|unisim|vcomponentsobuf_lvcmos12|unisim|vcomponentsobuf_lvcmos15_f_12|unisim|vcomponentsobuf_lvcmos15_f_16|unisim|vcomponentsobuf_lvcmos15_f_2|unisim|vcomponentsobuf_lvcmos15_f_4|unisim|vcomponentsobuf_lvcmos15_f_6|unisim|vcomponentsobuf_lvcmos15_f_8|unisim|vcomponentsobuf_lvcmos15_s_12|unisim|vcomponentsobuf_lvcmos15_s_16|unisim|vcomponentsobuf_lvcmos15_s_2|unisim|vcomponentsobuf_lvcmos15_s_4|unisim|vcomponentsobuf_lvcmos15_s_6|unisim|vcomponentsobuf_lvcmos15_s_8|unisim|vcomponentsobuf_lvcmos15|unisim|vcomponentsobuf_lvcmos18_f_12|unisim|vcomponentsobuf_lvcmos18_f_16|unisim|vcomponentsobuf_lvcmos18_f_2|unisim|vcomponentsobuf_lvcmos18_f_4|unisim|vcomponentsobuf_lvcmos18_f_6|unisim|vcomponentsobuf_lvcmos18_f_8|unisim|vcomponentsobuf_lvcmos18_s_12|unisim|vcomponentsobuf_lvcmos18_s_16|unisim|vcomponentsobuf_lvcmos18_s_2|unisim|vcomponentsobuf_lvcmos18_s_4|unisim|vcomponentsobuf_lvcmos18_s_6|unisim|vcomponentsobuf_lvcmos18_s_8|unisim|vcomponentsobuf_lvcmos18|unisim|vcomponentsobuf_lvcmos25_f_12|unisim|vcomponentsobuf_lvcmos25_f_16|unisim|vcomponentsobuf_lvcmos25_f_24|unisim|vcomponentsobuf_lvcmos25_f_2|unisim|vcomponentsobuf_lvcmos25_f_4|unisim|vcomponentsobuf_lvcmos25_f_6|unisim|vcomponentsobuf_lvcmos25_f_8|unisim|vcomponentsobuf_lvcmos25_s_12|unisim|vcomponentsobuf_lvcmos25_s_16|unisim|vcomponentsobuf_lvcmos25_s_24|unisim|vcomponentsobuf_lvcmos25_s_2|unisim|vcomponentsobuf_lvcmos25_s_4|unisim|vcomponentsobuf_lvcmos25_s_6|unisim|vcomponentsobuf_lvcmos25_s_8|unisim|vcomponentsobuf_lvcmos25|unisim|vcomponentsobuf_lvcmos2|unisim|vcomponentsobuf_lvcmos33_f_12|unisim|vcomponentsobuf_lvcmos33_f_16|unisim|vcomponentsobuf_lvcmos33_f_24|unisim|vcomponentsobuf_lvcmos33_f_2|unisim|vcomponentsobuf_lvcmos33_f_4|unisim|vcomponentsobuf_lvcmos33_f_6|unisim|vcomponentsobuf_lvcmos33_f_8|unisim|vcomponentsobuf_lvcmos33_s_12|unisim|vcomponentsobuf_lvcmos33_s_16|unisim|vcomponentsobuf_lvcmos33_s_24|unisim|vcomponentsobuf_lvcmos33_s_2|unisim|vcomponentsobuf_lvcmos33_s_4|unisim|vcomponentsobuf_lvcmos33_s_6|unisim|vcomponentsobuf_lvcmos33_s_8|unisim|vcomponentsobuf_lvcmos33|unisim|vcomponentsobuf_lvdci_15|unisim|vcomponentsobuf_lvdci_18|unisim|vcomponentsobuf_lvdci_25|unisim|vcomponentsobuf_lvdci_33|unisim|vcomponentsobuf_lvdci_dv2_15|unisim|vcomponentsobuf_lvdci_dv2_18|unisim|vcomponentsobuf_lvdci_dv2_25|unisim|vcomponentsobuf_lvdci_dv2_33|unisim|vcomponentsobuf_lvds|unisim|vcomponentsobuf_lvpecl|unisim|vcomponentsobuf_lvttl_f_12|unisim|vcomponentsobuf_lvttl_f_16|unisim|vcomponentsobuf_lvttl_f_24|unisim|vcomponentsobuf_lvttl_f_2|unisim|vcomponentsobuf_lvttl_f_4|unisim|vcomponentsobuf_lvttl_f_6|unisim|vcomponentsobuf_lvttl_f_8|unisim|vcomponentsobuf_lvttl_s_12|unisim|vcomponentsobuf_lvttl_s_16|unisim|vcomponentsobuf_lvttl_s_24|unisim|vcomponentsobuf_lvttl_s_2|unisim|vcomponentsobuf_lvttl_s_4|unisim|vcomponentsobuf_lvttl_s_6|unisim|vcomponentsobuf_lvttl_s_8|unisim|vcomponentsobuf_lvttl|unisim|vcomponentsobuf_pci33_3|unisim|vcomponentsobuf_pci33_5|unisim|vcomponentsobuf_pci66_3|unisim|vcomponentsobuf_pcix66_3|unisim|vcomponentsobuf_pcix|unisim|vcomponentsobuf_s_12|unisim|vcomponentsobuf_s_16|unisim|vcomponentsobuf_s_24|unisim|vcomponentsobuf_s_2|unisim|vcomponentsobuf_s_4|unisim|vcomponentsobuf_s_6|unisim|vcomponentsobuf_s_8|unisim|vcomponentsobuf_sstl18_i_dci|unisim|vcomponentsobuf_sstl18_ii_dci|unisim|vcomponentsobuf_sstl18_ii|unisim|vcomponentsobuf_sstl18_i|unisim|vcomponentsobuf_sstl2_i_dci|unisim|vcomponentsobuf_sstl2_ii_dci|unisim|vcomponentsobuf_sstl2_ii|unisim|vcomponentsobuf_sstl2_i|unisim|vcomponentsobuf_sstl3_i_dci|unisim|vcomponentsobuf_sstl3_ii_dci|unisim|vcomponentsobuf_sstl3_ii|unisim|vcomponentsobuf_sstl3_i|unisim|vcomponentsobufds_blvds_25|unisim|vcomponentsobufds_ldt_25|unisim|vcomponentsobufds_lvds_25|unisim|vcomponentsobufds_lvds_33|unisim|vcomponentsobufds_lvdsext_25|unisim|vcomponentsobufds_lvdsext_33|unisim|vcomponentsobufds_lvpecl_25|unisim|vcomponentsobufds_lvpecl_33|unisim|vcomponentsobufds_ulvds_25|unisim|vcomponentsobufds|unisim|vcomponentsobufe|unisim|vcomponentsobuft_agp|unisim|vcomponentsobuft_ctt|unisim|vcomponentsobuft_f_12|unisim|vcomponentsobuft_f_16|unisim|vcomponentsobuft_f_24|unisim|vcomponentsobuft_f_2|unisim|vcomponentsobuft_f_4|unisim|vcomponentsobuft_f_6|unisim|vcomponentsobuft_f_8|unisim|vcomponentsobuft_gtl_dci|unisim|vcomponentsobuft_gtlp_dci|unisim|vcomponentsobuft_gtlp|unisim|vcomponentsobuft_gtl|unisim|vcomponentsobuft_hstl_i_18|unisim|vcomponentsobuft_hstl_i_dci_18|unisim|vcomponentsobuft_hstl_i_dci|unisim|vcomponentsobuft_hstl_ii_18|unisim|vcomponentsobuft_hstl_ii_dci_18|unisim|vcomponentsobuft_hstl_ii_dci|unisim|vcomponentsobuft_hstl_iii_18|unisim|vcomponentsobuft_hstl_iii_dci_18|unisim|vcomponentsobuft_hstl_iii_dci|unisim|vcomponentsobuft_hstl_iii|unisim|vcomponentsobuft_hstl_ii|unisim|vcomponentsobuft_hstl_iv_18|unisim|vcomponentsobuft_hstl_iv_dci_18|unisim|vcomponentsobuft_hstl_iv_dci|unisim|vcomponentsobuft_hstl_iv|unisim|vcomponentsobuft_hstl_i|unisim|vcomponentsobuft_lvcmos12_f_2|unisim|vcomponentsobuft_lvcmos12_f_4|unisim|vcomponentsobuft_lvcmos12_f_6|unisim|vcomponentsobuft_lvcmos12_f_8|unisim|vcomponentsobuft_lvcmos12_s_2|unisim|vcomponentsobuft_lvcmos12_s_4|unisim|vcomponentsobuft_lvcmos12_s_6|unisim|vcomponentsobuft_lvcmos12_s_8|unisim|vcomponentsobuft_lvcmos12|unisim|vcomponentsobuft_lvcmos15_f_12|unisim|vcomponentsobuft_lvcmos15_f_16|unisim|vcomponentsobuft_lvcmos15_f_2|unisim|vcomponentsobuft_lvcmos15_f_4|unisim|vcomponentsobuft_lvcmos15_f_6|unisim|vcomponentsobuft_lvcmos15_f_8|unisim|vcomponentsobuft_lvcmos15_s_12|unisim|vcomponentsobuft_lvcmos15_s_16|unisim|vcomponentsobuft_lvcmos15_s_2|unisim|vcomponentsobuft_lvcmos15_s_4|unisim|vcomponentsobuft_lvcmos15_s_6|unisim|vcomponentsobuft_lvcmos15_s_8|unisim|vcomponentsobuft_lvcmos15|unisim|vcomponentsobuft_lvcmos18_f_12|unisim|vcomponentsobuft_lvcmos18_f_16|unisim|vcomponentsobuft_lvcmos18_f_2|unisim|vcomponentsobuft_lvcmos18_f_4|unisim|vcomponentsobuft_lvcmos18_f_6|unisim|vcomponentsobuft_lvcmos18_f_8|unisim|vcomponentsobuft_lvcmos18_s_12|unisim|vcomponentsobuft_lvcmos18_s_16|unisim|vcomponentsobuft_lvcmos18_s_2|unisim|vcomponentsobuft_lvcmos18_s_4|unisim|vcomponentsobuft_lvcmos18_s_6|unisim|vcomponentsobuft_lvcmos18_s_8|unisim|vcomponentsobuft_lvcmos18|unisim|vcomponentsobuft_lvcmos25_f_12|unisim|vcomponentsobuft_lvcmos25_f_16|unisim|vcomponentsobuft_lvcmos25_f_24|unisim|vcomponentsobuft_lvcmos25_f_2|unisim|vcomponentsobuft_lvcmos25_f_4|unisim|vcomponentsobuft_lvcmos25_f_6|unisim|vcomponentsobuft_lvcmos25_f_8|unisim|vcomponentsobuft_lvcmos25_s_12|unisim|vcomponentsobuft_lvcmos25_s_16|unisim|vcomponentsobuft_lvcmos25_s_24|unisim|vcomponentsobuft_lvcmos25_s_2|unisim|vcomponentsobuft_lvcmos25_s_4|unisim|vcomponentsobuft_lvcmos25_s_6|unisim|vcomponentsobuft_lvcmos25_s_8|unisim|vcomponentsobuft_lvcmos25|unisim|vcomponentsobuft_lvcmos2|unisim|vcomponentsobuft_lvcmos33_f_12|unisim|vcomponentsobuft_lvcmos33_f_16|unisim|vcomponentsobuft_lvcmos33_f_24|unisim|vcomponentsobuft_lvcmos33_f_2|unisim|vcomponentsobuft_lvcmos33_f_4|unisim|vcomponentsobuft_lvcmos33_f_6|unisim|vcomponentsobuft_lvcmos33_f_8|unisim|vcomponentsobuft_lvcmos33_s_12|unisim|vcomponentsobuft_lvcmos33_s_16|unisim|vcomponentsobuft_lvcmos33_s_24|unisim|vcomponentsobuft_lvcmos33_s_2|unisim|vcomponentsobuft_lvcmos33_s_4|unisim|vcomponentsobuft_lvcmos33_s_6|unisim|vcomponentsobuft_lvcmos33_s_8|unisim|vcomponentsobuft_lvcmos33|unisim|vcomponentsobuft_lvdci_15|unisim|vcomponentsobuft_lvdci_18|unisim|vcomponentsobuft_lvdci_25|unisim|vcomponentsobuft_lvdci_33|unisim|vcomponentsobuft_lvdci_dv2_15|unisim|vcomponentsobuft_lvdci_dv2_18|unisim|vcomponentsobuft_lvdci_dv2_25|unisim|vcomponentsobuft_lvdci_dv2_33|unisim|vcomponentsobuft_lvds|unisim|vcomponentsobuft_lvpecl|unisim|vcomponentsobuft_lvttl_f_12|unisim|vcomponentsobuft_lvttl_f_16|unisim|vcomponentsobuft_lvttl_f_24|unisim|vcomponentsobuft_lvttl_f_2|unisim|vcomponentsobuft_lvttl_f_4|unisim|vcomponentsobuft_lvttl_f_6|unisim|vcomponentsobuft_lvttl_f_8|unisim|vcomponentsobuft_lvttl_s_12|unisim|vcomponentsobuft_lvttl_s_16|unisim|vcomponentsobuft_lvttl_s_24|unisim|vcomponentsobuft_lvttl_s_2|unisim|vcomponentsobuft_lvttl_s_4|unisim|vcomponentsobuft_lvttl_s_6|unisim|vcomponentsobuft_lvttl_s_8|unisim|vcomponentsobuft_lvttl|unisim|vcomponentsobuft_pci33_3|unisim|vcomponentsobuft_pci33_5|unisim|vcomponentsobuft_pci66_3|unisim|vcomponentsobuft_pcix66_3|unisim|vcomponentsobuft_pcix|unisim|vcomponentsobuft_s_12|unisim|vcomponentsobuft_s_16|unisim|vcomponentsobuft_s_24|unisim|vcomponentsobuft_s_2|unisim|vcomponentsobuft_s_4|unisim|vcomponentsobuft_s_6|unisim|vcomponentsobuft_s_8|unisim|vcomponentsobuft_sstl18_i_dci|unisim|vcomponentsobuft_sstl18_ii_dci|unisim|vcomponentsobuft_sstl18_ii|unisim|vcomponentsobuft_sstl18_i|unisim|vcomponentsobuft_sstl2_i_dci|unisim|vcomponentsobuft_sstl2_ii_dci|unisim|vcomponentsobuft_sstl2_ii|unisim|vcomponentsobuft_sstl2_i|unisim|vcomponentsobuft_sstl3_i_dci|unisim|vcomponentsobuft_sstl3_ii_dci|unisim|vcomponentsobuft_sstl3_ii|unisim|vcomponentsobuft_sstl3_i|unisim|vcomponentsobuftds_blvds_25|unisim|vcomponentsobuftds_ldt_25|unisim|vcomponentsobuftds_lvds_25|unisim|vcomponentsobuftds_lvds_33|unisim|vcomponentsobuftds_lvdsext_25|unisim|vcomponentsobuftds_lvdsext_33|unisim|vcomponentsobuftds_lvpecl_25|unisim|vcomponentsobuftds_lvpecl_33|unisim|vcomponentsobuftds_ulvds_25|unisim|vcomponentsobuftds|unisim|vcomponentsobuft|unisim|vcomponentsobuf|unisim|vcomponentsoddr2|unisim|vcomponentsoddr|unisim|vcomponentsofddrcpe|unisim|vcomponentsofddrrse|unisim|vcomponentsofddrtcpe|unisim|vcomponentsofddrtrse|unisim|vcomponentsopt_off|unisim|vcomponentsopt_uim|unisim|vcomponentsor2b1|unisim|vcomponentsor2b2|unisim|vcomponentsor2|unisim|vcomponentsor3b1|unisim|vcomponentsor3b2|unisim|vcomponentsor3b3|unisim|vcomponentsor3|unisim|vcomponentsor4b1|unisim|vcomponentsor4b2|unisim|vcomponentsor4b3|unisim|vcomponentsor4b4|unisim|vcomponentsor4|unisim|vcomponentsor5b1|unisim|vcomponentsor5b2|unisim|vcomponentsor5b3|unisim|vcomponentsor5b4|unisim|vcomponentsor5b5|unisim|vcomponentsor5|unisim|vcomponentsor6|unisim|vcomponentsor7|unisim|vcomponentsor8|unisim|vcomponentsorcy|unisim|vcomponentsoserdes|unisim|vcomponentspcie_ep|unisim|vcomponentspcie_internal_1_1|unisim|vcomponentspll_adv|unisim|vcomponentspll_base|unisim|vcomponentspmcd|unisim|vcomponentsppc405_adv|unisim|vcomponentsppc405|unisim|vcomponentspulldown|unisim|vcomponentspullup|unisim|vcomponentsram128x1d|unisim|vcomponentsram128x1s_1|unisim|vcomponentsram128x1s|unisim|vcomponentsram16x1d_1|unisim|vcomponentsram16x1d|unisim|vcomponentsram16x1s_1|unisim|vcomponentsram16x1s|unisim|vcomponentsram16x2s|unisim|vcomponentsram16x4s|unisim|vcomponentsram16x8s|unisim|vcomponentsram256x1s|unisim|vcomponentsram32m|unisim|vcomponentsram32x1d_1|unisim|vcomponentsram32x1d|unisim|vcomponentsram32x1s_1|unisim|vcomponentsram32x1s|unisim|vcomponentsram32x2s|unisim|vcomponentsram32x4s|unisim|vcomponentsram32x8s|unisim|vcomponentsram64m|unisim|vcomponentsram64x1d_1|unisim|vcomponentsram64x1d|unisim|vcomponentsram64x1s_1|unisim|vcomponentsram64x1s|unisim|vcomponentsram64x2s|unisim|vcomponentsramb16_s18_s18|unisim|vcomponentsramb16_s18_s36|unisim|vcomponentsramb16_s18|unisim|vcomponentsramb16_s1_s18|unisim|vcomponentsramb16_s1_s1|unisim|vcomponentsramb16_s1_s2|unisim|vcomponentsramb16_s1_s36|unisim|vcomponentsramb16_s1_s4|unisim|vcomponentsramb16_s1_s9|unisim|vcomponentsramb16_s1|unisim|vcomponentsramb16_s2_s18|unisim|vcomponentsramb16_s2_s2|unisim|vcomponentsramb16_s2_s36|unisim|vcomponentsramb16_s2_s4|unisim|vcomponentsramb16_s2_s9|unisim|vcomponentsramb16_s2|unisim|vcomponentsramb16_s36_s36|unisim|vcomponentsramb16_s36|unisim|vcomponentsramb16_s4_s18|unisim|vcomponentsramb16_s4_s36|unisim|vcomponentsramb16_s4_s4|unisim|vcomponentsramb16_s4_s9|unisim|vcomponentsramb16_s4|unisim|vcomponentsramb16_s9_s18|unisim|vcomponentsramb16_s9_s36|unisim|vcomponentsramb16_s9_s9|unisim|vcomponentsramb16_s9|unisim|vcomponentsramb16bwe_s18_s18|unisim|vcomponentsramb16bwe_s18_s9|unisim|vcomponentsramb16bwe_s18|unisim|vcomponentsramb16bwe_s36_s18|unisim|vcomponentsramb16bwe_s36_s36|unisim|vcomponentsramb16bwe_s36_s9|unisim|vcomponentsramb16bwe_s36|unisim|vcomponentsramb16bwer|unisim|vcomponentsramb16bwe|unisim|vcomponentsramb16|unisim|vcomponentsramb18sdp|unisim|vcomponentsramb18|unisim|vcomponentsramb32_s64_ecc|unisim|vcomponentsramb36_exp|unisim|vcomponentsramb36sdp_exp|unisim|vcomponentsramb36sdp|unisim|vcomponentsramb36|unisim|vcomponentsramb4_s16_s16|unisim|vcomponentsramb4_s16|unisim|vcomponentsramb4_s1_s16|unisim|vcomponentsramb4_s1_s1|unisim|vcomponentsramb4_s1_s2|unisim|vcomponentsramb4_s1_s4|unisim|vcomponentsramb4_s1_s8|unisim|vcomponentsramb4_s1|unisim|vcomponentsramb4_s2_s16|unisim|vcomponentsramb4_s2_s2|unisim|vcomponentsramb4_s2_s4|unisim|vcomponentsramb4_s2_s8|unisim|vcomponentsramb4_s2|unisim|vcomponentsramb4_s4_s16|unisim|vcomponentsramb4_s4_s4|unisim|vcomponentsramb4_s4_s8|unisim|vcomponentsramb4_s4|unisim|vcomponentsramb4_s8_s16|unisim|vcomponentsramb4_s8_s8|unisim|vcomponentsramb4_s8|unisim|vcomponentsrocbuf|unisim|vcomponentsroc|unisim|vcomponentsrom128x1|unisim|vcomponentsrom16x1|unisim|vcomponentsrom256x1|unisim|vcomponentsrom32x1|unisim|vcomponentsrom64x1|unisim|vcomponentsspi_access|unisim|vcomponentssrl16_1|unisim|vcomponentssrl16e_1|unisim|vcomponentssrl16e|unisim|vcomponentssrl16|unisim|vcomponentssrlc16_1|unisim|vcomponentssrlc16e_1|unisim|vcomponentssrlc16e|unisim|vcomponentssrlc16|unisim|vcomponentssrlc32e|unisim|vcomponentsstartbuf_fpgacore|unisim|vcomponentsstartbuf_spartan2|unisim|vcomponentsstartbuf_spartan3|unisim|vcomponentsstartbuf_virtex2|unisim|vcomponentsstartbuf_virtex4|unisim|vcomponentsstartbuf_virtex|unisim|vcomponentsstartup_fpgacore|unisim|vcomponentsstartup_spartan2|unisim|vcomponentsstartup_spartan3a|unisim|vcomponentsstartup_spartan3e|unisim|vcomponentsstartup_spartan3|unisim|vcomponentsstartup_virtex2|unisim|vcomponentsstartup_virtex4|unisim|vcomponentsstartup_virtex5|unisim|vcomponentsstartup_virtex|unisim|vcomponentssysmon|unisim|vcomponentstblock|unisim|vcomponentstemac|unisim|vcomponentstimegrp|unisim|vcomponentstimespec|unisim|vcomponentstocbuf|unisim|vcomponentstoc|unisim|vcomponentsusr_access_virtex4|unisim|vcomponentsusr_access_virtex5|unisim|vcomponentsvcc|unisim|vcomponentswireand|unisim|vcomponentsxnor2|unisim|vcomponentsxnor3|unisim|vcomponentsxnor4|unisim|vcomponentsxnor5|unisim|vcomponentsxor2|unisim|vcomponentsxor3|unisim|vcomponentsxor4|unisim|vcomponentsxor5|unisim|vcomponentsxorcy_d|unisim|vcomponentsxorcy_l|unisim|vcomponentsxorcy|unisim|vcomponents****PROP_DevFamilyPMName=aspartan3********PROP_Parse_Target=synthesis********PROP_DevFamilyPMName=spartan3e********PROP_Parse_Target=synthesis********PROP_Parse_Target=synthesis****PROP_Parse_TargetsynthesisPROP_DevFamilyPMNamespartan3ePROP_DevFamilyAutomotive CoolRunner2Spartan3EPROP_Dummydum1CoolRunner XPLA3 CPLDsXC9500XV CPLDsXC9500XL CPLDsXC9500 CPLDsCoolRunner2 CPLDsAutomotive 9500XLVirtexEVirtex2PVirtex2VirtexSpartan-3A DSPSpartan3A and Spartan3ANSpartan3Spartan2ESpartan2QPro VirtexE MilitaryQPro Virtex Hi-RelQPro Virtex Rad-HardAutomotive Spartan3EAutomotive Spartan3Automotive Spartan2EPROP_xstVeriIncludeDir_GlobalPLUGIN_EdifPLUGIN_GeneralPLUGIN_NcdPLUGIN_VerilogPLUGIN_VhdllibHdlaspartan3|File||/home/andi/xilinx/diogenes/vhdl/mysio.stx|PLUGIN_General|1201550702|FILE_XST_STX|Generic||mysio.stxmysio.stxDESUT_XST_STX|File||/home/andi/xilinx/diogenes/vhdl/video_ram.vho|PLUGIN_General|1201547406|FILE_VHO|Generic||video_ram.vhovideo_ram.vhoDESUT_XCO_MISC|File||/home/andi/xilinx/diogenes/vhdl/video_ram.vhd|PLUGIN_Vhdl|1201547402|FILE_VHDL|Architecture||video_ram_a|video_ram|||Entity||video_ram|Library||||Use||ieee|std_logic_1164|all|video_ram_avideo_ramDESUT_VHDL_ARCHITECTUREDESUT_VHDL_ENTITYieee.std_logic_1164.allieeestd_logic_1164all|ComponentInstantiation||video_ram|video_ram_a|U0|wrapped_video_ram|U0wrapped_video_ramXilinxCoreLib|File||/home/andi/xilinx/diogenes/vhdl/video_ram.xco|PLUGIN_SingleModule|1201547410|PLUGIN_SingleModuleFILE_COREGEN|Module||video_ramDESUT_XCOTBIND_regenerateCoreTRAN_regenerateCoreTBIND_coreManageTRAN_coreManage|File||/home/andi/xilinx/diogenes/vhdl/video_ram.ngc|PLUGIN_NGC|1201547398|PLUGIN_NGCFILE_NGCDESUT_NGC3s500efg320-4|File||/home/andi/xilinx/diogenes/vhdl/vga/vga.vhdl|PLUGIN_Vhdl|1200747884||Architecture||Behavioral|vga|||ComponentInstantiation||vga|Behavioral|video_ram_c|video_ram||Entity||vga|Use||IEEE|STD_LOGIC_1164|all||Use||IEEE|STD_LOGIC_ARITH|all||Use||IEEE|STD_LOGIC_UNSIGNED|all|Behavioralvgavideo_ram_cIEEE.STD_LOGIC_UNSIGNED.allIEEESTD_LOGIC_UNSIGNEDIEEE.STD_LOGIC_ARITH.allSTD_LOGIC_ARITHIEEE.STD_LOGIC_1164.allSTD_LOGIC_1164|File||/home/andi/xilinx/diogenes/vhdl/_xmsgs/bitgen.xmsgs|PLUGIN_General|1201550790|FILE_XMSGS|Generic||bitgen.xmsgsbitgen.xmsgsDESUT_XMSGS|File||/home/andi/xilinx/diogenes/vhdl/mysio.bgn|PLUGIN_General|1201550788|FILE_BITGEN_REPORT|Generic||mysio.bgnmysio.bgnDESUT_BITGEN_REPORT|File||/home/andi/xilinx/diogenes/vhdl/mysio.bit|PLUGIN_General|1201550788|FILE_BIT|Generic||mysio.bitmysio.bitDESUT_BIT|File||/home/andi/xilinx/diogenes/vhdl/mysio.drc|PLUGIN_General|1201550780|FILE_BITGEN_DRC|Generic||mysio.drcmysio.drcDESUT_BITGEN_DRC|File||/home/andi/xilinx/diogenes/vhdl/coregen.log|PLUGIN_General|1200510094|FILE_LOG|File||/home/andi/xilinx/diogenes/vhdl/sio_testbench_isim_beh.exe|PLUGIN_General|1200510094|FILE_ISIM_EXE|File||/home/andi/xilinx/diogenes/vhdl/sio_testbench_beh.prj|PLUGIN_General|1200510094|FILE_XST_PROJECT|Generic||sio_testbench_beh.prjsio_testbench_beh.prjDESUT_XST_PROJECT|File||/home/andi/xilinx/diogenes/vhdl/sio_testbench_isim_par.exe|PLUGIN_General|1200510092||File||/home/andi/xilinx/diogenes/vhdl/sio_testbench_par.prj|PLUGIN_General|1200510092||Generic||sio_testbench_par.prjsio_testbench_par.prj|File||/home/andi/xilinx/diogenes/vhdl/netgen|PLUGIN_General|1200510094|FILE_DIRECTORY|File||/home/andi/xilinx/diogenes/vhdl/netgen/par/mysio_timesim.sdf|PLUGIN_General|1200510094|FILE_SDF|File||/home/andi/xilinx/diogenes/vhdl/netgen/par/mysio_timesim.vhd|PLUGIN_Vhdl|1200510094||File||/home/andi/xilinx/diogenes/vhdl/netgen/par/mysio_timesim.nlf|PLUGIN_General|1200510094|FILE_NETGEN_REPORT|File||/home/andi/xilinx/diogenes/vhdl/cpu/barrel.vhd|PLUGIN_Vhdl|1200510094||Architecture||Behavioral|barrel|||Entity||barrelbarrel|File||/home/andi/xilinx/diogenes/vhdl/mysio_map.ngm|PLUGIN_NGM|1201550718|PLUGIN_NGMFILE_NGM|Module||mysiomysioDESUT_NGM|File||/home/andi/xilinx/diogenes/vhdl/mysio.pcf|PLUGIN_General|1201550720|FILE_PCF|Generic||mysio.pcfmysio.pcfDESUT_PCF|File||/home/andi/xilinx/diogenes/vhdl/mysio_map.ncd|PLUGIN_NCD|1201550722|PLUGIN_NCDFILE_NCDDESUT_NCD|File||/home/andi/xilinx/diogenes/vhdl/cpu_stx.prj|PLUGIN_General|1200510092||Generic||cpu_stx.prjcpu_stx.prj|File||/home/andi/xilinx/diogenes/vhdl/cpu/pmem.vho|PLUGIN_General|1200510096||Generic||pmem.vhopmem.vho|File||/home/andi/xilinx/diogenes/vhdl/cpu/pmem.sym|PLUGIN_General|1200510096|FILE_SYMBOL|Generic||pmem.sympmem.symDESUT_SYMBOL|File||/home/andi/xilinx/diogenes/vhdl/cpu/pmem.asy|PLUGIN_General|1200510096|FILE_ASY|Generic||pmem.asypmem.asy|File||/home/andi/xilinx/diogenes/vhdl/cpu/pmem.vhd|PLUGIN_Vhdl|1200510094||Architecture||pmem_a|pmem|||Entity||pmempmem_apmem|ComponentInstantiation||pmem|pmem_a|U0|wrapped_pmem|wrapped_pmem|File||/home/andi/xilinx/diogenes/vhdl/cpu/pmem.xco|PLUGIN_SingleModule|1200510096||Module||pmem|File||/home/andi/xilinx/diogenes/vhdl/mysio.ngr|PLUGIN_NGR|1201550666|PLUGIN_NGRFILE_NGRDESUT_NGR|File||/home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.vho|PLUGIN_General|1200510096||Generic||dist_mem.vhodist_mem.vho|File||/home/andi/xilinx/diogenes/vhdl/cpu/pmem.ngc|PLUGIN_NGC|1200510096|3s500efg320-5|File||/home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.ngc|PLUGIN_NGC|1200510096||Module||dist_memdist_mem3s100evq100-5|File||/home/andi/xilinx/diogenes/vhdl/pmem_readme.txt|PLUGIN_General|1200510096|FILE_USERDOC|File||/home/andi/xilinx/diogenes/vhdl/pmem.vho|PLUGIN_General|1200510096||File||/home/andi/xilinx/diogenes/vhdl/pmem.sym|PLUGIN_General|1200510096||File||/home/andi/xilinx/diogenes/vhdl/pmem.asy|PLUGIN_General|1200510096||File||/home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.xco|PLUGIN_SingleModule|1200510096||File||/home/andi/xilinx/diogenes/vhdl/cpu/dist_mem.vhd|PLUGIN_Vhdl|1200510096||Architecture||dist_mem_a|dist_mem|||Entity||dist_memdist_mem_a|ComponentInstantiation||dist_mem|dist_mem_a|U0|wrapped_dist_mem|wrapped_dist_mem|File||/home/andi/xilinx/diogenes/vhdl/mysio.sym|PLUGIN_General|1200510094||Generic||mysio.symmysio.sym|File||/home/andi/xilinx/diogenes/vhdl/mysio.twx|PLUGIN_General|1201550776|FILE_TIMING_XML_REPORT|Generic||mysio.twxmysio.twxDESUT_TIMING_XML_REPORT|File||/home/andi/xilinx/diogenes/vhdl/mysio.twr|PLUGIN_General|1201550776|FILE_TIMING_TXT_REPORT|Generic||mysio.twrmysio.twrDESUT_TIMING_TXT_REPORT|File||/home/andi/xilinx/diogenes/vhdl/mysio_pad.csv|PLUGIN_General|1201550770|FILE_PAD_EXCEL_REPORT|Generic||mysio_pad.csvmysio_pad.csvDESUT_PAD_EXCEL_REPORT|File||/home/andi/xilinx/diogenes/vhdl/mysio_pad.txt|PLUGIN_General|1201550770|FILE_PAD_TXT_REPORT|Generic||mysio_pad.txtmysio_pad.txtDESUT_PAD_TXT_REPORTTBIND_viewPadRptsTRAN_viewPadRpts|File||/home/andi/xilinx/diogenes/vhdl/mysio.xpi|PLUGIN_General|1201550770|FILE_XPI|Generic||mysio.xpimysio.xpiDESUT_XPI|File||/home/andi/xilinx/diogenes/vhdl/mysio.unroutes|PLUGIN_General|1201550770|FILE_UNROUTES|Generic||mysio.unroutesmysio.unroutesDESUT_UNROUTES|File||/home/andi/xilinx/diogenes/vhdl/mysio.par|PLUGIN_General|1201550770|FILE_PAR_REPORT|Generic||mysio.parmysio.parDESUT_PAR_REPORTTBIND_viewParRptsTRAN_viewParRpts|File||/home/andi/xilinx/diogenes/vhdl/mysio.pad|PLUGIN_General|1201550770|FILE_PAD_MISC|Generic||mysio.padmysio.padDESUT_PAD_MISC|File||/home/andi/xilinx/diogenes/vhdl/mysio.ncd|PLUGIN_NCD|1201550770||File||/home/andi/xilinx/diogenes/vhdl/mysio_guide.ncd|PLUGIN_NCD|1201550770||File||/home/andi/xilinx/diogenes/vhdl/mysio_usage.xml|PLUGIN_General|1201550788|FILE_WEBTALK|Generic||mysio_usage.xmlmysio_usage.xmlDESUT_GENERIC|File||/home/andi/xilinx/diogenes/vhdl/mysio_map.mrp|PLUGIN_General|1201550722|FILE_MAP_REPORT|Generic||mysio_map.mrpmysio_map.mrpDESUT_MAP_REPORT|File||/home/andi/xilinx/diogenes/vhdl/mysio.ngd|PLUGIN_NGD|1201550710|PLUGIN_NGDFILE_NGDDESUT_NGD|File||/home/andi/xilinx/diogenes/vhdl/cpu/dmem.vhd|PLUGIN_Vhdl|1200510094||Architecture||dmem_a|dmem|||Entity||dmemdmem_admem|ComponentInstantiation||dmem|dmem_a|U0|wrapped_dmem|wrapped_dmem|File||/home/andi/xilinx/diogenes/vhdl/mysio.bld|PLUGIN_General|1201550710|FILE_NGDBUILD_LOG|Generic||mysio.bldmysio.bldDESUT_NGDBUILD_LOG|File||/home/andi/xilinx/diogenes/vhdl/pmem.vhd|PLUGIN_Vhdl|1201550702||File||/home/andi/xilinx/diogenes/vhdl/mysio.ngc|PLUGIN_NGC|1201550702|xc3s500e-4-fg320|File||/home/andi/xilinx/diogenes/vhdl/mysio.cmd_log|PLUGIN_General|1201550778|FILE_CMD_LOG|Generic||mysio.cmd_logmysio.cmd_logDESUT_CMD_LOG|File||/home/andi/xilinx/diogenes/vhdl/mysio.prj|PLUGIN_General|1201550654||Generic||mysio.prjmysio.prj|File||/home/andi/xilinx/diogenes/vhdl/mysio.syr|PLUGIN_General|1201550702|FILE_XST_REPORT|Generic||mysio.syrmysio.syrDESUT_XST_REPORT|File||/home/andi/xilinx/diogenes/vhdl/mysio.lso|PLUGIN_General|1200510092|FILE_LSO|Generic||mysio.lsomysio.lsoDESUT_LSO|File||/home/andi/xilinx/diogenes/vhdl/mysio.xst|PLUGIN_General|1201550654|FILE_XST|Generic||mysio.xstmysio.xstDESUT_XST|File||/home/andi/xilinx/diogenes/vhdl/sio.vhd|PLUGIN_Vhdl|1201173258||Architecture||Behavioral|mysio|||ComponentInstantiation||mysio|Behavioral|diogenes_cpu|cpu||ComponentInstantiation||mysio|Behavioral|pmemc|pmem||ComponentInstantiation||mysio|Behavioral|sc_uartc|sc_uart||ComponentInstantiation||mysio|Behavioral|vga_c|vga||Entity||mysio|Use||UNISIM|Vcomponents|all||Use||work|types|all|diogenes_cpucpupmemcsc_uartcsc_uartvga_cwork.types.alltypesUNISIM.Vcomponents.allUNISIMVcomponents|File||/home/andi/xilinx/diogenes/vhdl/cpu.xst|PLUGIN_General|1200510092||Generic||cpu.xstcpu.xst|File||/home/andi/xilinx/diogenes/vhdl/cpu.stx|PLUGIN_General|1200510096||Generic||cpu.stxcpu.stx|File||/home/andi/xilinx/diogenes/vhdl/cpu.prj|PLUGIN_General|1200510094||Generic||cpu.prjcpu.prj|File||/home/andi/xilinx/diogenes/vhdl/pmem.xst|PLUGIN_General|1200510092||File||/home/andi/xilinx/diogenes/vhdl/pmem.stx|PLUGIN_General|1200510092||File||/home/andi/xilinx/diogenes/vhdl/pmem.prj|PLUGIN_General|1200510092||File||/home/andi/xilinx/diogenes/vhdl/sc_uart.xst|PLUGIN_General|1200510092||Generic||sc_uart.xstsc_uart.xst|File||/home/andi/xilinx/diogenes/vhdl/sc_uart.stx|PLUGIN_General|1200510094||Generic||sc_uart.stxsc_uart.stx|File||/home/andi/xilinx/diogenes/vhdl/sc_uart.prj|PLUGIN_General|1200510092||Generic||sc_uart.prjsc_uart.prj|File||/home/andi/xilinx/diogenes/vhdl/types.vhd|PLUGIN_Vhdl|1200510092||PackageBody||types||PackageDecl||types|DESUT_VHDL_PACKAGE_BODYDESUT_VHDL_PACKAGE_DECL|File||/home/andi/xilinx/diogenes/vhdl/sio_vhdl.prj|PLUGIN_General|1200510092||Generic||sio_vhdl.prjsio_vhdl.prj|File||/home/andi/xilinx/diogenes/vhdl/cpu/regfile.vhd|PLUGIN_Vhdl|1200510096||Architecture||Behavioral|regfile|||ComponentInstantiation||regfile|Behavioral|reg1|dist_mem||ComponentInstantiation||regfile|Behavioral|reg2|dist_mem||Entity||regfileregfilereg2reg1|File||/home/andi/xilinx/diogenes/vhdl/cpu/fetch.vhd|PLUGIN_Vhdl|1200510094||Architecture||Behavioral|fetch|||Entity||fetch|Use||ieee|numeric_std|all|fetchieee.numeric_std.allnumeric_std|File||/home/andi/xilinx/diogenes/vhdl/cpu/execute.vhd|PLUGIN_Vhdl|1200668374||Architecture||Behavioral|execute|||ComponentInstantiation||execute|Behavioral|calu|alu||ComponentInstantiation||execute|Behavioral|cdmem|dmem||Entity||execute|Use||UNISIM|VComponents|all|executecalualucdmemUNISIM.VComponents.allVComponents|File||/home/andi/xilinx/diogenes/vhdl/cpu/decode.vhd|PLUGIN_Vhdl|1200510096||Architecture||Behavioral|decode|||ComponentInstantiation||decode|Behavioral|rf|regfile||Entity||decodedecoderf|File||/home/andi/xilinx/diogenes/vhdl/cpu/cpu.vhd|PLUGIN_Vhdl|1200667870||Architecture||Behavioral|cpu|||ComponentInstantiation||cpu|Behavioral|pipestage1|fetch||ComponentInstantiation||cpu|Behavioral|pipestage2|decode||ComponentInstantiation||cpu|Behavioral|pipestage3|execute||Entity||cpupipestage3pipestage2pipestage1|File||/home/andi/xilinx/diogenes/vhdl/cpu/alu.vhd|PLUGIN_Vhdl|1200510096||Architecture||Behavioral|alu|||ComponentInstantiation||alu|Behavioral|cbarrel|barrel||Entity||alucbarrel|File||/home/andi/xilinx/diogenes/vhdl/sio.stx|PLUGIN_General|1201550800||File||/home/andi/xilinx/diogenes/vhdl/pmem.ngc|PLUGIN_NGC|1201550800||File||/home/andi/xilinx/diogenes/vhdl/pmem/pmem.vho|PLUGIN_General|1201550800||File||/home/andi/xilinx/diogenes/vhdl/pmem/pmem.sym|PLUGIN_General|1201550800||File||/home/andi/xilinx/diogenes/vhdl/pmem/pmem.asy|PLUGIN_General|1201550800||File||/home/andi/xilinx/diogenes/vhdl/pmem/pmem.ngc|PLUGIN_NGC|1201550800||File||/home/andi/xilinx/diogenes/vhdl/pmem/pmem.vhd|PLUGIN_Vhdl|1201550800||File||/home/andi/xilinx/diogenes/vhdl/_impact.log|PLUGIN_General|1201550800||Generic||_impact.log_impact.logDESUT_LOG|File||/home/andi/xilinx/diogenes/vhdl/_impact.cmd|PLUGIN_General|1201550800|FILE_CMD|Generic||_impact.cmd_impact.cmdDESUT_CMD|File||/home/andi/xilinx/diogenes/vhdl/sio.bgn|PLUGIN_General|1200510096||Generic||sio.bgnsio.bgn|File||/home/andi/xilinx/diogenes/vhdl/sio.bit|PLUGIN_General|1200510092||File||/home/andi/xilinx/diogenes/vhdl/sio.drc|PLUGIN_General|1200510092||Generic||sio.drcsio.drc|File||/home/andi/xilinx/diogenes/vhdl/_xmsgs/trce.xmsgs|PLUGIN_General|1201550776||Generic||trce.xmsgstrce.xmsgs|File||/home/andi/xilinx/diogenes/vhdl/sio.twx|PLUGIN_General|1200510092||Generic||sio.twxsio.twx|File||/home/andi/xilinx/diogenes/vhdl/sio.twr|PLUGIN_General|1200510092||Generic||sio.twrsio.twr|File||/home/andi/xilinx/diogenes/vhdl/_xmsgs/par.xmsgs|PLUGIN_General|1201550770||Generic||par.xmsgspar.xmsgs|File||/home/andi/xilinx/diogenes/vhdl/sio_pad.csv|PLUGIN_General|1200510096||Generic||sio_pad.csvsio_pad.csv|File||/home/andi/xilinx/diogenes/vhdl/sio_pad.txt|PLUGIN_General|1200510094||Generic||sio_pad.txtsio_pad.txt|File||/home/andi/xilinx/diogenes/vhdl/sio.xpi|PLUGIN_General|1200510094||Generic||sio.xpisio.xpi|File||/home/andi/xilinx/diogenes/vhdl/sio.unroutes|PLUGIN_General|1200510094||Generic||sio.unroutessio.unroutes|File||/home/andi/xilinx/diogenes/vhdl/sio.par|PLUGIN_General|1200510094||Generic||sio.parsio.par|File||/home/andi/xilinx/diogenes/vhdl/sio.pad|PLUGIN_General|1200510094||Generic||sio.padsio.pad|File||/home/andi/xilinx/diogenes/vhdl/sio.ncd|PLUGIN_NCD|1200510094||Module||siosio|File||/home/andi/xilinx/diogenes/vhdl/sio_guide.ncd|PLUGIN_NCD|1200510096||File||/home/andi/xilinx/diogenes/vhdl/sio_usage.xml|PLUGIN_General|1200417696||Generic||sio_usage.xmlsio_usage.xml|File||/home/andi/xilinx/diogenes/vhdl/_xmsgs/map.xmsgs|PLUGIN_General|1201550722||Generic||map.xmsgsmap.xmsgs|File||/home/andi/xilinx/diogenes/vhdl/sio_map.ngm|PLUGIN_NGM|1200510096||File||/home/andi/xilinx/diogenes/vhdl/sio.pcf|PLUGIN_General|1200510094||Generic||sio.pcfsio.pcf|File||/home/andi/xilinx/diogenes/vhdl/sio_map.mrp|PLUGIN_General|1200510094||Generic||sio_map.mrpsio_map.mrp|File||/home/andi/xilinx/diogenes/vhdl/sio_map.ncd|PLUGIN_NCD|1200510092||File||/home/andi/xilinx/diogenes/vhdl/_xmsgs/ngdbuild.xmsgs|PLUGIN_General|1201550710||Generic||ngdbuild.xmsgsngdbuild.xmsgs|File||/home/andi/xilinx/diogenes/vhdl/_ngo|PLUGIN_General|1201550706||Generic||_ngo_ngoDESUT_DIRECTORY|File||/home/andi/xilinx/diogenes/vhdl/_ngo/netlist.lst|PLUGIN_General|1201550710|FILE_LST|Generic||netlist.lstnetlist.lstDESUT_LST|File||/home/andi/xilinx/diogenes/vhdl/sio.bld|PLUGIN_General|1200510094||Generic||sio.bldsio.bld|File||/home/andi/xilinx/diogenes/vhdl/sio.ngd|PLUGIN_NGD|1200510092||File||/home/andi/xilinx/diogenes/vhdl/_xmsgs/xst.xmsgs|PLUGIN_General|1201550702||Generic||xst.xmsgsxst.xmsgs|File||/home/andi/xilinx/diogenes/vhdl/sio.cmd_log|PLUGIN_General|1200510092||Generic||sio.cmd_logsio.cmd_log|File||/home/andi/xilinx/diogenes/vhdl/xst|PLUGIN_General|1200510092||Generic||xstxst|File||/home/andi/xilinx/diogenes/vhdl/sio.ngr|PLUGIN_NGR|1200510092||File||/home/andi/xilinx/diogenes/vhdl/sio.ngc|PLUGIN_NGC|1200510092|xc3s500e-5-fg320|File||/home/andi/xilinx/diogenes/vhdl/sio.prj|PLUGIN_General|1200510094||Generic||sio.prjsio.prj|File||/home/andi/xilinx/diogenes/vhdl/sio.syr|PLUGIN_General|1200510092||Generic||sio.syrsio.syr|File||/home/andi/xilinx/diogenes/vhdl/sio.lso|PLUGIN_General|1200510094||Generic||sio.lsosio.lso|File||/home/andi/xilinx/diogenes/vhdl/sio.xst|PLUGIN_General|1200510092||Generic||sio.xstsio.xst|File||/home/andi/xilinx/diogenes/vhdl/sio.ucf|PLUGIN_AssocModule|1201173560|PLUGIN_AssocModuleFILE_UCF|Module||sio.ucfsio.ucfDESUT_UCF|File||/home/andi/xilinx/diogenes/vhdl/isim.hdlsourcefiles|PLUGIN_General|1200510094|FILE_ISIM_MISC|Generic||isim.hdlsourcefilesisim.hdlsourcefilesDESUT_ISIM_MISC|File||/home/andi/xilinx/diogenes/vhdl/isimwavedata.xwv|PLUGIN_General|1200510092|FILE_XWV|File||/home/andi/xilinx/diogenes/vhdl/isim.cmd|PLUGIN_General|1200510092||Generic||isim.cmdisim.cmd|File||/home/andi/xilinx/diogenes/vhdl/xilinxsim.ini|PLUGIN_General|1200510094|FILE_INI|Generic||xilinxsim.inixilinxsim.iniDESUT_INI|File||/home/andi/xilinx/diogenes/vhdl/isim|PLUGIN_General|1200510094||File||/home/andi/xilinx/diogenes/vhdl/sio_testbench_stx.prj|PLUGIN_General|1200510094||Generic||sio_testbench_stx.prjsio_testbench_stx.prj|File||/home/andi/xilinx/diogenes/vhdl/sio_testbench.vhd|PLUGIN_Vhdl|1200510094||Architecture||sio_testbench_arch|sio_testbench|||ComponentInstantiation||sio_testbench|sio_testbench_arch|UUT|mysio||Entity||sio_testbench|Use||IEEE|std_logic_1164|all|sio_testbench_archsio_testbenchUUTIEEE.std_logic_1164.all|File||/home/andi/xilinx/diogenes/vhdl/sc_uart.vhd|PLUGIN_Vhdl|1200510094||Architecture||rtl|sc_uart|||ComponentInstantiation||sc_uart|rtl|cmp_rf|fifo||ComponentInstantiation||sc_uart|rtl|cmp_tf|fifo||Entity||sc_uartrtlcmp_rffifocmp_tf|File||/home/andi/xilinx/diogenes/vhdl/fifo.vhd|PLUGIN_Vhdl|1200510094||Architecture||rtl|fifo_elem|||Architecture||rtl|fifo|||ComponentInstantiation||fifo|rtl|f1|fifo_elem||Entity||fifo|Entity||fifo_elemf1fifo_elemArchitecture|sio|BehavioralVIEW_AssignPackagePinsTBIND_XSTAssignPackagePinsTRAN_assignPackagePinsVIEW_XSTPreSynthesisTBIND_EditConstraintsTextAppTRAN_editConstraintsVIEW_PreSynthEditConstraintsTBINDEXT_XSTPreSynthesisToStructural_spartan3eTRAN_copyPreSynthesisToStructuralForBitgenTRANEXT_xstsynthesize_spartan3eTRAN_copyPreSynthesisToStructuralForTranslateVIEW_StructuralTBIND_StructuralToPost-SynthesisAbstractSimulationTRAN_postSynthesisSimModelVIEW_Post-SynthesisAbstractSimulationTBINDEXT_StructuralToTranslation_FPGATRAN_copyStructuralToTranslationForBitgenTRAN_copyStructuralToTranslationForConstraintsTRANEXT_ngdbuild_FPGAVIEW_TranslationTBIND_xlateFloorPlannerTRAN_xlateFloorPlannerVIEW_Post-TranslateFloorPlannerTBIND_xlateAssignPackagePinsTRAN_xlateAssignPackagePinsVIEW_Post-TranslateAssignPinsTBIND_TranslationToPost-TranslateFormalityNetlistTRAN_postXlateFormalityNetlistVIEW_Post-TranslateFormalityNetlistTBIND_TranslationToPost-TranslateAbstractSimulationTRAN_postXlateSimModelVIEW_Post-TranslateAbstractSimulationTBIND_Post-TranslateAbstractToTBWPreSimulationTRAN_createPostXlateTestBenchTRAN_copyPost-TranslateAbstractToPreSimulationVIEW_TBWPost-TranslatePreSimulationTBIND_Post-TranslateAbstractToPreSimulationVIEW_Post-TranslatePreSimulationTBIND_NGCAssignPackagePinsTRAN_ngcAssignPackagePinsVIEW_ngcAssignPackagePinsTBIND_CreateTimingConstraintsTRAN_createTimingConstraintsVIEW_Post-TranslateTimingConstraintsTBIND_CreateAreaConstraintsTRAN_createAreaConstraintsVIEW_Post-TranslateAreaConstraintsTBINDEXT_TranslationToMap_spartan3TRAN_copyTranslationToMapForBitgenTRANEXT_map_spartan3VIEW_MapTBIND_preRouteTrceTRAN_preRouteTrceVIEW_Post-MapStaticTimingTBIND_mapFpgaEditorTRAN_mapFpgaEditorVIEW_Post-MapFpgaEditorTBIND_mapFloorPlannerTRAN_mapFloorPlannerVIEW_Post-MapFloorPlannerTBIND_MapToPost-MapAbstractSimulationTRAN_postMapSimModelVIEW_Post-MapAbstractSimulationTBIND_Post-MapAbstractToTBWPreSimulationTRAN_createPostMapTestBenchTRAN_copyPost-MapAbstractToPreSimulationVIEW_TBWPost-MapPreSimulationTBIND_Post-MapAbstractToPreSimulationVIEW_Post-MapPreSimulationTBINDEXT_MapToPar_spartan3TRAN_copyMapToParForBitgenTRANEXT_par_spartan3VIEW_ParTBIND_postRouteTrceTRAN_postRouteTrceVIEW_Post-ParStaticTimingTBIND_postParPrimetimeNetlistTRAN_postParPrimetimeNetlistVIEW_PrimetimeNetlistTBIND_parFpgaEditorTRAN_parFpgaEditorVIEW_Post-ParFpgaEditorTBIND_parFloorPlannerTRAN_parFloorPlannerVIEW_Post-ParFloorPlannerTBIND_genPowerDataTRAN_genPowerDataVIEW_FPGAGeneratePowerDataTBIND_createIBISModelTRAN_createIBISModelVIEW_IBISModelTBIND_XpowerTRAN_XPowerVIEW_FPGAAnalyzePowerTBIND_ParToPost-ParFormalityNetlistTRAN_postParFormalityNetlistVIEW_Post-ParFormalityNetlistTBIND_ParToPost-ParClockRegionTRAN_clkRegionRptVIEW_Post-ParClockRegionReportTBIND_ParToPost-ParAsyncDelayTRAN_asynDlyRptVIEW_Post-ParAsyncDelayReportTBIND_ParToPost-ParAbstractSimulationTRAN_postParSimModelVIEW_Post-ParAbstractSimulationTBIND_Post-ParAbstractToTBWPreSimulationTRAN_createPostParTestBenchTRAN_copyPost-ParAbstractToPreSimulationVIEW_TBWPost-ParPreSimulationTBIND_TBWPost-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuse(bencher)VIEW_TBWPost-ParFuseTBIND_TBWPost-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModel(bencher)VIEW_TBWPost-ParSimulationISimTBIND_Post-ParAbstractToPreSimulationVIEW_Post-ParPreSimulationTBIND_Post-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuseVIEW_Post-ParFuseTBIND_Post-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModelVIEW_Post-ParSimulationISimTBIND_ParToMpprResultTRAN_copyMpprRsltVIEW_MpprResultTBIND_ParToLockedPinConstraintsTRAN_genLockedPinConstraintsVIEW_LockedPinConstraintsTBIND_ParToBackAnnoPinLocationsTRAN_backAnnoPinLocationsVIEW_BackAnnoPinLocationsTBINDEXT_ParToFPGAConfiguration_spartan3eTRANEXT_bitFile_spartan3eVIEW_FPGAConfigurationTBIND_analyzeDesignUsingChipscopeTRAN_analyzeDesignUsingChipscopeVIEW_AnalyzedDesignTBIND_UpdateBitstreamXPSTRAN_xpsUpdBitstreamVIEW_UpdatedBitstreamTBIND_FPGAConfigurationToFPGAGeneratePROMTRAN_genImpactFileVIEW_FPGAGeneratePROMTBIND_FPGAConfigurationToFPGAConfigureDeviceTRAN_impactProgrammingToolVIEW_FPGAConfigureDeviceTBIND_XSTAbstractToPreSynthesisTRAN_copyAbstractToPreSynthesisForBitgenTRAN_copyAbstractToPreSynthesisForTranslateTRAN_convertToHdlTRAN_copyAbstractToPreSynthesisForSynthesisVIEW_XSTAbstractSynthesisAutoGeneratedViewArchitecture|sc_uart|rtlTBIND_InitialToXSTAbstractSynthesisTRAN_copyInitialToXSTAbstractSynthesisVIEW_InitialTBIND_InitialToAbstractSimulationTRAN_copyInitialToAbstractSimulationVIEW_AbstractSimulationTBIND_AbstractToPostAbstractSimulationTRAN_copyAbstractToPostAbstractSimulationVIEW_PostAbstractSimulationTBIND_PostAbstractToTBWPreSimulationTRAN_viewBehavioralTestbenchTRAN_copyPostAbstractToPreSimulationVIEW_TBWPreSimulationTBIND_TBWPreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuse(bencher)VIEW_TBWBehavioralFuseTBIND_TBWBehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModel(bencher)VIEW_TBWBehavioralSimulationISimTBIND_PostAbstractToPreSimulationVIEW_PreSimulationTBIND_PreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuseVIEW_BehavioralFuseTBIND_BehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModelVIEW_BehavioralSimulationISimTBIND_PostAbstractToAnnotatedPreSimulationTRAN_viewBehavioralTestbenchForAnnoTRAN_copyPostAbstractToAnnotatedPreSimulationVIEW_AnnotatedPreSimulationTBIND_PreToGenerateAnnotatedResultsFuseTRAN_ISimGenerateAnnotatedResultsRunFuseTRAN_copyPreToGenerateAnnotatedResultsFuseForTBWVIEW_AnnotatedResultsFuseTBIND_FuseToAnnotatedResultsISimTRAN_ISimGenerateAnnotatedResultsTRAN_copyFuseToAnnotatedResultsISimForTBWVIEW_AnnotatedResultsISimTBIND_AnnotatedToGenerateExpectedSimulationResultsISimTRAN_ISimGenerateExpectedSimulationResultsVIEW_ExpectedSimulationResultsISimTBINDEXT_InitialToCommon_FPGATRANEXT_compLibraries_FPGAVIEW_CommonDESPF_TRADITIONALPROP_PreferredLanguageVerilogVHDLPROP_SimulatorISE Simulator (VHDL/Verilog)Other MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-XE VHDLModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE MixedModelsim-SE VerilogModelsim-SE VHDLPROP_Synthesis_ToolXST (VHDL/Verilog)PROP_Top_Level_Module_TypeHDLPROP_DevSpeed-5-4PROP_DevPackagecp132fg320PROP_DevDevicexc3s100exc3s500exc3s1600exc3s1200exc3s250epq208ft256PROP_ParSmartGuideFileNamePROP_SmartGuidePROP_TopDesignUnitModule|mysioNCD files (*.ncd)|*.ncdPROP_MapSmartGuideFileNamePROP_ISimSpecifyDefMacroAndValuePROP_ISimSpecifySearchDirectoryPROP_ISimValueRangeCheckPROP_ISimCompileForHdlDebugPROP_ISimIncreCompilationPROP_xstVeriIncludeDirPROP_tbwPostParTestbenchNamesio_testbench.timesim_vhwPROP_tbwTestbenchTargetLangArchitecture|sio_testbench|sio_testbench_archPROP_tbwPostMapTestbenchNamesio_testbench.map_vhwPROP_tbwPostXlateTestbenchNamesio_testbench.translate_vhwPROP_PostParSimModelName_timesim.vhdPROP_SimModelTargetmysio_timesim.vhdPROP_PostMapSimModelNamemysio_map.vhd_map.vhdPROP_PostXlateSimModelName_translate.vhdmysio_translate.vhdPROP_SimModelRenTopLevEntToPROP_SimModelGenArchOnlyArchitecture|mysio|BehavioralPROPEXT_xilxSynthAddBufg_spartan3ePROPEXT_xilxBitgCfg_Rate_spartan3eDefault (1)PROPEXT_xilxSynthMaxFanout_virtex2PROPEXT_SynthMultStyle_virtex2AutoPROPEXT_xilxMapGenInputK_virtex24PROP_MapRegDuplicationPROP_xilxMapTimingDrivenPackingPROP_MapLogicOptimizationPROP_MapPlacerCostTablePROP_MapExtraEffortNonePROP_MapEffortLevelMediumHighStandardContinue on ImpossibleNormalPROP_xilxBitgCfg_GenOpt_IEEE1532FilePROP_xilxBitgStart_Clk_MatchCyclePROP_bitgen_otherCmdLineOptionsPROP_xilxBitgCfg_GenOpt_DbgBitStrPROP_xilxBitgCfg_GenOpt_CompressPROP_xilxBitgCfg_GenOpt_ASCIIFilePROP_xilxBitgCfg_GenOpt_BinaryFilePROP_xilxBitgCfg_GenOpt_BitFilePROP_xilxBitgCfg_GenOpt_DRCPROP_parMpprNodelistFilePROP_xilxPARstratNormal Place and RouteAll files (*)|*PROP_parMpprResultsDirectorymppr_resultPROP_parMpprResultsToSavePROP_parMpprParIterationsPROP_mpprRsltToCopyPROP_mpprViewPadRptForSelRsltPROP_mpprViewPadRptsForAllRsltPROP_mpprViewParRptForSelRsltPROP_mpprViewParRptsForAllRsltPROP_par_otherCmdLineOptionsPROP_parPowerReductionPROP_parGenSimModelPROP_parGenTimingRptPROP_xstUseSyncResetYesPROP_xstUseSyncSetPROP_xstUseClockEnablePROP_xilxSynthRegDuplicationPROP_xstOptimizeInsPrimtivesPROP_xstSlicePackingPROP_xstPackIORegisterPROP_xstMoveLastFfStagePROP_xilxSynthRegBalancingNoPROP_xstMoveFirstFfStagePROP_SynthLogicalShifterExtractPROP_SynthShiftRegExtractPROP_SynthDecoderExtractPROP_SynthMuxStylePROP_SynthExtractMuxMUXCYMUXFPROP_xstROMStylePROP_SynthExtractROMBlockDistributedPROP_SynthRAMStylePROP_SynthExtractRAMPROP_xstFsmStyleLUTPROP_xstCrossClockAnalysisPROP_xstSliceUtilRatioPROP_xstWriteTimingConstraintsPROP_xstCoresSearchDirPROP_xstReadCoresPROP_xstAsynToSyncPROP_xstBRAMUtilRatioPROP_xstAutoBRAMPackingPROP_xilxSynthGlobOptAllClockNetsPROP_CompxlibXlnxCoreLibPROP_impactConfigFileNamePROP_impactConfigModePROP_ImpactProjectFileDesktop ConfigurationSelect MAPSlave SerialBoundary ScanISC files (*.isc)|*.iscCMD files (*.cmd)|*.cmdHEX files (*.hex)|*.hexMCS files (*.mcs)|*.mcsEXO files (*.exo)|*.exoCDF files (*.cdf)|*.cdfBIT files (*.bit)|*.bitPROP_AceActiveNamePROP_AutoGenFilePROP_primeTopLevelModulePROP_primeCorrelateOutputPROP_primeFlatternOutputNetlistPROP_primetimeBlockRamDataPROP_xilxPostTrceTSIFilePROP_xilxPostTrceStampPROP_PostTrceFastPathPROP_xilxPostTrceUncovPathPROP_xilxPostTrceSpeedAbsolute MinPROP_xilxPostTrceAdvAnaPROP_xilxPostTrceRptLimitPROP_xilxPostTrceRptError ReportPROP_PreTrceFastPathPROP_xilxPreTrceUncovPathPROP_xilxPreTrceSpeedPROP_xilxPreTrceAdvAnaPROP_xilxPreTrceRptLimitPROP_xilxPreTrceRptPROP_CurrentFloorplanFilePROP_xilxBitgCfg_GenOpt_MaskFilePROP_xilxBitgCfg_GenOpt_ReadBackPROP_xilxBitgCfg_GenOpt_LogicAllocFilePROP_xilxBitgReadBk_GenBitStrPROP_xilxBitgReadBk_SecEnable Readback and ReconfigurationPROP_xilxBitgStart_Clk_DriveDonePROP_xilxBitgStart_Clk_RelDLLDefault (NoWait)PROP_xilxBitgStart_Clk_WrtEnDefault (6)PROP_xilxBitgStart_Clk_EnOutDefault (5)PROP_xilxBitgStart_Clk_DoneDefault (4)PROP_xilxBitgStart_IntDonePROP_xilxBitgStart_ClkCCLKPROP_xilxBitgCfg_Code0xFFFFFFFFPROP_xilxBitgCfg_UnusedPull DownPROP_xilxBitgCfg_TMSPull UpPROP_xilxBitgCfg_TDOPROP_xilxBitgCfg_TDIPROP_xilxBitgCfg_TCKPROP_xilxBitgCfg_DonePROP_xilxBitgCfg_PgmPROP_xilxBitgCfg_M2PROP_xilxBitgCfg_M1PROP_SynthEncoderExtractPROP_xilxBitgCfg_M0PROP_xilxBitgCfg_ClkPROP_mapUseRLOCConstraintsPROPEXT_xilxSynthAddBufg_spartan3PROP_xilxMapPackfactorPROP_xilxMapAllowLogicOptPROP_xilxMapReplicateLogicPROP_xilxNgdbldURPROP_xilxNgdbldUnexpBlksPROP_xilxMapPackRegIntoFor Inputs and OutputsPROP_xilxNgdbldNTTypeTimestampPROP_xilxMapDisableRegOrderingPROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3As RequiredPROP_xilxMapReportDetailPROP_xilxMapCoverModeAreaPROP_xilxPARplacerCostTablePROP_xilxMapTrimUnconnSigPROP_xilxNgdbldPresHierarchyPROP_ngdbuildUseLOCConstraintsPROP_xilxPARrouterEffortLevelPROP_xilxPARplacerEffortLevelPROPEXT_xilxBitgCfg_Rate_spartan3PROP_xilxBitgCfg_GenOpt_EnableCRCPROP_xilxPARextraEffortLevelPROP_xilxPAReffortLevelPROP_xilxNgdbldIOPadsPROP_map_otherCmdLineOptionsPROP_xilxMapSliceLogicInUnusedBRAMsPROP_xilxBitgCfg_DCMShutdownPROP_MapPowerReductionPROP_parGenClkRegionRptPROP_parGenAsyDlyRptPROP_xilxPARuseBondedIOPROP_parUseTimingConstraintsPROP_Enable_Incremental_MessagingPROP_Enable_Message_FilteringPROP_Enable_Message_CapturePROP_FitterReportFormatHTMLPROP_FlowDebugLevelPROP_UserConstraintEditorPreferenceConstraints EditorPROP_UserEditorCustomSettingPROP_UserEditorPreferenceISE Text EditorPROP_XplorerOtherCmdLineOptionsPROP_XplorerModeOffPROP_XplorerSearchPathForSourcePROP_XplorerEnableRetimingPROP_XplorerNumIterationsPROP_XplorerRunTypePROP_SimModelInsertBuffersPulseSwallowPROP_SimModelAutoInsertGlblModuleInNetlistPROP_SimModelGenMultiHierFilePROP_SimModelRetainHierarchyPROP_PostSynthSimModelName_synthesis.vhdPROP_SimModelIncUnisimInVerilogFilePROP_SimModelIncSimprimInVerilogFilePROP_xstSafeImplementPROP_SynthFsmEncodePROP_XPowerOtherXPowerOptsPROP_XPowerOptBaseTimeUnitpsPROP_XPowerOptUseTimeBasedPROP_XPowerOptLoadVCDFileDefaultusfsnsPROP_XPowerOptNumberOfUnitsPROP_XPowerOptInputTclScriptPROP_XPowerOptLoadPCFFilePROP_XPowerOptOutputFilePROP_XPowerOptLoadXMLFilePROP_XPowerOptMaxNumberLinesPROP_XPowerOptVerboseRptPROP_XPowerOptAdvancedVerboseRptPROP_xilxSynthKeepHierarchyPROP_xilxNgdbldMacro/home/andi/xilinx/rs232/cpu/PROP_xilxNgdbld_AULPROP_SynthXORCollapsePROP_ngdbuild_otherCmdLineOptionsPROP_impactPortparport0 (LINUX)/dev/ttyb (UNIX)/dev/ttya (UNIX)USB 2 (PC)USB 1 (PC)USB 0 (PC)COM 3 (PC)COM 2 (PC)COM 1 (PC)LPT 3 (PC)LPT 2 (PC)LPT 1 (PC)LPT 0 (PC)PROP_impactBaud5760038400192009600PROP_ibiswriterShowAllModelsPROP_ISimCustomCompilationOrderFilePROP_ISimUseCustomCompilationOrderPROP_ISimSpecifyDefMacroAndValueChkSyntaxPROP_ISimSpecifySearchDirectoryChkSyntaxPROP_ISimSDFTimingToBeReadSetup TimePROP_ISimVCDFileName_par_tbwxpower.vcdPROP_ISimGenVCDFile_par_tbwPROP_ISimUseCustomSimCmdFile_par_tbwPROP_ISimVCDFileName_par_tbPROP_ISimGenVCDFile_par_tbPROP_ISimUseCustomSimCmdFile_par_tbPROP_ISimStoreAllSignalTransitions_behav_tbwPROP_ISimUseCustomSimCmdFile_behav_tbwPROP_ISimStoreAllSignalTransitions_behav_tbPROP_ISimUseCustomSimCmdFile_behav_tbPROP_ISimStoreAllSignalTransitions_par_tbwPROP_ISimStoreAllSignalTransitions_par_tbPROP_ISimSimulationRunTime_behav_tbw1000 nsPROP_ISimSimulationRun_behav_tbwPROP_ISimSimulationRunTime_behav_tb30000 nsPROP_ISimSimulationRun_behav_tbPROP_ISimSimulationRunTime_par_tbwPROP_ISimSimulationRun_par_tbwPROP_ISimSimulationRunTime_par_tbPROP_ISimSimulationRun_par_tbPROP_ISimCustomSimCmdFileName_gen_tbwPROP_ISimUseCustomSimCmdFile_gen_tbwPROP_ISimCustomSimCmdFileName_behav_tbwPROP_ISimCustomSimCmdFileName_behav_tbPROP_ISimCustomSimCmdFileName_par_tbwPROP_ISimCustomSimCmdFileName_par_tbPROP_ISimUutInstNamePROP_xstEquivRegRemovalPROP_xilxSynthAddIObufPROP_SynthResSharingPROP_SynthCaseImplStylePROP_xstBusDelimiter<>PROP_xstHierarchySeparator/PROP_xstGenerateRTLNetlistPROP_xst_otherCmdLineOptionsPROP_xstVerilogMacrosPROP_xstGenericsParametersPROP_xstUserCompileListPROP_xstVerilog2001PROP_xstIniFilePROP_xstWorkDir./xstPROP_xstCaseMaintainPROP_xstLibSearchOrderPROP_xstUseSynthConstFilePROP_SynthConstraintsFileCST files (*.cst)|*.cstXCF files (*.xcf)|*.xcfPROP_SynthOptEffortPROP_SynthOptSpeedPROP_CorgenRegenCoreUnder Current Project SettingPROP_coregenFuncModelTargetLangPROP_SimModelNoEscapeSignalPROP_SimModelPathUsedInSdfAnnPROP_SimModelIncSdfAnnInVerilogFilePROP_SimModelIncUselibDirInVerilogFilePROP_SimModelRenTopLevModPROP_SimModelOtherNetgenOptsPROP_SimModelOutputExtIdentPROP_SimModelRenTopLevInstToPROP_SimModelGenerateTestbenchFilePROP_SimModelRenTopLevArchToStructurePROP_SimModelRocPulseWidthPROP_SimModelBringOutGsrNetAsAPortPROP_SimModelGsrPortNameGSR_PORTPROP_SimModelTocPulseWidthPROP_SimModelBringOutGtsNetAsAPortPROP_SimModelGtsPortNameGTS_PORTPROP_ChangeDevSpeedPROP_CompxlibLangAllPROP_CompxlibSimPrimativesPROP_ModelSimProcWinPROP_SimDoPROP_ModelSimVarsWinPROP_ModelSimStructWinPROP_ModelSimSignalWinPROP_ModelSimWaveWinPROP_CompxlibUniSimLibPROP_CompxlibOtherCompxlibOptsPROP_CompxlibOverwriteLibOverwritePROP_CompxlibSimPathSearch in PathPROP_CompxlibOutputDir$XILINX//PROP_OverwriteSymPROP_MSimSDFTimingToBeReadPROP_ModelSimConfigNamePROP_ModelSimUseConfigNamePROP_ModelSimSimRunTime_tbw1000nsPROP_SimCustom_postParPROP_SimUseCustom_postParDO files (*.do)|*.doPROP_SimCustom_postMapPROP_SimUseCustom_postMapPROP_SimCustom_postXlatePROP_SimUseCustom_postXlatePROP_SimUserCompileList_behavPROP_SimCustom_behavPROP_SimUseCustom_behavPROP_SimGenVcdFilePROP_ModelSimUutInstName_postParPROP_ModelSimUutInstName_postMapPROP_ModelSimSimRunTime_tbPROP_SimUseExpDeclOnlyPROP_SimSyntax9387PROP_ModelSimSimResDefault (1 ps)100 sec10 sec1 sec100 ms10 ms1 ms100 us10 us1 us100 ns10 ns1 ns100 ps10 ps1 ps100 fs10 fs1 fsPROP_ModelSimDataWinPROP_ModelSimSourceWinPROP_DesignNamePROP_PartitionForcePlacementPROP_PartitionForceTranslatePROP_PartitionForceSynthPROP_PartitionCreateDeletePROP_vlog_otherCmdLineOptionsPROP_vcom_otherCmdLineOptionsPROP_vsim_otherCmdLineOptionsPROP_ModelSimListWinPK
199
xo0__OBJSTORE__/ProjectNavigator/__stored_objects__
200

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~         
201


202
 
!"#$%&'()*+,-./01/    -xrtpq/9
203

204

 |~ 
XZ[\]`o}e0u%*+)78,2z@   
205

!"#$&'()*+,-./01345DEFGMWafghijklmn	!"#$%&'(.123456
7?8m9K:B;A<@=y>z?{@|A}B~CDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmbncodpeqfrhsjtkulvZw[x]y_z`{a|C}D~EFGHIJPQRSTUVWXYLuvNwx=>nopqr
206
 
207

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  
208

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  
209

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  
210

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  
211

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUPVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      
212

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  
213

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  
214
 
215

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~     
216

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXY~Z[}\]^_`|abcdexfgwhivjklmnropqqrpstuvwxyjz{|}~fed]\[PONMLKJFEDCBA@?>=<;:987&6       %
217

 !"#$%&'()*+,-5.&/0123456789:;<=>?@ABCDEFGHIJKLMNOPQRST4UV3W$XYZ[2\]^_.RS`QQ"Cmk=#ab/c5d1e4f3gtZhvjkli^hj_kPOstubcaxl]m[nWoYpUqSNMrsLtMusvOwHxJX?yz
218
{        Uzq|r}B~@><76D:F8\WnA
}$qpo|oP9LEJHKIVx+!N{(
219
z*|&mT;`fafhddbiv/w-gix1;RK5?P_'Vvt$~*co3=a]TYX-7&zk[)+3N "q
220
HB/97UmZWepr%|E1G6`1G6 YG6 1G611111111111111111G6X111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111G5nmysio.stx//_xG@
221
+/^xG+@
222
/\xG@
223
G(video_ram.vho.._xG6a@
224
.^xG6`@
225
.\xG6^J@
226
G(video_ram.vhd_xG6Q6
227
G6OO,
228
G''G'f &^xG6M6
229
(G6L,
230
(G''G'y &\xG6JH6
231
G't~G6HT,
232
G'? )G'!'G6A. &G(video_ram.xco/_x/G6,         
233

234
/
 /G't
235
&i
/
236

G6?/G't
237
9/
238

G6?Z^xZG6*m        
239
Z'Z G't  Z!
240
G8
kG8
#i!Gi)ZGG'G'GG6
241
GE       G6 YG6      PGG*
242

G6SZ"G't     ]Z
243

G6.
244
\x
245
G6'         #
246

247
$%"&
248
'G't     q)%
249

250

G6.3
251
(G't     T$
252

253

G6.$)*+G(video_ram.ngc,---_xG6} +./0
254
+1-^xG6{c *.20
255
(3-!\x!G6yt ).40
256
!5678Glvga/vga.vhdl9:;<=NO_xO>N:;<=Gl8>        ?           
257
O @AG
O  4      Gl28   B        
258
N CDG
8               G
,8                G
8                        G
E 8    EFGH^xIEFGHGl7I  J           
259
'(KG

260
      4      Gl7   L        
261
'(MG
7                     G
X7                G
7                        G
l 7    NOPQ(\x(RNOPQGl%6R  S           
262
("TG
(  4      Gl6   U        
263
"VG
O6               G
6                G
6                        G
݋ 6    WXY
264
G5_xmsgs/bitgen.xmsgsZ[     ,,\_x \GW@Y   
       ]      
       
^   
265
\_,`^x      `G@X   
       a      
       
^   
266
`b,c\x      cG@W   
       d      
       
^   
267
cefgh    G5mysio.bgnij      ++k_x kGs@h          l             m   
268
kn+^^x      ^G@g          o             m   
269
^/p+q\x    qG6@f          r             m   
270
qstuv    G5mysio.bitwx      **y_x yGp@v          z             {   
271
y|*]^x      ]G@u          }             {   
272
]/~*\x    G(@t                       {   
273
    G5mysio.drc      ))_x G@                          
274
)_^x      _G@                          
275
_/)\x    G7@                          
276
    GTcoregen.log    ((_x(^x(\x      GTsio_testbench_isim_beh.exe     !''_x'^x'\x     "GTsio_testbench_beh.prj  #&&_x $G        @    %       $      %       %   &
277
&^x      $G        ~@    %       $      %       %   &
278
&\x      $G        }%@    %       $      %       %   &
279
    'GTsio_testbench_isim_par.exe     !%%_x%^x%\x     (GTsio_testbench_par.prj  #$$_x )G        q@    *       )      *       *   &
280
$^x      )G        o@    *       )      *       *   &
281
$\x      )G        nD@    *       )      *       *   &
282
    +GTnetgen ,##_x#^x#\x     -GTnetgen/par/mysio_timesim.sdf   .""_x"^x"\x     /GTnetgen/par/mysio_timesim.vhd_x^x\x       0GTnetgen/par/mysio_timesim.nlf   1!!_x!^x!\x     2GTcpu/barrel.vhd

67_x       37     46G        d           3&             5
283
7 G       b_    5       4  5
284
6 GEj
j9               GEj
i                GEj
iw                        GEj
i     
^x  3     4G        `           3&             5
285
'(G     _S    5       4  5
286
'(GEj
jd                     GEj
j                GEj
i                        GEj
iC     
\x  3     4G        ]           3&             5
287
"G       [    5       4  5
288
"GEj
`               GEj
`                GEj
`o                        GEj
`       6G5~mysio_map.ngm    7       8  _x 9G[q    :       9      :   ;
289
- ^x    9GY    :       9      :   ;
290
 \x      9GW    :       9      :   ;
291
    <G5mysio.pcf	=_x	>G
@    ?       >      ?       ?   @
292
-^x    >G
H@   ?       >      ?       ?   @
293
\x      >G
@   ?       >      ?       ?   @
294
 
295
      AG5mysio_map.ncd    B       C_x 9G
~/ 
296
    :       9
      :   D
297
-^x    9G
|             :       9
      :   D
298
\x      9G
zS    :       9
      :   D
299
    EGTcpu_stx.prj    #_x FGv@   G       F      G       G   &
300
^x      FG@   G       F      G       G   &
301
 !\x      F!G߃@   G       F"      G       G   &
302
!#$%&    HGTcpu/pmem.vho'(_x   I(G@&   J       I)      J       J
303
(*+^x      I+Gڜ@%   J       I,      J       J
304
+-.\x      I.G@$   J       I/      J       J
305
.0123    KGTcpu/pmem.sym45   L6_x M6GՎ@3   N       M7      N       N8   O
306
69:^x      M:G&@2	N	M; N       N8   O
307
:<=\x	M=Gҝ@1	N	M>       N       N8   O
308
=?@AB    PGTcpu/pmem.asyCD   QE_x REG@B   S       RF      S       S
309
EGH^x      RHGͲ@A   S       RI      S       S
310
HJK\x      RKG@@   S       RL      S       S
311
KMNOP    TGTcpu/pmem.vhdQRS89_x     U9     V8RSGƆP   W       U6T        W     X
312
9 UVGP  X       V,W  X
313
8 XYG>
[P'G>
 P&Z[^x    U     VZ[GOO   W       U6\        W     X
314
'(]GO        X       V,^  X
315
'(_G>
O'G>
$ O&`ab\x        U     Yc     VbaGNc W       U6d        W     X
316
"eG>
(        Y~      ZG N     X       V,f  X
317
"gG>
} N)G>
BN'G{ N&hij [GTcpu/pmem.xcokM_x   \MGP j   X       \     l  X
318
Mmn opMqG>nM
319

GxMrG>ѸmM
320

GkY^x   \YG i   X       \     s  X
321
Ytu'vYwG>uYx
322
xGl9YGG GG8
kG8
#iG6
323
GE       G6 YG6      PG
324
GI
325
GIYyG>tY
326

G'\x   \'G h   X       \     z  X
327
'{|"}'~G>=|'x
328
xGJ#'GJ#1)GJ:GJ:G8
kG8
#iG6
329
GE       G6 YG6      PGJeGJeS
330

G'G>{'
331

G= ]G5Jmysio.ngr        ^       __x 9GWi    :       9      :   `
332
+^x    9GU    :       9      :   `
333
\x      9GS    :       9      :   `
334
    aGTcpu/dist_mem.vho_x       bG@   c       b      c       c
335
^x      bGM@   c       b      c       c
336
\x      bGl@   c       b      c       c
337
    dGTcpu/pmem.ngc-_x   \Go    X       \.      X0
338
+^x    \Gn    X       \.      X0
339
(x e\x    \xGl9    X       \.      X0
340
 
341
+^x    gG`    h       g.      h0
342
( i\x    gG^    h       g.      h0
343
    jGTpmem_readme.txt        k_x^x\x     lGTpmem.vho_x^x\x   mGTpmem.sym5       L_x^x\x     nGTpmem.asyD       Q_x^x\x     oGTcpu/dist_mem.xcoL_x       gLG{    h       g       h
344
L LG=
L
345

G>wLG=
L
346

G>jX^x   gXG    h       g       h
347
X'XG=X

348
XGG
GG^G8
kG8
#iG6
349
GE       G6 YG6      PG JG
350
o
351
G
352
oXG=X
353

Gp&\x   g&G0    h       g       h
354
&"&G=I&x
&G=vG=y

G=y
xGJ#G=TG8
kG8
#iG6
355
GE       G6 YG6      PGJe-GJe1
356

G"&G=&
357

GH pGTcpu/dist_mem.vhd
358

359
01_x        q1     r0G   s       q6        s     h
360
1 G  h       r,  h
361
0 G=y
'G=y
v &
362
^x        q     rG   s       q6        s     h
363
'(G        h       r,  h
364
'(G=y
'G=y
 &
365

\x      q
     t     rG s       q6        s     h
366

"G=y
C
        th      uG     h       r,  h
367
"G=y
 )G=y
'G & vGTmysio.sym5      L_x wG\@   x       w      x       x8   O
368
^x      wG
369
@      x       w      x       x8   O
370
\x      wG@   x       w      x       x8   O
371
    yG5mysio.twx      zG_x {GG
372

@    |       {      |       |   }
373
GC^x    {G
374
@    |       {       |       |   }
375

376
\x    {G
377
@    |       {      |       |   }
378

    ~G5mysio.twr      F_x FG
379
'@                           
380
FC^x    G
381
382
@                            
383
\x      G
384
@                           
385
    G5mysio_pad.csv   _x G
386
B@           !             "   
387
.#$^x    $G
388
@           %             "   
389
$&'\x      'G
390
@           (             "   
391
')*+,    G5mysio_pad.txt-.  

_x G        @,           /             0   
392
1.23        4G9$156
393

G
394
7    
8^x      8G        v@+           9             0   
395
8:;3  8<G9:856
396

G
397
W7    
=\x      =G        @*           >             0   
398
=?@3  =AG98?=56
399

G
400
       7      BCD    G5mysio.xpiEF      G_x GG        9@D           H             I   
401
GJK^x      KG        @C           L             I   
402
KMN\x      NG        
403
@B             O             I   
404
NPQRS    G5mysio.unroutesTU _x G        h@S           V             W   
405
.XY^x    YG        @R           Z             W   
406
Y[\\x      \G        @Q           ]             W   
407
\^_`a    G5mysio.parbc      
408

409
_x      G        @a           d             e   
410
f.gh        iG9Qfjk
411

G   l    
412
m^x      mG        @`           n             e   
413
moph  mqG9omjk
414

G   _l    
415
r\x      rG        @_           s             e   
416
rtuh  rvG9itrjk
417

G   l    wxy    G5mysio.padz{                   |_x      |G        Q@y           }             ~   
418
| ^x      G        @x                        ~   
419
 \x      G        @w                        ~   
420
    G5mysio.ncd        B       C_x 9G        ڊ     :       9
      :   D
421
.^x    9G             :       9
      :   D
422
\x      9G             :       9
      :   D
423
    G5mysio_guide.ncd  B       C_x 9G|    :       9
      :   D
424
^x      9G{7    :       9
      :   D
425
\x      9Gy    :       9
      :   D
426
    G5mysio_usage.xml        _x G*@                          
427
^x      G)@                          
428
\x      G'E@                          
429
    G5mysio_map.mrp  _x G#b@                          
430
-^x    G!@                          
431
\x      G@                          
432
    G5vmysio.ngd               _x 9Gm    :       9      :   
433
,^x    9G    :       9      :   
434
\x      9G    :       9      :   
435
    GTcpu/dmem.vhdHI_x     I     HG
436
~           4             
437
I G
438
           ,  
439
H G9n@'G9n@0 &^x         G
440
           4             
441
'(G
442
S           ,  
443
'(G9n@'G9n@U &"#\x        #          "G
444
         4             
445
#"G9n>G#        e      G
446
L           ,  
447
""G9n9D )G9n8'G
448
uo &     G5vmysio.bld      _x G@                          
449
,^x    GW@                          
450
\x      G@                          
451
    G5npmem.vhd_x^x\x   G5nmysio.ngc-_x      9G    :       9.      :0
452
+^x    9G0    :       9.      :0
453
   \x    9G    :       9.      :0
454
    G5mysio.cmd_log  _x G@                        
455
        
456
^x      G3@          
             
457
        
458
\x      G@                       
459
        
460
    G5>mysio.prj      #_x G@                          &
461
+^x    GP@                          &
462
\x      G@                          &
463
     G5nmysio.syr!"      _x G@           #             $   
464
+%&^x    &G@          '             $   
465
&()\x      )Ga@          *             $   
466
)+,-.    GTmysio.lso/0      _x G@.          1             2   
467
+34^x    4G@-          5             2   
468
467\x      7G@,          8             2   
469
79:;<	G5>mysio.xst=>       _x Gw@<          ?             @   
470
+AB^x    BG@;          C             @   
471
BDE\x      EG#@:          F             @   
472
EGHIJ    Gs
473
sio.vhdK LMNOPQRFG_x  G     S     T     U     V     FPMNO     Q     RGs
474
ڢJVUTS             CW             :
475
G XYG9tG                        G9sG                           XG9r?G                           G G                           Gs
476
J      :       %Z  :
477
F [\G9JJ                G9J                         G9 J   G94J               G9J                G9oJ                        Gs
478
a J         ]^_`abc^x       d     e     f     g     a^_`     b     cGs
479
]Igfed             Ch             :
480
'(iG9t                              G9s                           XG9ri                           GM                           Gs
481
I      :       %j  :
482
'(kG9rI                      G9I                         G9 I   G9^I               G9I                G9I                        Gs
483
 I         lmnopqr !\x  !     s     t     u     v      pmno     q     rGs
484
Hvuts             Cw             :
485
!"xG9]r!                        G9\!                           XG9[|!                           G`!                           Gs
486
1H      :       %y  :
487
 "zG9H                G9H                         G9 H   G9XH               G9H                G9~H                        Gs
488
\ H      {|}  GTcpu.xst~>        _x GKl@}                       @   
489
^x      GH@|                       @   
490
\x      GEf@{                       @   
491
    GTcpu.stx_x        G&7@                       
492
^x      G#U@                       
493
\x      G@                       
494
 
495
^x      G=@                          &
496
\x      G@                          &
497
    GTpmem.xst>       _x^x\x     GTpmem.stx_x^x\x   GTpmem.prj       #_x^x\x     GTsc_uart.xst>    _x G@                       @   
498
^x      G@                       @   
499
\x      G@                       @   
500
    GTsc_uart.stx_x    GV@
501
       
502
503

504
^x      GQ{@
505
       
506
507

508
\x      G@
509
       
510
511

512

513
GTsc_uart.prj    #_x
514
G@
515

516

517

518
   &
519
^x
520
G<@
521

522

523

524
   &
525
\x
526
G@
527

528

529

530
   &
531

532
GTtypes.vhdJK_x
533
K
534
JGߏ       
535
  
536

537
K G҂@  
538

539
  
540

541
J G9X                       G9XŨ     ^x
542

543
G       
544
  
545

546
'(G@        
547

548
  
549
 
550
'(G9X,                             G9X     $%\x
551
%
552
$Gȕ       
553
  
554

555
%"G8@  
556

557
  
558

559
$"G9X                       G9X     
560
        GTsio_vhdl.prj    #_x
561
562
Ge@
563
564
565

566
567
   &
568
^x
569
570
G]@
571
572
573

574
575
   &
576
\x
577
578
G@
579
580
581

582
583
   &
584

585
GTcpu/regfile.vhdDE_x
586

E
587

588

589
D     G
590

+
591

592
E 
593
G9
EE
594

595
K
596
       hG9

TE
597

598
A
599
       hG'
600

601
!
602

603
D 
G9
                        G9
       O                  G9
                G9
                        G9
,     ^x
604


605

606

607
     G
608

+
609

610
'(G9
k
611

612
K
613
       hG9


614

615
A
616
       hG~1
617

618
!
619

620
'(G9
                      G9
       v                  G9
                         G9
                        G9
P     \x
621


622

623

624
     Gz
625

+!
626

627
""G9
^
628

629
K
630
       hG9

631

632
A
633
       hGts
634

635
!#
636

637
"$G9
Z               G9
                G9
                G9
                        G9
d     %&'
638
GTcpu/fetch.vhd()*+,-.BC_x
639
C
640
B)*+,
641
 
642
 
643
 
644
 
645
 
646
!2
647

648
B 34G9       P'                 G9        P'
649

650

651
G9        P'                 G9        O'                 G9        OI'                         G9 N '    56789:^x
652

653
5678
654
9     :GTS&
655
1;
656

657
'(<GQO&
658

659
!=
660

661
'(>G9     Q&                 G9        P&
662

663

664
G9        P@&                 G9        O&                 G9        O&                         G9 O &    ?@ABCD\x
665

666
?@AB
667
C     DGMs%
668
1E
669

670
"FGI%
671

672
!G
673

674
"HG9       H%                 G9        Ht%
675

676

677
G9        H=%                 G9        H%                 G9        G%                         G9 G %    IJK
678
Gcpu/execute.vhdL       MNOPQRS@A_x
679
680
A
681
T
682
U
683
@RNOP
684
 S     QG
685
KUT
686
7V
687
!
688
A WXG9A
689
 
690
c
691
"
692
#G9A
693
$
694
a
695
 
696
|K
697
!
698
!Y
699
!
700
@ Z[G9K
701
%
702
         
703
&G9ߊ K       G9)K               G9K                G9_K                G9K                        G  K       \]^_`ab^x
704
705

706
c
707
d
708
 
709
 b     `G        Jdc
710
7e
711
!
712
'(fG9
713
"
714
c
715
"
716
#G9

717
$
718
a
719
$       G  J
720
!
721
!g
722
!
723
'(hG9J
724
%
725
         
726
&G9߫ J       G9SJ               G9J                G9ފJ                G9(J                        G  J       ijklmno\x
727
728

729
p
730
q
731
njkl
732
 o     mG        Iqp
733
7r
734
!
735
"sG9
736
"
737
 
738
"
739
#G9
740
$
741
a
742
$       G  I
743
 
744
!t
745
!
746
"uG9lI
747
%
748
         
749
&G9- I       G9I               G9пI                G9ЅI                G9HI                        G  I    vwx
750
'GTcpu/decode.vhdyz{|}~>?_x
751
(?

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.