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fellnhofer |
//! **************************************************************************
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// Written by: Map J.36 on Tue Nov 13 12:05:43 2007
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//! **************************************************************************
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SCHEMATIC START;
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COMP "testout<0>" LOCATE = SITE "F12" LEVEL 1;
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COMP "clk" LOCATE = SITE "C9" LEVEL 1;
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COMP "testout<1>" LOCATE = SITE "E12" LEVEL 1;
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COMP "testout<2>" LOCATE = SITE "E11" LEVEL 1;
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COMP "testout<3>" LOCATE = SITE "F11" LEVEL 1;
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COMP "testout<4>" LOCATE = SITE "C11" LEVEL 1;
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COMP "testout<5>" LOCATE = SITE "D11" LEVEL 1;
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COMP "testout<6>" LOCATE = SITE "E9" LEVEL 1;
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COMP "testout<7>" LOCATE = SITE "F9" LEVEL 1;
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COMP "rx" LOCATE = SITE "U8" LEVEL 1;
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COMP "tx" LOCATE = SITE "M13" LEVEL 1;
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COMP "reset" LOCATE = SITE "L13" LEVEL 1;
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NET "clk_BUFGP/IBUFG" BEL "clk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
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TIMEGRP clk = BEL "wr_data_6" BEL "mem_add_0" BEL "mem_add_1" BEL "mem_add_2"
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BEL "mem_add_3" BEL "mem_add_4" BEL "mem_add_5" BEL "mem_add_6" BEL
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"mem_add_7" BEL "mem_add_8" BEL "mem_add_9" BEL "wr_data_7" BEL
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"wr_gen" BEL "mem_hi" BEL "mode_0" BEL "mem_we" BEL "rd_gen" BEL
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"wr_data_0" BEL "wr_data_1" BEL "wr_data_2" BEL "wr_data_3" BEL
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"wr_data_4" BEL "addr_0" BEL "wr_data_5" BEL "mem_din_7" BEL
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"mem_din_8" BEL "mem_din_9" BEL "mem_din_10" BEL "mem_din_11" BEL
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"mem_din_12" BEL "mem_din_13" BEL "mem_din_14" BEL "mem_din_15" BEL
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"mem_din_0" BEL "mem_din_1" BEL "mem_din_2" BEL "mem_din_3" BEL
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"mem_din_4" BEL "mem_din_5" BEL "mem_din_6" BEL "testout_0" BEL
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"testout_1" BEL "testout_2" BEL "testout_3" BEL "testout_4" BEL
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"testout_5" BEL "testout_6" BEL "testout_7" BEL "state_FFd4" BEL
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"state_FFd3" BEL "state_FFd2" BEL "state_FFd1" BEL "sc_uartc/clktx_3"
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BEL "sc_uartc/clktx_2" BEL "sc_uartc/clktx_1" BEL "sc_uartc/clktx_0"
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BEL "sc_uartc/clkrx_3" BEL "sc_uartc/clkrx_2" BEL "sc_uartc/clkrx_1"
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BEL "sc_uartc/clkrx_0" BEL "sc_uartc/i_3" BEL "sc_uartc/i_2" BEL
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"sc_uartc/i_1" BEL "sc_uartc/i_0" BEL "sc_uartc/clk16_31" BEL
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"sc_uartc/clk16_30" BEL "sc_uartc/clk16_29" BEL "sc_uartc/clk16_28"
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BEL "sc_uartc/clk16_27" BEL "sc_uartc/clk16_26" BEL
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"sc_uartc/clk16_25" BEL "sc_uartc/clk16_24" BEL "sc_uartc/clk16_23"
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BEL "sc_uartc/clk16_22" BEL "sc_uartc/clk16_21" BEL
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"sc_uartc/clk16_20" BEL "sc_uartc/clk16_19" BEL "sc_uartc/clk16_18"
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BEL "sc_uartc/clk16_17" BEL "sc_uartc/clk16_16" BEL
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"sc_uartc/clk16_15" BEL "sc_uartc/clk16_14" BEL "sc_uartc/clk16_13"
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BEL "sc_uartc/clk16_12" BEL "sc_uartc/clk16_11" BEL
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"sc_uartc/clk16_10" BEL "sc_uartc/clk16_9" BEL "sc_uartc/clk16_8" BEL
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"sc_uartc/clk16_7" BEL "sc_uartc/clk16_6" BEL "sc_uartc/clk16_5" BEL
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"sc_uartc/clk16_4" BEL "sc_uartc/clk16_3" BEL "sc_uartc/clk16_2" BEL
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"sc_uartc/clk16_1" BEL "sc_uartc/clk16_0" BEL
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"sc_uartc/uart_rx_state_FFd1" BEL "sc_uartc/uart_rx_state_FFd2" BEL
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"sc_uartc/cmp_tf/g1[0].f1/f" BEL "sc_uartc/cmp_tf/g1[0].f1/buf_7" BEL
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"sc_uartc/cmp_tf/g1[0].f1/buf_6" BEL "sc_uartc/cmp_tf/g1[0].f1/buf_5"
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BEL "sc_uartc/cmp_tf/g1[0].f1/buf_4" BEL
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"sc_uartc/cmp_tf/g1[0].f1/buf_3" BEL "sc_uartc/cmp_tf/g1[0].f1/buf_2"
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BEL "sc_uartc/cmp_tf/g1[0].f1/buf_1" BEL
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"sc_uartc/cmp_tf/g1[0].f1/buf_0" BEL "sc_uartc/cmp_rf/g1[0].f1/f" BEL
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"sc_uartc/cmp_rf/g1[0].f1/buf_7" BEL "sc_uartc/cmp_rf/g1[0].f1/buf_6"
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BEL "sc_uartc/cmp_rf/g1[0].f1/buf_5" BEL
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"sc_uartc/cmp_rf/g1[0].f1/buf_4" BEL "sc_uartc/cmp_rf/g1[0].f1/buf_3"
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BEL "sc_uartc/cmp_rf/g1[0].f1/buf_2" BEL
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"sc_uartc/cmp_rf/g1[0].f1/buf_1" BEL "sc_uartc/cmp_rf/g1[0].f1/buf_0"
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BEL "sc_uartc/rsr_0" BEL "sc_uartc/rsr_1" BEL "sc_uartc/rsr_2" BEL
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"sc_uartc/rsr_3" BEL "sc_uartc/rsr_4" BEL "sc_uartc/rsr_5" BEL
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"sc_uartc/rsr_6" BEL "sc_uartc/rsr_7" BEL "sc_uartc/rsr_8" BEL
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"sc_uartc/rsr_9" BEL "sc_uartc/rx_buf_2" BEL "sc_uartc/rx_buf_1" BEL
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"sc_uartc/rx_buf_0" BEL "sc_uartc/ncts_buf_2" BEL
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"sc_uartc/ncts_buf_1" BEL "sc_uartc/tsr_6" BEL "sc_uartc/tsr_5" BEL
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"sc_uartc/i0_3" BEL "sc_uartc/i0_2" BEL "sc_uartc/i0_1" BEL
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"sc_uartc/i0_0" BEL "sc_uartc/tsr_4" BEL "sc_uartc/tsr_3" BEL
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"sc_uartc/tsr_2" BEL "sc_uartc/tsr_1" BEL "sc_uartc/tsr_0" BEL
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"sc_uartc/tx_clk" BEL "sc_uartc/uart_tx_state_0" BEL "sc_uartc/ua_rd"
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BEL "sc_uartc/tf_rd" BEL "sc_uartc/rd_data_7" BEL "sc_uartc/rd_data_6"
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BEL "sc_uartc/rd_data_5" BEL "sc_uartc/rd_data_4" BEL
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"sc_uartc/rx_clk_ena" BEL "sc_uartc/ncts_buf_0" BEL
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"sc_uartc/rd_data_3" BEL "sc_uartc/rd_data_2" BEL "sc_uartc/rd_data_0"
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BEL "sc_uartc/rd_data_1" BEL "sc_uartc/rf_wr" BEL "sc_uartc/rx_clk"
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BEL "sc_uartc/tsr_9" BEL "sc_uartc/tsr_8" BEL "sc_uartc/tsr_7" BEL
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"sc_uartc/Mshreg_rxd_reg_2" BEL "sc_uartc/rxd_reg_2" BEL "pmemc/B6.A";
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NET "clk_BUFGP/IBUFG" PERIOD = 25 ns HIGH 50%;
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SCHEMATIC END;
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