Subversion Repositories diogenes

Release 9.2i - xst J.36

Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

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Reading design: sio.prj

TABLE OF CONTENTS

  1) Synthesis Options Summary

  2) HDL Compilation

  3) Design Hierarchy Analysis

  4) HDL Analysis

  5) HDL Synthesis

     5.1) HDL Synthesis Report

  6) Advanced HDL Synthesis

     6.1) Advanced HDL Synthesis Report

  7) Low Level Synthesis

  8) Partition Report

  9) Final Report

     9.1) Device utilization summary

     9.2) Partition Resource Summary

     9.3) TIMING REPORT

=========================================================================

*                      Synthesis Options Summary                        *

=========================================================================

---- Source Parameters

Input File Name                    : "sio.prj"

Input Format                       : mixed

Ignore Synthesis Constraint File   : NO

---- Target Parameters

Output File Name                   : "sio"

Output Format                      : NGC

Target Device                      : xc3s500e-5-fg320

---- Source Options

Top Module Name                    : sio

Automatic FSM Extraction           : YES

FSM Encoding Algorithm             : Auto

Safe Implementation                : No

FSM Style                          : lut

RAM Extraction                     : Yes

RAM Style                          : Auto

ROM Extraction                     : Yes

Mux Style                          : Auto

Decoder Extraction                 : YES

Priority Encoder Extraction        : YES

Shift Register Extraction          : YES

Logical Shifter Extraction         : YES

XOR Collapsing                     : YES

ROM Style                          : Auto

Mux Extraction                     : YES

Resource Sharing                   : YES

Asynchronous To Synchronous        : NO

Multiplier Style                   : auto

Automatic Register Balancing       : No

---- Target Options

Add IO Buffers                     : YES

Global Maximum Fanout              : 500

Add Generic Clock Buffer(BUFG)     : 24

Register Duplication               : YES

Slice Packing                      : YES

Optimize Instantiated Primitives   : NO

Use Clock Enable                   : Yes

Use Synchronous Set                : Yes

Use Synchronous Reset              : Yes

Pack IO Registers into IOBs        : auto

Equivalent register Removal        : YES

---- General Options

Optimization Goal                  : Speed

Optimization Effort                : 1

Library Search Order               : sio.lso

Keep Hierarchy                     : NO

RTL Output                         : Yes

Global Optimization                : AllClockNets

Read Cores                         : YES

Write Timing Constraints           : NO

Cross Clock Analysis               : NO

Hierarchy Separator                : /

Bus Delimiter                      : <>

Case Specifier                     : maintain

Slice Utilization Ratio            : 100

BRAM Utilization Ratio             : 100

Verilog 2001                       : YES

Auto BRAM Packing                  : NO

Slice Utilization Ratio Delta      : 5

=========================================================================

=========================================================================

*                          HDL Compilation                              *

=========================================================================

WARNING:HDLParsers:3607 - Unit work/mysio is now defined in a different file.  It was defined in "/home/andi/xilinx/rs232/sio.vhdl", and is now defined in "/home/andi/xilinx/rs232/sio.vhd".

WARNING:HDLParsers:3607 - Unit work/sio/Behavioral is now defined in a different file.  It was defined in "/home/andi/xilinx/rs232/sio.vhdl", and is now defined in "/home/andi/xilinx/rs232/sio.vhd".

WARNING:HDLParsers:3516 - Found error in file "/home/andi/xilinx/rs232/sio.vhd".

WARNING:HDLParsers:3458 - Because of erroneous VHDL file(s), automatic determination of correct order of compilation of files in project file "/home/andi/xilinx/rs232/sio_vhdl.prj" may be inaccurate. Please put the files in the project file in correct order with keyword 'nosort' at end of the project file, or compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s).

Compiling vhdl file "/home/andi/xilinx/rs232/types.vhd" in Library work.

Architecture types of Entity types is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/cpu/alu.vhd" in Library work.

Architecture behavioral of Entity alu is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/cpu/cmp.vhd" in Library work.

Architecture behavioral of Entity cmp is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/cpu/regfile.vhd" in Library work.

Architecture behavioral of Entity regfile is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/pmem.vhd" in Library work.

Architecture pmem_a of Entity pmem is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/cpu/fetch.vhd" in Library work.

Architecture behavioral of Entity fetch is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/cpu/decode.vhd" in Library work.

Architecture behavioral of Entity decode is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/cpu/execute.vhd" in Library work.

Architecture behavioral of Entity execute is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/fifo.vhd" in Library work.

Architecture rtl of Entity fifo_elem is up to date.

Architecture rtl of Entity fifo is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/sc_uart.vhd" in Library work.

Architecture rtl of Entity sc_uart is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/cpu/cpu.vhd" in Library work.

Architecture behavioral of Entity cpu is up to date.

Compiling vhdl file "/home/andi/xilinx/rs232/sio.vhd" in Library work.

Entity  compiled.

ERROR:HDLParsers:3312 - "/home/andi/xilinx/rs232/sio.vhd" Line 79. Undefined symbol 'slv_32'.

ERROR:HDLParsers:1209 - "/home/andi/xilinx/rs232/sio.vhd" Line 79. slv_32: Undefined symbol (last report in this block)

ERROR:HDLParsers:1202 - "/home/andi/xilinx/rs232/sio.vhd" Line 83. Redeclaration of symbol mem_addr.

ERROR:HDLParsers:3312 - "/home/andi/xilinx/rs232/sio.vhd" Line 84. Undefined symbol 'slv_16'.

ERROR:HDLParsers:1209 - "/home/andi/xilinx/rs232/sio.vhd" Line 84. slv_16: Undefined symbol (last report in this block)

ERROR:HDLParsers:3312 - "/home/andi/xilinx/rs232/sio.vhd" Line 116. Undefined symbol 'slv_16'.

ERROR:HDLParsers:1209 - "/home/andi/xilinx/rs232/sio.vhd" Line 116. slv_16: Undefined symbol (last report in this block)

ERROR:HDLParsers:3312 - "/home/andi/xilinx/rs232/sio.vhd" Line 119. Undefined symbol 'slv_8'.

ERROR:HDLParsers:1209 - "/home/andi/xilinx/rs232/sio.vhd" Line 119. slv_8: Undefined symbol (last report in this block)

ERROR:HDLParsers:164 - "/home/andi/xilinx/rs232/sio.vhd" Line 125. parse error, unexpected IDENTIFIER, expecting COMMA or COLON

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Total memory usage is 98980 kilobytes

Number of errors   :   10 (   0 filtered)

Number of warnings :    4 (   0 filtered)

Number of infos    :    0 (   0 filtered)