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1 154 fellnhofer
Release 9.2i Map J.36
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Xilinx Mapping Report File for Design 'sio'
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Design Information
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------------------
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Command Line   : map -ise /home/andi/xilinx/rs232/rs232.ise -intstyle ise -p
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xc3s500e-fg320-5 -cm area -pr b -k 4 -c 100 -o sio_map.ncd sio.ngd sio.pcf
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Target Device  : xc3s500e
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Target Package : fg320
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Target Speed   : -5
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Mapper Version : spartan3e -- $Revision: 1.1.1.1 $
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Mapped Date    : Tue Nov 13 12:05:41 2007
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Design Summary
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--------------
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Number of errors:      0
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Number of warnings:    2
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Logic Utilization:
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  Number of Slice Flip Flops:         153 out of   9,312    1%
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  Number of 4 input LUTs:             171 out of   9,312    1%
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Logic Distribution:
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  Number of occupied Slices:                          140 out of   4,656    3%
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    Number of Slices containing only related logic:     140 out of     140  100%
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    Number of Slices containing unrelated logic:          0 out of     140    0%
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      *See NOTES below for an explanation of the effects of unrelated logic
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Total Number of 4 input LUTs:            212 out of   9,312    2%
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  Number used as logic:                171
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  Number used as a route-thru:          40
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  Number used as Shift registers:        1
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  Number of bonded IOBs:               12 out of     232    5%
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    IOB Flip Flops:                     9
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  Number of Block RAMs:                1 out of      20    5%
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  Number of GCLKs:                     1 out of      24    4%
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Total equivalent gate count for design:  68,222
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Additional JTAG gate count for IOBs:  576
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Peak Memory Usage:  145 MB
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Total REAL time to MAP completion:  3 secs
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Total CPU time to MAP completion:   3 secs
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NOTES:
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   Related logic is defined as being logic that shares connectivity - e.g. two
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   LUTs are "related" if they share common inputs.  When assembling slices,
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   Map gives priority to combine logic that is related.  Doing so results in
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   the best timing performance.
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   Unrelated logic shares no connectivity.  Map will only begin packing
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   unrelated logic into a slice once 99% of the slices are occupied through
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   related logic packing.
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   Note that once logic distribution reaches the 99% level through related
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   logic packing, this does not mean the device is completely utilized.
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   Unrelated logic packing will then begin, continuing until all usable LUTs
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   and FFs are occupied.  Depending on your timing budget, increased levels of
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   unrelated logic packing may adversely affect the overall timing performance
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   of your design.
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group and Partition Summary
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Section 10 - Modular Design Summary
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Section 11 - Timing Report
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Section 12 - Configuration String Information
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Section 13 - Control Set Information
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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WARNING:LIT:243 - Logical network mem_wr has no load.
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WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 3
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   more times for the following (max. 5 shown):
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   mem_data,
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   mem_en,
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   mem_addr
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   To see the details of these warning messages, please use the -detail switch.
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Section 3 - Informational
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-------------------------
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INFO:MapLib:562 - No environment variables are currently set.
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INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to
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   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
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   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)
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INFO:MapLib:159 - Net Timing constraints on signal clk are pushed forward
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   through input buffer.
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INFO:LIT:244 - All of the single ended outputs in this design are using slew
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   rate limited output drivers. The delay on speed critical single ended outputs
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   can be dramatically reduced by designating them as fast outputs in the
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   schematic.
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Section 4 - Removed Logic Summary
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---------------------------------
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   4 block(s) optimized away
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Section 5 - Removed Logic
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-------------------------
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Optimized Block(s):
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TYPE            BLOCK
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GND             XST_GND
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VCC             XST_VCC
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GND             pmemc/GND
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VCC             pmemc/VCC
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To enable printing of redundant blocks removed and signals merged, set the
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detailed map report option and rerun map.
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Section 6 - IOB Properties
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--------------------------
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+-----------------------------------------------------------------------------------------------------------------------------------------+
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| IOB Name                           | IOB Type         | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IBUF/IFD  |
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|                                    |                  |           |             | Strength | Rate |              |          | Delay     |
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+-----------------------------------------------------------------------------------------------------------------------------------------+
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| clk                                | IBUF             | INPUT     | LVTTL       |          |      |              |          | 0 / 0     |
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| reset                              | IBUF             | INPUT     | LVTTL       |          |      |              | PULLUP   | 0 / 0     |
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| rx                                 | IBUF             | INPUT     | LVTTL       |          |      |              |          | 0 / 0     |
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| testout<0>                         | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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| testout<1>                         | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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| testout<2>                         | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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| testout<3>                         | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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| testout<4>                         | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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| testout<5>                         | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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| testout<6>                         | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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| testout<7>                         | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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| tx                                 | IOB              | OUTPUT    | LVTTL       | 4        | SLOW | OFF1         |          | 0 / 0     |
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+-----------------------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group and Partition Summary
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--------------------------------------------
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Partition Implementation Status
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-------------------------------
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  No Partitions were found in this design.
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-------------------------------
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Area Group Information
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----------------------
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  No area groups were found in this design.
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----------------------
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Section 10 - Modular Design Summary
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-----------------------------------
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Modular Design not used for this design.
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Section 11 - Timing Report
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--------------------------
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This design was not run using timing mode.
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Section 12 - Configuration String Details
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-----------------------------------------
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Use the "-detail" map option to print out Configuration Strings
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Section 13 - Control Set Information
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------------------------------------
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No control set information for this architecture.

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