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[/] [diogenes/] [trunk/] [vhdl/] [templates/] [coregen.xml] - Blame information for rev 236

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-- The following code must appear in the VHDL architecture header:
 
component video_ram
    port (
    addra: IN std_logic_VECTOR(12 downto 0);
    addrb: IN std_logic_VECTOR(12 downto 0);
    clka: IN std_logic;
    clkb: IN std_logic;
    dinb: IN std_logic_VECTOR(7 downto 0);
    douta: OUT std_logic_VECTOR(7 downto 0);
    web: IN std_logic);
end component;
 
 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : video_ram
        port map (
            addra => addra,
            addrb => addrb,
            clka => clka,
            clkb => clkb,
            dinb => dinb,
            douta => douta,
            web => web);
 
                
        




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Line No.	Rev	Author	Line
1	212	fellnhofer
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19			`-- The following code must appear in the VHDL architecture header:`
20
21			`component video_ram`
22			`port (`
23			`addra: IN std_logic_VECTOR(12 downto 0);`
24			`addrb: IN std_logic_VECTOR(12 downto 0);`
25			`clka: IN std_logic;`
26			`clkb: IN std_logic;`
27			`dinb: IN std_logic_VECTOR(7 downto 0);`
28			`douta: OUT std_logic_VECTOR(7 downto 0);`
29			`web: IN std_logic);`
30			`end component;`
31
32
33			`-------------------------------------------------------------`
34
35			`-- The following code must appear in the VHDL architecture body.`
36			`-- Substitute your own instance name and net names.`
37
38			`your_instance_name : video_ram`
39			`port map (`
40			`addra => addra,`
41			`addrb => addrb,`
42			`clka => clka,`
43			`clkb => clkb,`
44			`dinb => dinb,`
45			`douta => douta,`
46			`web => web);`
47
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49
50

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[/] [diogenes/] [trunk/] [vhdl/] [templates/] [coregen.xml] - Blame information for rev 236