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fellnhofer |
##############################################################
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#
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# Xilinx Core Generator version J.36
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# Date: Mon Jan 28 19:09:12 2008
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = False
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SET asysymbol = False
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc3s500e
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SET devicefamily = spartan3e
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SET flowvendor = Other
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = fg320
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -4
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SET verilogsim = False
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SET vhdlsim = True
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# END Project Options
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# BEGIN Select
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SELECT Dual_Port_Block_Memory family Xilinx,_Inc. 6.3
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# END Select
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# BEGIN Parameters
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CSET coefficient_file=/home/andi/xilinx/rs232/vga/video_ram.coe
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CSET component_name=video_ram
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CSET configuration_port_a=Read_Only
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CSET configuration_port_b=Write_Only
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CSET depth_a=8192
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CSET depth_b=8192
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CSET disable_warning_messages=true
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CSET global_init_value=0
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CSET load_init_file=true
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CSET port_a_active_clock_edge=Rising_Edge_Triggered
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CSET port_a_additional_output_pipe_stages=0
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CSET port_a_enable_pin=false
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CSET port_a_enable_pin_polarity=Active_High
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CSET port_a_handshaking_pins=false
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CSET port_a_init_pin=false
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CSET port_a_init_value=0
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CSET port_a_initialization_pin_polarity=Active_High
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CSET port_a_register_inputs=false
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CSET port_a_write_enable_polarity=Active_High
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CSET port_b_active_clock_edge=Rising_Edge_Triggered
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CSET port_b_additional_output_pipe_stages=0
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CSET port_b_enable_pin=false
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CSET port_b_enable_pin_polarity=Active_High
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CSET port_b_handshaking_pins=false
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CSET port_b_init_pin=false
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CSET port_b_init_value=0
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CSET port_b_initialization_pin_polarity=Active_High
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CSET port_b_register_inputs=false
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CSET port_b_write_enable_polarity=Active_High
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CSET primitive_selection=Optimize_For_Area
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CSET select_primitive=16kx1
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CSET width_a=8
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CSET width_b=8
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CSET write_mode_port_a=Read_After_Write
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CSET write_mode_port_b=Read_After_Write
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# END Parameters
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GENERATE
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# CRC: abce57
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