Subversion Repositories dirac

Release 7.1.04i - xst H.42

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

--> Parameter TMPDIR set to __projnav

CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s

--> Parameter xsthdpdir set to ./xst

CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s

--> Reading design: fifo.prj

TABLE OF CONTENTS

  1) Synthesis Options Summary

  2) HDL Compilation

  3) HDL Analysis

  4) HDL Synthesis

  5) Advanced HDL Synthesis

     5.1) HDL Synthesis Report

  6) Low Level Synthesis

  7) Final Report

     7.1) Device utilization summary

     7.2) TIMING REPORT

=========================================================================

*                      Synthesis Options Summary                        *

=========================================================================

---- Source Parameters

Input File Name                    : "fifo.prj"

Input Format                       : mixed

Ignore Synthesis Constraint File   : NO

---- Target Parameters

Output File Name                   : "fifo"

Output Format                      : NGC

Target Device                      : xc2v250-6-cs144

---- Source Options

Top Module Name                    : fifo

Automatic FSM Extraction           : YES

FSM Encoding Algorithm             : Auto

FSM Style                          : lut

RAM Extraction                     : Yes

RAM Style                          : Auto

ROM Extraction                     : Yes

ROM Style                          : Auto

Mux Extraction                     : YES

Mux Style                          : Auto

Decoder Extraction                 : YES

Priority Encoder Extraction        : YES

Shift Register Extraction          : YES

Logical Shifter Extraction         : YES

XOR Collapsing                     : YES

Resource Sharing                   : YES

Multiplier Style                   : auto

Automatic Register Balancing       : No

---- Target Options

Add IO Buffers                     : YES

Global Maximum Fanout              : 500

Add Generic Clock Buffer(BUFG)     : 16

Register Duplication               : YES

Equivalent register Removal        : YES

Slice Packing                      : YES

Pack IO Registers into IOBs        : auto

---- General Options

Optimization Goal                  : Speed

Optimization Effort                : 1

Keep Hierarchy                     : NO

Global Optimization                : AllClockNets

RTL Output                         : Yes

Write Timing Constraints           : NO

Hierarchy Separator                : _

Bus Delimiter                      : <>

Case Specifier                     : maintain

Slice Utilization Ratio            : 100

Slice Utilization Ratio Delta      : 5

---- Other Options

lso                                : fifo.lso

Read Cores                         : YES

cross_clock_analysis               : NO

verilog2001                        : YES

safe_implementation                : No

Optimize Instantiated Primitives   : NO

tristate2logic                     : Yes

use_clock_enable                   : Yes

use_sync_set                       : Yes

use_sync_reset                     : Yes

enable_auto_floorplanning          : No

=========================================================================

=========================================================================

*                          HDL Compilation                              *

=========================================================================

Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" in Library work.

Architecture rtl of Entity fifo is up to date.

=========================================================================

*                            HDL Analysis                               *

=========================================================================

Analyzing Entity  (Architecture ).

ERROR:Xst:834 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" line 13: Generic  has not been given a value.

-->

Total memory usage is 77708 kilobytes

Number of errors   :    1 (   0 filtered)

Number of warnings :    0 (   0 filtered)

Number of infos    :    0 (   0 filtered)