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Release 7.1.04i - xst H.42

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

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--> Reading design: updater.prj

TABLE OF CONTENTS

  1) Synthesis Options Summary

  2) HDL Compilation

  3) HDL Analysis

  4) HDL Synthesis

  5) Advanced HDL Synthesis

     5.1) HDL Synthesis Report

  6) Low Level Synthesis

  7) Final Report

     7.1) Device utilization summary

     7.2) TIMING REPORT

=========================================================================

*                      Synthesis Options Summary                        *

=========================================================================

---- Source Parameters

Input File Name                    : "updater.prj"

Input Format                       : mixed

Ignore Synthesis Constraint File   : NO

---- Target Parameters

Output File Name                   : "updater"

Output Format                      : NGC

Target Device                      : xc2v2000-6-bg575

---- Source Options

Top Module Name                    : updater

Automatic FSM Extraction           : YES

FSM Encoding Algorithm             : Auto

FSM Style                          : lut

RAM Extraction                     : Yes

RAM Style                          : Auto

ROM Extraction                     : Yes

ROM Style                          : Auto

Mux Extraction                     : YES

Mux Style                          : Auto

Decoder Extraction                 : YES

Priority Encoder Extraction        : YES

Shift Register Extraction          : YES

Logical Shifter Extraction         : YES

XOR Collapsing                     : YES

Resource Sharing                   : YES

Multiplier Style                   : auto

Automatic Register Balancing       : No

---- Target Options

Add IO Buffers                     : YES

Global Maximum Fanout              : 500

Add Generic Clock Buffer(BUFG)     : 16

Register Duplication               : YES

Equivalent register Removal        : YES

Slice Packing                      : YES

Pack IO Registers into IOBs        : auto

---- General Options

Optimization Goal                  : Speed

Optimization Effort                : 2

Keep Hierarchy                     : NO

Global Optimization                : AllClockNets

RTL Output                         : Yes

Write Timing Constraints           : NO

Hierarchy Separator                : _

Bus Delimiter                      : <>

Case Specifier                     : maintain

Slice Utilization Ratio            : 100

Slice Utilization Ratio Delta      : 5

---- Other Options

lso                                : updater.lso

Read Cores                         : YES

cross_clock_analysis               : NO

verilog2001                        : YES

safe_implementation                : No

Optimize Instantiated Primitives   : NO

tristate2logic                     : Yes

use_clock_enable                   : Yes

use_sync_set                       : Yes

use_sync_reset                     : Yes

enable_auto_floorplanning          : No

=========================================================================

=========================================================================

*                          HDL Compilation                              *

=========================================================================

Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work.

Entity  compiled.

Entity  (Architecture ) compiled.

=========================================================================

*                            HDL Analysis                               *

=========================================================================

Analyzing Entity  (Architecture ).

Entity  analyzed. Unit  generated.

=========================================================================

*                           HDL Synthesis                               *

=========================================================================

Synthesizing Unit .

    Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd".

    Found 8-bit 4-to-1 multiplexer for signal .

    Found 8-bit 4-to-1 multiplexer for signal .

    Found 1-bit register for signal .

    Found 8-bit adder for signal <$n0009> created at line 50.

    Found 8-bit adder for signal <$n0011> created at line 72.

    Found 8-bit adder for signal <$n0012> created at line 83.

    Found 8-bit adder for signal <$n0013> created at line 61.

    Found 8-bit register for signal .

    Found 8-bit register for signal .

    Found 8-bit register for signal .

    Found 8-bit register for signal .

    Found 8-bit register for signal .

    Found 1-bit xor2 for signal .

    Summary:

        inferred   1 D-type flip-flop(s).

        inferred   4 Adder/Subtractor(s).

        inferred  16 Multiplexer(s).

Unit  synthesized.

=========================================================================

*                       Advanced HDL Synthesis                          *

=========================================================================

Advanced RAM inference ...

Advanced multiplier inference ...

Advanced Registered AddSub inference ...

Dynamic shift register inference ...

=========================================================================

HDL Synthesis Report

Macro Statistics

# Adders/Subtractors               : 4

 8-bit adder                       : 4

# Registers                        : 6

 1-bit register                    : 1

 8-bit register                    : 5

# Multiplexers                     : 2

 8-bit 4-to-1 multiplexer          : 2

# Xors                             : 1

 1-bit xor2                        : 1

=========================================================================

=========================================================================

*                         Low Level Synthesis                           *

=========================================================================

Optimizing unit  ...

Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block updater, actual ratio is 0.

=========================================================================

*                            Final Report                               *

=========================================================================

Final Results

RTL Top Level Output File Name     : updater.ngr

Top Level Output File Name         : updater

Output Format                      : NGC

Optimization Goal                  : Speed

Keep Hierarchy                     : NO

Design Statistics

# IOs                              : 37

Macro Statistics :

# Registers                        : 41

#      1-bit register              : 41

# Multiplexers                     : 2

#      8-bit 4-to-1 multiplexer    : 2

# Adders/Subtractors               : 4

#      8-bit adder                 : 4

Cell Usage :

# BELS                             : 123

#      GND                         : 1

#      INV                         : 3

#      LUT1                        : 27

#      LUT2                        : 2

#      LUT3                        : 6

#      LUT4                        : 20

#      MUXCY                       : 28

#      MUXF5                       : 8

#      VCC                         : 1

#      XORCY                       : 27

# FlipFlops/Latches                : 41

#      FDR                         : 36

#      FDS                         : 5

# Clock Buffers                    : 1

#      BUFGP                       : 1

# IO Buffers                       : 36

#      IBUF                        : 19

#      OBUF                        : 17

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 2v2000bg575-6

 Number of Slices:                      32  out of  10752     0%

 Number of Slice Flip Flops:            41  out of  21504     0%

 Number of 4 input LUTs:                55  out of  21504     0%

 Number of bonded IOBs:                 37  out of    408     9%

 Number of GCLKs:                        1  out of     16     6%

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal                       | Clock buffer(FF name)  | Load  |

-----------------------------------+------------------------+-------+

CLOCK                              | BUFGP                  | 41    |

-----------------------------------+------------------------+-------+

Timing Summary:

---------------

Speed Grade: -6

   Minimum period: No path found

   Minimum input arrival time before clock: 5.430ns

   Maximum output required time after clock: 5.814ns

   Maximum combinational path delay: 8.314ns

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'

  Total number of paths / destination ports: 291 / 82

-------------------------------------------------------------------------

Offset:              5.430ns (Levels of Logic = 11)

  Source:            NUMERATOR<2> (PAD)

  Destination:       NUMERATOR4_7 (FF)

  Destination Clock: CLOCK rising

  Data Path: NUMERATOR<2> to NUMERATOR4_7

                                Gate     Net

    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

    ----------------------------------------  ------------

     IBUF:I->O             3   0.653   0.760  NUMERATOR_2_IBUF (NUMERATOR_2_IBUF)

     LUT1:I0->O            1   0.347   0.000  NUMERATOR_2_IBUF_rt1 (NUMERATOR_2_IBUF_rt1)

     MUXCY:S->O            1   0.235   0.000  updater__n0013<1>cy (updater__n0013<1>_cyo)

     MUXCY:CI->O           1   0.042   0.000  updater__n0013<2>cy (updater__n0013<2>_cyo)

     MUXCY:CI->O           1   0.042   0.000  updater__n0013<3>cy (updater__n0013<3>_cyo)

     MUXCY:CI->O           1   0.042   0.000  updater__n0013<4>cy (updater__n0013<4>_cyo)

     MUXCY:CI->O           1   0.042   0.000  updater__n0013<5>cy (updater__n0013<5>_cyo)

     XORCY:CI->O           2   0.824   0.744  updater__n0013<6>_xor (_n0013<6>)

     LUT1:I0->O            1   0.347   0.000  _n0013<6>_rt (_n0013<6>_rt)

     MUXCY:S->O            0   0.235   0.000  updater__n0011<6>cy (updater__n0011<6>_cyo)

     XORCY:CI->O           1   0.824   0.000  updater__n0011<7>_xor (_n0011<7>)

     FDR:D                     0.293          NUMERATOR4_7

    ----------------------------------------

    Total                      5.430ns (3.926ns logic, 1.504ns route)

                                       (72.3% logic, 27.7% route)

=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'

  Total number of paths / destination ports: 41 / 17

-------------------------------------------------------------------------

Offset:              5.814ns (Levels of Logic = 3)

  Source:            NUMERATOR2_7 (FF)

  Destination:       NUMERATOR_OUT<7> (PAD)

  Source Clock:      CLOCK rising

  Data Path: NUMERATOR2_7 to NUMERATOR_OUT<7>

                                Gate     Net

    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

    ----------------------------------------  ------------

     FDR:C->Q              1   0.449   0.548  NUMERATOR2_7 (NUMERATOR2_7)

     LUT4:I1->O            1   0.347   0.000  DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6_F (N25)

     MUXF5:I0->O           1   0.345   0.383  DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6 (NUMERATOR_OUT_7_OBUF)

     OBUF:I->O                 3.743          NUMERATOR_OUT_7_OBUF (NUMERATOR_OUT<7>)

    ----------------------------------------

    Total                      5.814ns (4.884ns logic, 0.930ns route)

                                       (84.0% logic, 16.0% route)

=========================================================================

Timing constraint: Default path analysis

  Total number of paths / destination ports: 204 / 16

-------------------------------------------------------------------------

Delay:               8.314ns (Levels of Logic = 5)

  Source:            DENOMINATOR<0> (PAD)

  Destination:       DENOMINATOR_OUT<1> (PAD)

  Data Path: DENOMINATOR<0> to DENOMINATOR_OUT<1>

                                Gate     Net

    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

    ----------------------------------------  ------------

     IBUF:I->O             2   0.653   0.743  DENOMINATOR_0_IBUF (DENOMINATOR_0_IBUF)

     LUT4:I0->O           23   0.347   1.007  _n00144 (CHOICE167)

     LUT2:I0->O            2   0.347   0.744  _n001410 (HALVE_VALUES)

     LUT4:I0->O            1   0.347   0.383  DENOMINATOR_OUT<1>1 (DENOMINATOR_OUT_1_OBUF)

     OBUF:I->O                 3.743          DENOMINATOR_OUT_1_OBUF (DENOMINATOR_OUT<1>)

    ----------------------------------------

    Total                      8.314ns (5.437ns logic, 2.877ns route)

                                       (65.4% logic, 34.6% route)

=========================================================================

CPU : 6.39 / 8.98 s | Elapsed : 7.00 / 9.00 s

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Total memory usage is 121148 kilobytes

Number of errors   :    0 (   0 filtered)

Number of warnings :    0 (   0 filtered)

Number of infos    :    0 (   0 filtered)