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petebleack |
-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
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--
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-- The contents of this file are subject to the Mozilla Public License
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-- Version 1.1 (the "License"); you may not use this file except in compliance
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-- with the License. You may obtain a copy of the License at
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-- http://www.mozilla.org/MPL/
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--
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-- Software distributed under the License is distributed on an "AS IS" basis,
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-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- the specific language governing rights and limitations under the License.
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--
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-- The Original Code is BBC Research and Development code.
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--
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-- The Initial Developer of the Original Code is the British Broadcasting
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-- Corporation.
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-- Portions created by the Initial Developer are Copyright (C) 2006.
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-- All Rights Reserved.
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--
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-- Contributor(s): Peter Bleackley (Original author)
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--
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-- Alternatively, the contents of this file may be used under the terms of
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-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- the GPL or the LGPL are applicable instead of those above. If you wish to
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-- allow use of your version of this file only under the terms of the either
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-- the GPL or LGPL and not to allow others to use your version of this file
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-- under the MPL, indicate your decision by deleting the provisions above
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-- and replace them with the notice and other provisions required by the GPL
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-- or LGPL. If you do not delete the provisions above, a recipient may use
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-- your version of this file under the terms of any one of the MPL, the GPL
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-- or the LGPL.
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-- * ***** END LICENSE BLOCK ***** */
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity HALVING_MANAGER is
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Port ( TRIGGER_HALVING : in std_logic;
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INPUT_READY : in std_logic;
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NUMERATOR_IN : in std_logic_vector(9 downto 0);
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DENOMINATOR_IN : in std_logic_vector(9 downto 0);
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CONTEXT : in std_logic_vector(5 downto 0);
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RESET : in std_logic;
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CLOCK : in std_logic;
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NUMERATOR_OUT : out std_logic_vector(9 downto 0);
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DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
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OUTPUT_READY : out std_logic);
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end HALVING_MANAGER;
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architecture RTL of HALVING_MANAGER is
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type COUNTARRAY is array(45 downto 0) of std_logic_vector(2 downto 0);
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signal SHIFTS : COUNTARRAY;
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signal NUMERATOR : std_logic_vector (9 downto 0);
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signal DENOMINATOR : std_logic_vector (9 downto 0);
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signal NUMERATOR2 : std_logic_vector (9 downto 0);
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signal DENOMINATOR2 : std_logic_vector (9 downto 0);
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signal DENOMINATOR_INCREMENT : std_logic_vector (9 downto 0);
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signal GREATER_THAN_16 : std_logic;
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signal PERFORM_HALVING : std_logic;
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signal AFTER_TRIGGER : std_logic;
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signal LOAD : std_logic;
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signal CALCULATE_VALUES : std_logic;
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begin
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COUNT_HALVING_EVENTS : process (CLOCK)
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begin
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if CLOCK'event and CLOCK = '1' then
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if RESET = '1' then
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SHIFTS <= (others => "000");
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elsif TRIGGER_HALVING = '1' then
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for I in 0 to 45 loop
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if SHIFTS(I) /= "111" then
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SHIFTS(I) <= SHIFTS(I) + "001";
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end if;
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end loop;
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elsif CALCULATE_VALUES = '1' then
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SHIFTS(conv_integer(CONTEXT)) <= SHIFTS(conv_integer(CONTEXT)) - "001";
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elsif GREATER_THAN_16 = '0' and LOAD = '0' and INPUT_READY = '1' then
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SHIFTS(conv_integer(CONTEXT)) <= "000";
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end if;
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end if;
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end process COUNT_HALVING_EVENTS;
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NUMERATOR2 <= ('0' & NUMERATOR (9 downto 1)) + "0000000001";
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DENOMINATOR2 <= ('0' & DENOMINATOR(9 downto 1)) + DENOMINATOR_INCREMENT;
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HALVE_COUNTS : process (CLOCK)
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begin
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if CLOCK'event and CLOCK='1' then
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if RESET = '1' then
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NUMERATOR <= "0000000001";
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DENOMINATOR <= "0000000010";
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elsif CALCULATE_VALUES = '1' then
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NUMERATOR <= NUMERATOR2;
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DENOMINATOR <= DENOMINATOR2;
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elsif LOAD = '1' then
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NUMERATOR <= NUMERATOR_IN;
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DENOMINATOR <= DENOMINATOR_IN;
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end if;
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end if;
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end process HALVE_COUNTS;
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HALVING_PERMITTED : process (DENOMINATOR)
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begin
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if DENOMINATOR > "0000010000" then
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GREATER_THAN_16 <= '1';
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else
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GREATER_THAN_16 <= '0';
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end if;
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end process HALVING_PERMITTED;
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HALVING_ACTIVE : process (INPUT_READY, SHIFTS, CONTEXT, GREATER_THAN_16)
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begin
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if INPUT_READY = '1' and (SHIFTS(conv_integer(CONTEXT)) > "000") then
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PERFORM_HALVING <= GREATER_THAN_16;
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else
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PERFORM_HALVING <= '0';
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end if;
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end process HALVING_ACTIVE;
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SELECT_OUTPUT : process (NUMERATOR_IN, DENOMINATOR_IN, NUMERATOR, DENOMINATOR, TRIGGER_HALVING, PERFORM_HALVING, LOAD)
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begin
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if (LOAD and (TRIGGER_HALVING nor PERFORM_HALVING)) = '1' then
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NUMERATOR_OUT <= NUMERATOR_IN;
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DENOMINATOR_OUT <= DENOMINATOR_IN;
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else
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NUMERATOR_OUT <= NUMERATOR;
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DENOMINATOR_OUT <= DENOMINATOR;
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end if;
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end process SELECT_OUTPUT;
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DELAY_TRIGGER : process (CLOCK)
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begin
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if CLOCK'event and CLOCK = '1' then
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if RESET = '1' then
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AFTER_TRIGGER <= '0';
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else
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AFTER_TRIGGER <= INPUT_READY;
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end if;
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end if;
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end process DELAY_TRIGGER;
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CHOOSE_DENOMINATOR_INCREMENT : process (NUMERATOR, DENOMINATOR)
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begin
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if (NUMERATOR (0) = '1') and (DENOMINATOR (0) = '0') then
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DENOMINATOR_INCREMENT <= "0000000001";
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else
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DENOMINATOR_INCREMENT <= "0000000010";
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end if;
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end process CHOOSE_DENOMINATOR_INCREMENT;
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LOAD <= INPUT_READY and not AFTER_TRIGGER;
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CALCULATE_VALUES <= PERFORM_HALVING and AFTER_TRIGGER;
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OUTPUT_READY <= INPUT_READY and (PERFORM_HALVING nor TRIGGER_HALVING);
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end RTL;
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