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petebleack |
-- ***** BEGIN LICENSE BLOCK *****
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petebleack |
--
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petebleack |
-- $Id: ARITHMETICCODER.vhd,v 1.4 2006-10-05 16:17:13 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- *
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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-- * The contents of this file are subject to the Mozilla Public License
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * with the License. You may obtain a copy of the License at
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-- * http://www.mozilla.org/MPL/
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-- *
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- * the specific language governing rights and limitations under the License.
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-- *
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-- * The Original Code is BBC Research and Development code.
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-- *
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- * Corporation.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * All Rights Reserved.
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-- *
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-- * Contributor(s): Peter Bleackley (Original author)
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-- *
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-- * Alternatively, the contents of this file may be used under the terms of
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * allow use of your version of this file only under the terms of the either
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-- * the GPL or LGPL and not to allow others to use your version of this file
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-- * under the MPL, indicate your decision by deleting the provisions above
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-- * and replace them with the notice and other provisions required by the GPL
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * or the LGPL.
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petebleack |
-- * ***** END LICENSE BLOCK ***** */
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ARITHMETICCODER is
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Port ( ENABLE : in std_logic;
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DATA_IN : in std_logic;
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CONTEXT_ENABLE : in std_logic;
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CONTEXT_IN : in std_logic_vector (5 downto 0);
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HALVECOUNTS_IN : in std_logic;
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FLUSH : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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SENDING : out std_logic;
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DATA_OUT : out std_logic;
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FLUSH_COMPLETE : out std_logic);
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petebleack |
end ARITHMETICCODER;
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architecture RTL of ARITHMETICCODER is
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petebleack |
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component LIMIT_REGISTER
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generic(CONST: std_logic);
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port( LOAD : in std_logic_vector(15 downto 0);
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SET_VALUE : in std_logic;
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SHIFT_ALL : in std_logic;
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SHIFT_MOST : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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OUTPUT : out std_logic_vector(15 downto 0));
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end component LIMIT_REGISTER;
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component FOLLOW_COUNTER
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port ( INCREMENT : in std_logic;
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TEST : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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OUTPUT : out std_logic);
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end component FOLLOW_COUNTER;
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component CONVERGENCE_CHECK
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port ( HIGH_MSB : in std_logic;
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LOW_MSB : in std_logic;
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HIGH_SECONDBIT : in std_logic;
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LOW_SECONDBIT : in std_logic;
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CHECK : in std_logic;
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TRIGGER_OUTPUT : out std_logic;
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TRIGGER_FOLLOW : out std_logic);
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end component CONVERGENCE_CHECK;
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component ARITHMETIC_UNIT
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port ( DIFFERENCE : in std_logic_vector(15 downto 0);
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PROB : in std_logic_vector(7 downto 0);
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LOW : in std_logic_vector(15 downto 0);
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ENABLE : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
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DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0);
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RESULT_OUT0 : out std_logic_vector(15 downto 0);
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RESULT_OUT1 : out std_logic_vector(15 downto 0);
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DATA_LOAD : out std_logic);
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end component ARITHMETIC_UNIT;
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component OUTPUT_UNIT
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port ( ENABLE : in std_logic;
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DATA : in std_logic;
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FOLLOW : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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SENDING : out std_logic;
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DATA_OUT : out std_logic;
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FOLLOW_COUNTER_TEST : out std_logic;
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SHIFT : out std_logic);
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end component OUTPUT_UNIT;
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component INPUT_CONTROL
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generic( WIDTH : integer range 1 to 16);
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port( ENABLE : in std_logic;
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DATA_IN : in std_logic_vector(WIDTH - 1 downto 0);
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BUFFER_CONTROL : in std_logic;
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DEMAND : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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SENDING : out std_logic;
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DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0));
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end component INPUT_CONTROL;
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component CONTEXT_MANAGER
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port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0);
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SET : in std_logic;
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UPDATE : in std_logic;
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DATA_IN : in std_logic;
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HALVECOUNTS : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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PROB : out std_logic_vector(7 downto 0);
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READY : out std_logic);
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petebleack |
end component CONTEXT_MANAGER;
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petebleack |
signal HIGH_SET : std_logic;
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signal LOW_SET : std_logic;
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signal TRIGGER_SHIFT : std_logic;
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signal SHIFT_ALL : std_logic;
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signal DIFFERENCE_SHIFT_ALL : std_logic;
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signal SHIFT_MOST : std_logic;
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signal ZERO_INPUT : std_logic;
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signal ARITHMETIC_UNIT_ENABLE : std_logic;
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signal ARITHMETIC_UNIT_DATA_LOAD : std_logic;
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signal CONVERGENCE_TEST : std_logic;
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signal TRIGGER_OUTPUT : std_logic;
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signal FOLLOW_COUNTER_TEST : std_logic;
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signal FOLLOW: std_logic;
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signal DATA_LOAD: std_logic;
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signal OUTPUT_ACTIVE : std_logic;
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signal CHECK : std_logic;
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signal DELAYED_CHECK : std_logic;
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signal DATA_AVAILABLE : std_logic;
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signal BUFFERED_DATA : std_logic;
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signal BUFFER_INPUT : std_logic;
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petebleack |
signal NEWCONTEXT : std_logic;
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signal ARITHMETIC_UNIT_DIFFERENCE_OUT0 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_DIFFERENCE_OUT1 : std_logic_vector(15 downto 0);
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signal DIFFERENCE_IN : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0);
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signal DIFFERENCE_OUT : std_logic_vector (15 downto 0);
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signal HIGH_OUT : std_logic_vector (15 downto 0);
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signal LOW_OUT : std_logic_vector (15 downto 0);
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signal PROB : std_logic_vector (7 downto 0);
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signal CONTEXT_SELECT : std_logic_vector (5 downto 0);
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signal PROB_AVAILABLE : std_logic;
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signal BUFFERCONTEXT : std_logic;
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signal DATA_IN2 : std_logic_vector(0 downto 0);
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signal BUFFERED_DATA2 : std_logic_vector(0 downto 0);
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signal CONTEXT_BUFFER_DATA_IN : std_logic_vector(7 downto 0);
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signal CONTEXT_BUFFER_DATA_OUT : std_logic_vector(7 downto 0);
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-- signal LAST_FIVE_TRIGGERS : std_logic_vector(4 downto 0);
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signal HALVECOUNTS : std_logic;
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signal BUFFERED_FLUSH : std_logic;
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signal FLUSH_ENCODER : std_logic;
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signal SWITCHED_DATA : std_logic;
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signal CONVERGED : std_logic;
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signal INCREMENT_FOLLOW : std_logic;
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signal ALLOWHALVING : std_logic;
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signal RELEASE_CONTEXT : std_logic;
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-- signal FETCH_FLUSH : std_logic;
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signal DEMAND_CONTEXT : std_logic;
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signal LOCK : std_logic;
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signal DEMAND_DATA : std_logic;
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signal HOLDCONTEXT : std_logic;
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petebleack |
begin
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-- input buffering
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INBUFFER: INPUT_CONTROL
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petebleack |
generic map(WIDTH => 1)
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port map(ENABLE => ENABLE,
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DATA_IN => DATA_IN2,
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BUFFER_CONTROL => BUFFER_INPUT,
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DEMAND => DEMAND_DATA,
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RESET => RESET,
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CLOCK => CLOCK,
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SENDING => DATA_AVAILABLE,
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DATA_OUT => BUFFERED_DATA2);
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DATA_IN2(0) <= DATA_IN;
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BUFFERED_DATA <= BUFFERED_DATA2(0);
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DEMAND_DATA <= ARITHMETIC_UNIT_DATA_LOAD and not LOCK;
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CONTEXT_BUFFER: INPUT_CONTROL
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generic map(WIDTH => 8)
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port map(ENABLE => CONTEXT_ENABLE,
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DATA_IN => CONTEXT_BUFFER_DATA_IN,
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BUFFER_CONTROL => BUFFERCONTEXT,
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DEMAND => DEMAND_CONTEXT,
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RESET => RESET,
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CLOCK => CLOCK,
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SENDING => NEWCONTEXT,
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DATA_OUT => CONTEXT_BUFFER_DATA_OUT);
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CONTEXT_BUFFER_DATA_IN <= (CONTEXT_IN & HALVECOUNTS_IN & FLUSH);
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CONTEXT_SELECT <= CONTEXT_BUFFER_DATA_OUT(7 downto 2);
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HALVECOUNTS <= CONTEXT_BUFFER_DATA_OUT(1) and ALLOWHALVING;
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BUFFERED_FLUSH <= CONTEXT_BUFFER_DATA_OUT(0) and CONVERGENCE_TEST and (CONVERGED nor SHIFT_MOST) and not LOCK;
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petebleack |
-- Specify the registers
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HIGH: LIMIT_REGISTER
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generic map(CONST => '1')
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port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT0,
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SET_VALUE => HIGH_SET,
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SHIFT_ALL => SHIFT_ALL,
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SHIFT_MOST => SHIFT_MOST,
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RESET => RESET,
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CLOCK => CLOCK,
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OUTPUT => HIGH_OUT);
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DIFFERENCE: LIMIT_REGISTER
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generic map(CONST => '1')
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port map( LOAD => DIFFERENCE_IN,
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SET_VALUE => DATA_LOAD,
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SHIFT_ALL => DIFFERENCE_SHIFT_ALL,
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SHIFT_MOST => '0',
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RESET => RESET,
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CLOCK => CLOCK,
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OUTPUT => DIFFERENCE_OUT);
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LOW: LIMIT_REGISTER
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generic map(CONST => '0')
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port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT1,
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SET_VALUE => LOW_SET,
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SHIFT_ALL => SHIFT_ALL,
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SHIFT_MOST => SHIFT_MOST,
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RESET => RESET,
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CLOCK => CLOCK,
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OUTPUT => LOW_OUT);
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-- The arithmetic
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ARITH: ARITHMETIC_UNIT
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port map(DIFFERENCE => DIFFERENCE_OUT,
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PROB => PROB,
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LOW => LOW_OUT,
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ENABLE => ARITHMETIC_UNIT_ENABLE,
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RESET => RESET,
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CLOCK => CLOCK,
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DIFFERENCE_OUT0 => ARITHMETIC_UNIT_DIFFERENCE_OUT0,
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DIFFERENCE_OUT1 => ARITHMETIC_UNIT_DIFFERENCE_OUT1,
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RESULT_OUT0 => ARITHMETIC_UNIT_RESULT_OUT0,
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RESULT_OUT1 => ARITHMETIC_UNIT_RESULT_OUT1,
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DATA_LOAD => ARITHMETIC_UNIT_DATA_LOAD);
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--The convergence checks
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CONVERGE: CONVERGENCE_CHECK
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port map(HIGH_MSB => HIGH_OUT(15),
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LOW_MSB => LOW_OUT(15),
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HIGH_SECONDBIT => HIGH_OUT(14),
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LOW_SECONDBIT => LOW_OUT(14),
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CHECK => CONVERGENCE_TEST,
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petebleack |
TRIGGER_OUTPUT => CONVERGED,
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TRIGGER_FOLLOW => SHIFT_MOST);
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TRIGGER_OUTPUT <= CONVERGED or FLUSH_ENCODER;
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petebleack |
--The Follow Counter
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FC: FOLLOW_COUNTER
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petebleack |
port map( INCREMENT => INCREMENT_FOLLOW,
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petebleack |
TEST => FOLLOW_COUNTER_TEST,
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RESET => RESET,
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CLOCK => CLOCK,
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OUTPUT => FOLLOW);
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petebleack |
INCREMENT_FOLLOW <= SHIFT_MOST or BUFFERED_FLUSH;
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petebleack |
--The output unit
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OUTPUT: OUTPUT_UNIT
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port map(ENABLE => TRIGGER_OUTPUT,
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petebleack |
DATA => SWITCHED_DATA,
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petebleack |
FOLLOW => FOLLOW,
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RESET => RESET,
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CLOCK => CLOCK,
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SENDING => OUTPUT_ACTIVE,
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DATA_OUT => DATA_OUT,
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FOLLOW_COUNTER_TEST => FOLLOW_COUNTER_TEST,
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petebleack |
SHIFT => TRIGGER_SHIFT);
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petebleack |
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SENDING <= OUTPUT_ACTIVE;
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petebleack |
SHIFT_ALL <= TRIGGER_SHIFT and not FLUSH_ENCODER;
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petebleack |
-- Input logic
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DATA_LOAD <= DATA_AVAILABLE and ARITHMETIC_UNIT_DATA_LOAD;
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HIGH_SET <= ZERO_INPUT and DATA_LOAD;
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ZERO_INPUT <= not BUFFERED_DATA;
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LOW_SET <= BUFFERED_DATA and DATA_LOAD;
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8 |
petebleack |
FLUSH_SWITCH : process (FLUSH_ENCODER,LOW_OUT,HIGH_OUT)
|
316 |
|
|
begin
|
317 |
|
|
if FLUSH_ENCODER = '1' then
|
318 |
|
|
SWITCHED_DATA <= LOW_OUT(14);
|
319 |
|
|
else
|
320 |
|
|
SWITCHED_DATA <= HIGH_OUT(15);
|
321 |
|
|
end if;
|
322 |
|
|
end process FLUSH_SWITCH;
|
323 |
|
|
|
324 |
2 |
petebleack |
-- Control logic for DIFFERENCE register
|
325 |
|
|
|
326 |
|
|
DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST;
|
327 |
|
|
|
328 |
|
|
-- Control logic for convergence check
|
329 |
|
|
|
330 |
|
|
CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD;
|
331 |
|
|
|
332 |
5 |
petebleack |
CONVERGENCE_TEST_DELAY: process (CLOCK)
|
333 |
|
|
begin
|
334 |
|
|
if CLOCK'event and CLOCK = '1' then
|
335 |
|
|
DELAYED_CHECK <= CHECK;
|
336 |
|
|
end if;
|
337 |
|
|
end process CONVERGENCE_TEST_DELAY;
|
338 |
2 |
petebleack |
|
339 |
|
|
CONVERGENCE_TEST <= DELAYED_CHECK or FOLLOW_COUNTER_TEST;
|
340 |
|
|
|
341 |
|
|
-- Control logic for arithmetic unit
|
342 |
|
|
|
343 |
5 |
petebleack |
ARITHMETIC_UNIT_ENABLE <= PROB_AVAILABLE and not(OUTPUT_ACTIVE or DIFFERENCE_SHIFT_ALL or DATA_LOAD);
|
344 |
2 |
petebleack |
|
345 |
|
|
-- Control Logic for input control
|
346 |
|
|
|
347 |
|
|
BUFFER_INPUT <= OUTPUT_ACTIVE or not ARITHMETIC_UNIT_DATA_LOAD;
|
348 |
|
|
|
349 |
|
|
-- Select the new difference value
|
350 |
|
|
|
351 |
|
|
NEWDIFF : process(BUFFERED_DATA,ARITHMETIC_UNIT_DIFFERENCE_OUT0,ARITHMETIC_UNIT_DIFFERENCE_OUT1)
|
352 |
|
|
begin
|
353 |
|
|
if(BUFFERED_DATA = '1') then
|
354 |
|
|
DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT1;
|
355 |
|
|
else
|
356 |
|
|
DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT0;
|
357 |
|
|
end if;
|
358 |
|
|
end process NEWDIFF;
|
359 |
|
|
|
360 |
5 |
petebleack |
-- Select the context
|
361 |
|
|
|
362 |
|
|
PROBABILITY : CONTEXT_MANAGER
|
363 |
|
|
port map(CONTEXT_NUMBER => CONTEXT_SELECT,
|
364 |
8 |
petebleack |
SET => NEWCONTEXT,
|
365 |
|
|
UPDATE => DATA_LOAD,
|
366 |
|
|
DATA_IN => BUFFERED_DATA,
|
367 |
|
|
HALVECOUNTS => HALVECOUNTS,
|
368 |
5 |
petebleack |
RESET => RESET,
|
369 |
|
|
CLOCK => CLOCK,
|
370 |
8 |
petebleack |
PROB => PROB,
|
371 |
|
|
READY => PROB_AVAILABLE);
|
372 |
5 |
petebleack |
|
373 |
8 |
petebleack |
|
374 |
|
|
|
375 |
|
|
FLUSH_CONTROL : process (CLOCK)
|
376 |
|
|
begin
|
377 |
|
|
if CLOCK'event and CLOCK = '1' then
|
378 |
|
|
if RESET = '1' then
|
379 |
|
|
FLUSH_ENCODER <= '0';
|
380 |
|
|
elsif BUFFERED_FLUSH = '1' then
|
381 |
|
|
FLUSH_ENCODER <= '1';
|
382 |
|
|
elsif TRIGGER_SHIFT = '1' then
|
383 |
|
|
FLUSH_ENCODER <= '0';
|
384 |
|
|
end if;
|
385 |
5 |
petebleack |
end if;
|
386 |
8 |
petebleack |
end process FLUSH_CONTROL;
|
387 |
|
|
|
388 |
|
|
FLUSH_COMPLETE <= FLUSH_ENCODER and TRIGGER_SHIFT;
|
389 |
|
|
|
390 |
|
|
LIMITHALVING : process (CLOCK)
|
391 |
|
|
begin
|
392 |
|
|
if CLOCK'event and CLOCK='1' then
|
393 |
|
|
if RESET='1' then
|
394 |
|
|
ALLOWHALVING <= '1';
|
395 |
|
|
else
|
396 |
|
|
ALLOWHALVING <= not CONTEXT_BUFFER_DATA_OUT(1);
|
397 |
|
|
end if;
|
398 |
5 |
petebleack |
end if;
|
399 |
8 |
petebleack |
end process LIMITHALVING;
|
400 |
5 |
petebleack |
|
401 |
8 |
petebleack |
RELEASE_CONTEXT <= RESET or DEMAND_CONTEXT;
|
402 |
5 |
petebleack |
|
403 |
8 |
petebleack |
CONTEXTS_SHOULD_BE_BUFFERED : process (RELEASE_CONTEXT,CLOCK)
|
404 |
|
|
begin
|
405 |
|
|
if CLOCK'event and CLOCK = '1' then
|
406 |
|
|
if NEWCONTEXT = '1' then
|
407 |
|
|
HOLDCONTEXT <= '1';
|
408 |
|
|
elsif RELEASE_CONTEXT = '1' then
|
409 |
|
|
HOLDCONTEXT <= '0';
|
410 |
|
|
end if;
|
411 |
|
|
end if;
|
412 |
|
|
end process CONTEXTS_SHOULD_BE_BUFFERED;
|
413 |
|
|
|
414 |
|
|
BUFFERCONTEXT <= HOLDCONTEXT and not RELEASE_CONTEXT;
|
415 |
|
|
|
416 |
|
|
--STORE_TRIGGERS : process (CLOCK)
|
417 |
|
|
--begin
|
418 |
|
|
-- if CLOCK'event and CLOCK='1' then
|
419 |
|
|
-- if RESET='1' then
|
420 |
|
|
-- LAST_FIVE_TRIGGERS <= "11111";
|
421 |
|
|
-- else
|
422 |
|
|
-- LAST_FIVE_TRIGGERS <= LAST_FIVE_TRIGGERS(3 downto 0) & (DATA_AVAILABLE or OUTPUT_ACTIVE or DIFFERENCE_SHIFT_ALL);
|
423 |
|
|
-- end if;
|
424 |
|
|
-- end if;
|
425 |
|
|
--end process STORE_TRIGGERS;
|
426 |
|
|
|
427 |
|
|
--GET_FLUSH_SIGNAL : process (LAST_FIVE_TRIGGERS)
|
428 |
|
|
--begin
|
429 |
|
|
-- if LAST_FIVE_TRIGGERS = "00000" then
|
430 |
|
|
-- FETCH_FLUSH <= '1';
|
431 |
|
|
-- else
|
432 |
|
|
-- FETCH_FLUSH <= '0';
|
433 |
|
|
-- end if;
|
434 |
|
|
--end process GET_FLUSH_SIGNAL;
|
435 |
|
|
|
436 |
|
|
LOCK_ENCODER : process (CLOCK)
|
437 |
|
|
begin
|
438 |
|
|
if CLOCK'event and CLOCK='1' then
|
439 |
|
|
if RESET = '1' then
|
440 |
|
|
LOCK <= '0';
|
441 |
|
|
elsif BUFFERED_FLUSH='1' then
|
442 |
|
|
LOCK <= '1';
|
443 |
|
|
end if;
|
444 |
|
|
end if;
|
445 |
|
|
end process LOCK_ENCODER;
|
446 |
|
|
|
447 |
|
|
DEMAND_CONTEXT <= DATA_LOAD; -- or FETCH_FLUSH;--DATA_LOAD or FETCH_FLUSH or AFTER_RESET;
|
448 |
|
|
|
449 |
|
|
--DELAY_RESET: process (CLOCK)
|
450 |
|
|
--begin
|
451 |
|
|
-- if CLOCK'event and CLOCK='1' then
|
452 |
|
|
-- AFTER_RESET <= RESET;
|
453 |
|
|
-- end if;
|
454 |
|
|
--end process DELAY_RESET;
|
455 |
5 |
petebleack |
--
|
456 |
|
|
|
457 |
2 |
petebleack |
end RTL;
|