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[/] [distributed_intelligence/] [trunk/] [BENCH/] [tb_ALU_simple.vhd] - Blame information for rev 4

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--------------------------------------------------------------------------------
-- Company: 
-- Engineer: L�o Germond
--
-- Create Date:   14:28:28 11/04/2009
-- Design Name:   
-- Module Name:   C:/Users/microcon/tb_ALU_simple.vhd
-- Project Name:  microcon
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ALU
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UNITTEST.all;
use work.ALU_INT.all;
use work.MY_FUNCS.all;
 
ENTITY tb_ALU_simple IS
END tb_ALU_simple;
 
ARCHITECTURE behavior OF tb_ALU_simple IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ALU
    PORT(
         data1 : IN  std_logic_vector(15 downto 0);
         data2 : IN  std_logic_vector(15 downto 0);
         op : IN  ALU_OPCODE;
         dataA : OUT  std_logic_vector(15 downto 0);
                        overflow: OUT std_logic
        );
    END COMPONENT;
 
 
   --Inputs
   signal data1 : std_logic_vector(15 downto 0) := (others => '0');
   signal data2 : std_logic_vector(15 downto 0) := (others => '0');
   signal op : ALU_OPCODE;
 
        --Outputs
   signal dataA : std_logic_vector(15 downto 0);
        signal overflow: std_logic;
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
   uut: ALU PORT MAP (
          data1 => data1,
          data2 => data2,
          dataA => dataA,
          op => op,
                         overflow => overflow
        );
 
 
   -- Stimulus process
   stim_proc: process
 
                procedure testAdd(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is
                        variable signe: std_logic;
                begin
                        -- Pr�paration des entr�es
                        if argSigne = '-' then -- On fixe le signe si ca n'a pas d�ja �t� fait
                                if(A < 0 or B < 0) then
                                        signe := '1';
                                else
                                        signe := '0';
                                end if;
                        else
                                signe := argSigne;
                        end if;
 
                        if signe = '1' then
                                op <= SADD;
                                data1 <= std_logic_vector(to_signed(A, 16));
                                data2 <= std_logic_vector(to_signed(B, 16));
                        else
                                op <= UADD;
                                data1 <= std_logic_vector(to_unsigned(A, 16));
                                data2 <= std_logic_vector(to_unsigned(B, 16));
                        end if;
 
                        -- D�lai d'attente
                        wait for delay;
 
                        -- V�rification du r�sultat
                        if signe = '1' then -- Op�ration sign�e
                                assertOperationResult(to_integer(signed(dataA)), A+B, "signed sum", (A+B > MAX_SIGNED) or (A+B < MIN_SIGNED), overflow);
                        else -- Op�ration non sign�e
                                assertOperationResult(to_integer(unsigned(dataA)), A+B, "unsigned sum", A+B > MAX_UNSIGNED, overflow);
                        end if;
                end procedure;
 
                procedure testSub(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is
                        variable signe: std_logic;
                begin
                        -- Pr�paration des entr�es
                        -- Fixe le signe
                        if argSigne = '-' then -- On fixe le signe si ca n'a pas d�ja �t� fait
                                if(A < 0 or B < 0) then
                                        signe := '1';
                                else
                                        signe := '0';
                                end if;
                        else
                                signe := argSigne;
                        end if;
 
                        -- Fixe l'op�ration
                        if signe = '1' then
                                op <= SSUB;
                                data1 <= std_logic_vector(to_signed(A, 16));
                                data2 <= std_logic_vector(to_signed(B, 16));
                        else
                                op <= USUB;
                                data1 <= std_logic_vector(to_unsigned(A, 16));
                                data2 <= std_logic_vector(to_unsigned(B, 16));
                        end if;
 
                        -- D�lai d'attente pour v�rification
                        wait for delay;
 
                        -- V�rification du r�sultat
                        if signe = '1' then -- Op�ration sign�e
                                assertOperationResult(to_integer(signed(dataA)), A-B, "signed subtraction", (A-B > MAX_SIGNED) or (A-B < MIN_SIGNED), overflow);
                        else -- Op�ration non sign�e
                                assertOperationResult(to_integer(unsigned(dataA)), A-B, "unsigned subtraction", (A-B > MAX_UNSIGNED) or (A-B < 0), overflow);
                        end if;
                end procedure;
 
                procedure testShift(A: in std_logic_vector(15 downto 0); argB: in integer; right: in std_logic := '-'; delay : in time := 50 ns) is
                        variable direction: std_logic;
                        variable B: natural;
                begin
                        -- Pr�paration des entr�es
                        if right = '-' then -- On fixe le signe si ca n'a pas d�ja �t� fait
                                if(argB < 0) then
                                        direction := '1';
                                        B := -argB;
                                else
                                        direction := '0';
                                end if;
                        else
                                direction := right;
                        end if;
 
                        if direction = '1' then
                                op <= LSHIFT;
                        else
                                op <= RSHIFT;
                        end if;
 
                        data1 <= A;
                        data2 <= std_logic_vector(to_unsigned(B, 16));
 
                        -- D�lai d'attente
                        wait for delay;
 
                        -- V�rification du r�sultat
                        if direction = '1' then -- A gauche
                                assertOperationResult(dataA, A sll B, "left shift", B > 15);
                        else -- A droite
                                assertOperationResult(dataA, A srl B, "right shift", B > 15);
                        end if;
                end procedure;
 
                procedure testBinary(A, B: in std_logic_vector(15 downto 0); delay : in time := 50 ns) is
                begin
                        op <= bOR;
                        data1 <= A;
                        data2 <= B;
 
                        -- D�lai d'attente
                        wait for delay;
 
                        -- V�rification du r�sultat
                        assertOperationResult(dataA, A OR B, "boolean OR");
 
                        op <= bAND;
 
                        -- D�lai d'attente
                        wait for delay;
 
                        -- V�rification du r�sultat
                        assertOperationResult(dataA, A AND B, "boolean AND");
 
                        op <= bXOR;
 
                        -- D�lai d'attente
                        wait for delay;
 
                        -- V�rification du r�sultat
                        assertOperationResult(dataA, A XOR B, "boolean OR");
 
                        op <= bNOT;
 
                        -- D�lai d'attente
                        wait for delay;
 
                        -- V�rification du r�sultat
                        assertOperationResult(dataA, NOT A, "boolean NOT");
                end procedure;
   begin
 
                report "TEST BEGINS";
 
                report "Testing binary ops ...";
                -- Binary ops
                testBinary(x"0000",x"0000");
                testBinary(x"f610",x"00ff");
                testBinary(x"ffff",x"aaaa");
                testBinary(x"f00f",x"aa00");
                testBinary(x"eeee",x"1111");
 
                report "Testing shiftings ...";
                -- LSHIFT
                testShift(x"fafb", 1);
                testShift(x"fafb", 2);
                testShift(x"fafb", 3);
                testShift(x"fafb", 0);
                testShift(x"fafb", 4);
                testShift(x"fafb", 15);
                testShift(x"fafb", 1);
 
                -- RSHIFT
                testShift(x"fafb", -1);
                testShift(x"fafb", -2);
                testShift(x"fafb", -3);
                testShift(x"fafb", 0, '1');
                testShift(x"fafb", -4);
                testShift(x"fafb", -15);
                testShift(x"fafb", -1);
 
                report "Testing additions ...";
                -- Additions non sign�es sans overflow
                testAdd(10,15);
                testAdd(5,0);
                testAdd(2,30);
                testAdd(MAX_UNSIGNED, 0);
                testAdd(MAX_UNSIGNED-15, 15);
 
                -- Additions sign�es sans overflow
                testAdd(0,-10);
                testAdd(10,-10);
                testAdd(11,-10);
                testAdd(MAX_SIGNED, MIN_SIGNED);
 
                -- Additions avec overflow
                testAdd(MAX_UNSIGNED,1);
                testAdd(MAX_UNSIGNED,MAX_UNSIGNED);
 
                testAdd(MAX_SIGNED,MAX_SIGNED, '1');
                testAdd(MIN_SIGNED, -1);
                testAdd(MIN_SIGNED,MIN_SIGNED);
 
 
                report "Testing subtractions ...";
                -- Substractions non sign�es sans overflow
                testSub(10,9);
                testSub(5,0);
                testSub(2,30);
                testSub(MAX_UNSIGNED, 0);
                testSub(MAX_UNSIGNED-15, 15);
 
                -- Substractions sign�es sans overflow
                testSub(0,-10);
                testSub(10,-10);
                testSub(11,-10);
                testSub(MAX_SIGNED, MIN_SIGNED);
                testSub(MIN_SIGNED, -1);
 
                -- Substractions avec overflow
                testSub(MAX_UNSIGNED,1);
                testSub(MAX_UNSIGNED,MAX_UNSIGNED);
 
                testSub(MAX_SIGNED,MAX_SIGNED, '1');
                testSub(MIN_SIGNED,MIN_SIGNED);
 
 
                report "END OF TEST";
      wait;
   end process;
 
END;

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Subversion Repositories distributed_intelligence

[/] [distributed_intelligence/] [trunk/] [BENCH/] [tb_ALU_simple.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	leoel	`--------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer: L�o Germond`
4			`--`
5			`-- Create Date: 14:28:28 11/04/2009`
6			`-- Design Name:`
7			`-- Module Name: C:/Users/microcon/tb_ALU_simple.vhd`
8			`-- Project Name: microcon`
9			`-- Target Device:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- VHDL Test Bench Created by ISE for module: ALU`
14			`--`
15			`-- Dependencies:`
16			`--`
17			`-- Revision:`
18			`-- Revision 0.01 - File Created`
19			`-- Additional Comments:`
20			`--`
21			`-- Notes:`
22			`-- This testbench has been automatically generated using types std_logic and`
23			`-- std_logic_vector for the ports of the unit under test. Xilinx recommends`
24			`-- that these types always be used for the top-level I/O of a design in order`
25			`-- to guarantee that the testbench will bind correctly to the post-implementation`
26			`-- simulation model.`
27			`--------------------------------------------------------------------------------`
28
29			`LIBRARY ieee;`
30			`USE ieee.std_logic_1164.ALL;`
31			`USE ieee.std_logic_unsigned.all;`
32			`USE ieee.numeric_std.ALL;`
33			`use work.UNITTEST.all;`
34			`use work.ALU_INT.all;`
35			`use work.MY_FUNCS.all;`
36
37			`ENTITY tb_ALU_simple IS`
38			`END tb_ALU_simple;`
39
40			`ARCHITECTURE behavior OF tb_ALU_simple IS`
41
42			`-- Component Declaration for the Unit Under Test (UUT)`
43
44			`COMPONENT ALU`
45			`PORT(`
46			`data1 : IN std_logic_vector(15 downto 0);`
47			`data2 : IN std_logic_vector(15 downto 0);`
48			`op : IN ALU_OPCODE;`
49			`dataA : OUT std_logic_vector(15 downto 0);`
50			`overflow: OUT std_logic`
51			`);`
52			`END COMPONENT;`
53
54
55			`--Inputs`
56			`signal data1 : std_logic_vector(15 downto 0) := (others => '0');`
57			`signal data2 : std_logic_vector(15 downto 0) := (others => '0');`
58			`signal op : ALU_OPCODE;`
59
60			`--Outputs`
61			`signal dataA : std_logic_vector(15 downto 0);`
62			`signal overflow: std_logic;`
63			`BEGIN`
64
65			`-- Instantiate the Unit Under Test (UUT)`
66			`uut: ALU PORT MAP (`
67			`data1 => data1,`
68			`data2 => data2,`
69			`dataA => dataA,`
70			`op => op,`
71			`overflow => overflow`
72			`);`
73
74
75			`-- Stimulus process`
76			`stim_proc: process`
77
78			`procedure testAdd(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is`
79			`variable signe: std_logic;`
80			`begin`
81			`-- Pr�paration des entr�es`
82			`if argSigne = '-' then -- On fixe le signe si ca n'a pas d�ja �t� fait`
83			`if(A < 0 or B < 0) then`
84			`signe := '1';`
85			`else`
86			`signe := '0';`
87			`end if;`
88			`else`
89			`signe := argSigne;`
90			`end if;`
91
92			`if signe = '1' then`
93			`op <= SADD;`
94			`data1 <= std_logic_vector(to_signed(A, 16));`
95			`data2 <= std_logic_vector(to_signed(B, 16));`
96			`else`
97			`op <= UADD;`
98			`data1 <= std_logic_vector(to_unsigned(A, 16));`
99			`data2 <= std_logic_vector(to_unsigned(B, 16));`
100			`end if;`
101
102			`-- D�lai d'attente`
103			`wait for delay;`
104
105			`-- V�rification du r�sultat`
106			`if signe = '1' then -- Op�ration sign�e`
107			`assertOperationResult(to_integer(signed(dataA)), A+B, "signed sum", (A+B > MAX_SIGNED) or (A+B < MIN_SIGNED), overflow);`
108			`else -- Op�ration non sign�e`
109			`assertOperationResult(to_integer(unsigned(dataA)), A+B, "unsigned sum", A+B > MAX_UNSIGNED, overflow);`
110			`end if;`
111			`end procedure;`
112
113			`procedure testSub(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is`
114			`variable signe: std_logic;`
115			`begin`
116			`-- Pr�paration des entr�es`
117			`-- Fixe le signe`
118			`if argSigne = '-' then -- On fixe le signe si ca n'a pas d�ja �t� fait`
119			`if(A < 0 or B < 0) then`
120			`signe := '1';`
121			`else`
122			`signe := '0';`
123			`end if;`
124			`else`
125			`signe := argSigne;`
126			`end if;`
127
128			`-- Fixe l'op�ration`
129			`if signe = '1' then`
130			`op <= SSUB;`
131			`data1 <= std_logic_vector(to_signed(A, 16));`
132			`data2 <= std_logic_vector(to_signed(B, 16));`
133			`else`
134			`op <= USUB;`
135			`data1 <= std_logic_vector(to_unsigned(A, 16));`
136			`data2 <= std_logic_vector(to_unsigned(B, 16));`
137			`end if;`
138
139			`-- D�lai d'attente pour v�rification`
140			`wait for delay;`
141
142			`-- V�rification du r�sultat`
143			`if signe = '1' then -- Op�ration sign�e`
144			`assertOperationResult(to_integer(signed(dataA)), A-B, "signed subtraction", (A-B > MAX_SIGNED) or (A-B < MIN_SIGNED), overflow);`
145			`else -- Op�ration non sign�e`
146			`assertOperationResult(to_integer(unsigned(dataA)), A-B, "unsigned subtraction", (A-B > MAX_UNSIGNED) or (A-B < 0), overflow);`
147			`end if;`
148			`end procedure;`
149
150			`procedure testShift(A: in std_logic_vector(15 downto 0); argB: in integer; right: in std_logic := '-'; delay : in time := 50 ns) is`
151			`variable direction: std_logic;`
152			`variable B: natural;`
153			`begin`
154			`-- Pr�paration des entr�es`
155			`if right = '-' then -- On fixe le signe si ca n'a pas d�ja �t� fait`
156			`if(argB < 0) then`
157			`direction := '1';`
158			`B := -argB;`
159			`else`
160			`direction := '0';`
161			`end if;`
162			`else`
163			`direction := right;`
164			`end if;`
165
166			`if direction = '1' then`
167			`op <= LSHIFT;`
168			`else`
169			`op <= RSHIFT;`
170			`end if;`
171
172			`data1 <= A;`
173			`data2 <= std_logic_vector(to_unsigned(B, 16));`
174
175			`-- D�lai d'attente`
176			`wait for delay;`
177
178			`-- V�rification du r�sultat`
179			`if direction = '1' then -- A gauche`
180			`assertOperationResult(dataA, A sll B, "left shift", B > 15);`
181			`else -- A droite`
182			`assertOperationResult(dataA, A srl B, "right shift", B > 15);`
183			`end if;`
184			`end procedure;`
185
186			`procedure testBinary(A, B: in std_logic_vector(15 downto 0); delay : in time := 50 ns) is`
187			`begin`
188			`op <= bOR;`
189			`data1 <= A;`
190			`data2 <= B;`
191
192			`-- D�lai d'attente`
193			`wait for delay;`
194
195			`-- V�rification du r�sultat`
196			`assertOperationResult(dataA, A OR B, "boolean OR");`
197
198			`op <= bAND;`
199
200			`-- D�lai d'attente`
201			`wait for delay;`
202
203			`-- V�rification du r�sultat`
204			`assertOperationResult(dataA, A AND B, "boolean AND");`
205
206			`op <= bXOR;`
207
208			`-- D�lai d'attente`
209			`wait for delay;`
210
211			`-- V�rification du r�sultat`
212			`assertOperationResult(dataA, A XOR B, "boolean OR");`
213
214			`op <= bNOT;`
215
216			`-- D�lai d'attente`
217			`wait for delay;`
218
219			`-- V�rification du r�sultat`
220			`assertOperationResult(dataA, NOT A, "boolean NOT");`
221			`end procedure;`
222			`begin`
223
224			`report "TEST BEGINS";`
225
226			`report "Testing binary ops ...";`
227			`-- Binary ops`
228			`testBinary(x"0000",x"0000");`
229			`testBinary(x"f610",x"00ff");`
230			`testBinary(x"ffff",x"aaaa");`
231			`testBinary(x"f00f",x"aa00");`
232			`testBinary(x"eeee",x"1111");`
233
234			`report "Testing shiftings ...";`
235			`-- LSHIFT`
236			`testShift(x"fafb", 1);`
237			`testShift(x"fafb", 2);`
238			`testShift(x"fafb", 3);`
239			`testShift(x"fafb", 0);`
240			`testShift(x"fafb", 4);`
241			`testShift(x"fafb", 15);`
242			`testShift(x"fafb", 1);`
243
244			`-- RSHIFT`
245			`testShift(x"fafb", -1);`
246			`testShift(x"fafb", -2);`
247			`testShift(x"fafb", -3);`
248			`testShift(x"fafb", 0, '1');`
249			`testShift(x"fafb", -4);`
250			`testShift(x"fafb", -15);`
251			`testShift(x"fafb", -1);`
252
253			`report "Testing additions ...";`
254			`-- Additions non sign�es sans overflow`
255			`testAdd(10,15);`
256			`testAdd(5,0);`
257			`testAdd(2,30);`
258			`testAdd(MAX_UNSIGNED, 0);`
259			`testAdd(MAX_UNSIGNED-15, 15);`
260
261			`-- Additions sign�es sans overflow`
262			`testAdd(0,-10);`
263			`testAdd(10,-10);`
264			`testAdd(11,-10);`
265			`testAdd(MAX_SIGNED, MIN_SIGNED);`
266
267			`-- Additions avec overflow`
268			`testAdd(MAX_UNSIGNED,1);`
269			`testAdd(MAX_UNSIGNED,MAX_UNSIGNED);`
270
271			`testAdd(MAX_SIGNED,MAX_SIGNED, '1');`
272			`testAdd(MIN_SIGNED, -1);`
273			`testAdd(MIN_SIGNED,MIN_SIGNED);`
274
275
276			`report "Testing subtractions ...";`
277			`-- Substractions non sign�es sans overflow`
278			`testSub(10,9);`
279			`testSub(5,0);`
280			`testSub(2,30);`
281			`testSub(MAX_UNSIGNED, 0);`
282			`testSub(MAX_UNSIGNED-15, 15);`
283
284			`-- Substractions sign�es sans overflow`
285			`testSub(0,-10);`
286			`testSub(10,-10);`
287			`testSub(11,-10);`
288			`testSub(MAX_SIGNED, MIN_SIGNED);`
289			`testSub(MIN_SIGNED, -1);`
290
291			`-- Substractions avec overflow`
292			`testSub(MAX_UNSIGNED,1);`
293			`testSub(MAX_UNSIGNED,MAX_UNSIGNED);`
294
295			`testSub(MAX_SIGNED,MAX_SIGNED, '1');`
296			`testSub(MIN_SIGNED,MIN_SIGNED);`
297
298
299			`report "END OF TEST";`
300			`wait;`
301			`end process;`
302
303			`END;`