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[/] [distributed_intelligence/] [trunk/] [LIB/] [UnitTest.vhd] - Blame information for rev 6

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Line No. Rev Author Line
1 5 leoel
--              UNIT TESTS
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--
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--      Purpose: This package gives procedures and function to make automated unit tests.
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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package UnitTest is
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        -- assertEqual: 
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        -- This procedure tests if 2 values are equal, if they are not, it shows an error report
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        procedure assertEqual(current, expected: in integer; resultName: in string := "Result");
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        procedure assertEqual(current, expected: in std_logic; resultName: in string := "Result");
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        procedure assertEqual(current, expected: in std_logic_vector; resultName: in string := "Result");
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        -- assertOperationResult:
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        -- This procedure tests if an operation is working under overflow conditions. If they are not, it reports an error.
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        -- You can also specify an overflow bit to be verified automatically by the procedure to be at '1' when there is an
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        -- overflow and at '0' when there is no overflow.
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        procedure assertOperationResult(        actual, expected : in integer; opName: in string:= "operation"; overflowCond: boolean := false; overflowBit: std_logic := '-');
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        procedure assertOperationResult(        actual, expected : in std_logic_vector; opName: in string:= "operation"; overflowCond: boolean := false; overflowBit: std_logic := '-');
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end UnitTest;
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package body UnitTest is
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                procedure assertEqual(current, expected: in integer; resultName: in string := "Result") is
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                begin
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                        assert current = expected
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                                report resultName &" is incorrect. Expected: " & integer'image(expected) & " Current: " & integer'image(current)
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                                severity ERROR;
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                end procedure;
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                procedure assertEqual(current, expected: in std_logic; resultName: in string := "Result") is
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                begin
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                        assert current = expected
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                                report resultName &" is incorrect. Expected: " & std_logic'image(expected) & " Current: " & std_logic'image(current)
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                                severity ERROR;
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                end procedure;
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                procedure assertEqual(current, expected: in std_logic_vector; resultName: in string := "Result") is
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                begin
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                        assertEqual(to_integer(unsigned(current)), to_integer(unsigned(expected)), resultName);
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                end procedure;
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                -- Automaticaly verifies that the result is correct, beeing given the boundaries of the calculator and that
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                -- overflow bit is correctly set in both cases
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                -- Arguments:
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                --      actual, expected: Actual and expected results
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                --              opName: Name of the operation
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                --              overflowCond: Condition for an overflow, ignored by default
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                --              overflowBit: Overflow bit set to 1 in case of overflow, no verification if set to '-' (default)
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                procedure assertOperationResult(        actual, expected : in integer; opName: in string:= "operation";
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                                                                                                        overflowCond: boolean := false; overflowBit: std_logic := '-') is
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                begin
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                        if overflowCond then
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                                if overflowBit /= '-' then
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                                        assertEqual(overflowBit, '1', "Overflow bit for " & opName & " with result " & integer'image(actual));
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                                end if;
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                        else
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                                if overflowBit /= '-' then
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                                        assertEqual(overflowBit, '0', "Overflow bit for " & opName & " with result " & integer'image(actual));
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                                end if;
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                                assertEqual(actual, expected , opName & " result");
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                        end if;
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                end procedure;
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                procedure assertOperationResult(        actual, expected : in std_logic_vector; opName: in string:= "operation";
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                                                                                                        overflowCond: boolean := false; overflowBit: std_logic := '-') is
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                begin
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                        assertOperationResult(to_integer(unsigned(actual)), to_integer(unsigned(expected)), opName, overflowCond, overflowBit);
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                end procedure;
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end UnitTest;

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