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[/] [distributed_intelligence/] [trunk/] [SRC/] [rdecal_x16.vhd] - Blame information for rev 4

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1 4 leoel
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: Léo Germond
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-- 
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-- Create Date:    19:21:58 11/04/2009 
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-- Design Name: 
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-- Module Name:    rdecal_x16 - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity rdecal_x16 is
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    Port ( data : in  STD_LOGIC_VECTOR (15 downto 0);
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           decal_lvl : in  STD_LOGIC_VECTOR (3 downto 0);
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           decal : out  STD_LOGIC_VECTOR (15 downto 0));
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end rdecal_x16;
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architecture BarrelShifter of rdecal_x16 is
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        signal din: STD_LOGIC_VECTOR (15 downto 0);
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        signal dout: STD_LOGIC_VECTOR (15 downto 0);
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        signal dec1: STD_LOGIC_VECTOR (15 downto 0);
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        signal dec2: STD_LOGIC_VECTOR (15 downto 0);
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        signal dec3: STD_LOGIC_VECTOR (15 downto 0);
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        component generic_const_rdecal_x16
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                generic ( BIT_DECAL : natural range 0 to 15 );
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                Port ( data : in  STD_LOGIC_VECTOR (15 downto 0);
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           en : in  STD_LOGIC;
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           decal : out  STD_LOGIC_VECTOR (15 downto 0));
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        end component;
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begin
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        d1 : generic_const_rdecal_x16
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                generic map(BIT_DECAL => 1)
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                port map( data => din, en => decal_lvl(0), decal => dec1);
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        d2 : generic_const_rdecal_x16
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                generic map(BIT_DECAL => 2)
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                port map( data => dec1, en => decal_lvl(1), decal => dec2);
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        d3 : generic_const_rdecal_x16
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                generic map(BIT_DECAL => 4)
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                port map( data => dec2, en => decal_lvl(2), decal => dec3);
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        d4 : generic_const_rdecal_x16
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                generic map(BIT_DECAL => 8)
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                port map( data => dec3, en => decal_lvl(3), decal => dout);
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                din <= data;
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                decal <= dout;
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end BarrelShifter;

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