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hidemi |
//---------------------------------------------------------------------------
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// File Name : jpeg_idctb.v
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// Module Name : jpeg_idctb
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// Description : data register for iDCT
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// Project : JPEG Decoder
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// Belong to :
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// Author : H.Ishihara
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// E-Mail : hidemi@sweetcafe.jp
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// HomePage : http://www.sweetcafe.jp/
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// Date : 2006/10/01
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// Rev. : 1.1
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//---------------------------------------------------------------------------
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// Rev. Date Description
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//---------------------------------------------------------------------------
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// 1.01 2006/10/01 1st Release
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//---------------------------------------------------------------------------
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// $Id:
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//---------------------------------------------------------------------------
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`timescale 1ps / 1ps
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module jpeg_idctb
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(
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rst,
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clk,
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DataInEnable,
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DataInPage,
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DataInCount,
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DataInIdle,
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Data0In,
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Data1In,
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DataOutEnable,
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DataOutSel,
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Data00Out,
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Data01Out,
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Data02Out,
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Data03Out,
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Data04Out,
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Data05Out,
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Data06Out,
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Data07Out,
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Data08Out,
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Data09Out,
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Data10Out,
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Data11Out,
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Data12Out,
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Data13Out,
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Data14Out,
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Data15Out,
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Data16Out,
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Data17Out,
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Data18Out,
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Data19Out,
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Data20Out,
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Data21Out,
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Data22Out,
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Data23Out,
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Data24Out,
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Data25Out,
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Data26Out,
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Data27Out,
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Data28Out,
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Data29Out,
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Data30Out,
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Data31Out,
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Data32Out,
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Data33Out,
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Data34Out,
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Data35Out,
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Data36Out,
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Data37Out,
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Data38Out,
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Data39Out,
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Data40Out,
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Data41Out,
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Data42Out,
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Data43Out,
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Data44Out,
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Data45Out,
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Data46Out,
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Data47Out,
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Data48Out,
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Data49Out,
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Data50Out,
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Data51Out,
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Data52Out,
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Data53Out,
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Data54Out,
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Data55Out,
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Data56Out,
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Data57Out,
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Data58Out,
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Data59Out,
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Data60Out,
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Data61Out,
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Data62Out,
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Data63Out,
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BankARelease,
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BankBRelease
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);
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input clk;
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input rst;
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input DataInEnable;
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input [2:0] DataInPage;
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input [1:0] DataInCount;
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output DataInIdle;
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input [15:0] Data0In;
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input [15:0] Data1In;
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output DataOutEnable;
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input DataOutSel;
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output [15:0] Data00Out;
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output [15:0] Data01Out;
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output [15:0] Data02Out;
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output [15:0] Data03Out;
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output [15:0] Data04Out;
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output [15:0] Data05Out;
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output [15:0] Data06Out;
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output [15:0] Data07Out;
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output [15:0] Data08Out;
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output [15:0] Data09Out;
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output [15:0] Data10Out;
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output [15:0] Data11Out;
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output [15:0] Data12Out;
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output [15:0] Data13Out;
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output [15:0] Data14Out;
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output [15:0] Data15Out;
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output [15:0] Data16Out;
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output [15:0] Data17Out;
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output [15:0] Data18Out;
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output [15:0] Data19Out;
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output [15:0] Data20Out;
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output [15:0] Data21Out;
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output [15:0] Data22Out;
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output [15:0] Data23Out;
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output [15:0] Data24Out;
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output [15:0] Data25Out;
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output [15:0] Data26Out;
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output [15:0] Data27Out;
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output [15:0] Data28Out;
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output [15:0] Data29Out;
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output [15:0] Data30Out;
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output [15:0] Data31Out;
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output [15:0] Data32Out;
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output [15:0] Data33Out;
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output [15:0] Data34Out;
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output [15:0] Data35Out;
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output [15:0] Data36Out;
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output [15:0] Data37Out;
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output [15:0] Data38Out;
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output [15:0] Data39Out;
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output [15:0] Data40Out;
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output [15:0] Data41Out;
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output [15:0] Data42Out;
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output [15:0] Data43Out;
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output [15:0] Data44Out;
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output [15:0] Data45Out;
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output [15:0] Data46Out;
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output [15:0] Data47Out;
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output [15:0] Data48Out;
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output [15:0] Data49Out;
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output [15:0] Data50Out;
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output [15:0] Data51Out;
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output [15:0] Data52Out;
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output [15:0] Data53Out;
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output [15:0] Data54Out;
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output [15:0] Data55Out;
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output [15:0] Data56Out;
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output [15:0] Data57Out;
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output [15:0] Data58Out;
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output [15:0] Data59Out;
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output [15:0] Data60Out;
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output [15:0] Data61Out;
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output [15:0] Data62Out;
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output [15:0] Data63Out;
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input BankARelease;
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input BankBRelease;
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reg BankAEnable;
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reg BankBEnable;
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reg DataInBank;
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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BankAEnable <= 1'b0;
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BankBEnable <= 1'b0;
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DataInBank <= 1'b0;
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end else begin
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if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
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if(DataInEnable == 1'b1 &
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DataInPage == 3'd7 & DataInCount == 2'd3) begin
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BankAEnable <= 1'b1;
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end
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end else begin
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if(BankARelease == 1'b1) begin
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BankAEnable <= 1'b0;
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end
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end
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if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
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if(DataInEnable == 1'b1 &
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DataInPage == 3'd7 & DataInCount == 2'd3) begin
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BankBEnable <= 1'b1;
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end
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end else begin
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if(BankBRelease == 1'b1) begin
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BankBEnable <= 1'b0;
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end
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end
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if(DataInEnable == 1'b1 &
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DataInPage == 3'd7 & DataInCount == 2'd3) begin
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DataInBank <= ~DataInBank;
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end
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end // else: !if(!rst)
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end // always @ (posedge clk or negedge rst)
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assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;
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assign DataOutEnable = DataInEnable == 1'b1 & DataInPage == 3'b111 &
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DataInCount == 2'b11;
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reg [15:0] BankAReg [0:63];
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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BankAReg[0] <= 12'h000;
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BankAReg[1] <= 12'h000;
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BankAReg[2] <= 12'h000;
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BankAReg[3] <= 12'h000;
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BankAReg[4] <= 12'h000;
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BankAReg[5] <= 12'h000;
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BankAReg[6] <= 12'h000;
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BankAReg[7] <= 12'h000;
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BankAReg[8] <= 12'h000;
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BankAReg[9] <= 12'h000;
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BankAReg[10] <= 12'h000;
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BankAReg[11] <= 12'h000;
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BankAReg[12] <= 12'h000;
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BankAReg[13] <= 12'h000;
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BankAReg[14] <= 12'h000;
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BankAReg[15] <= 12'h000;
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BankAReg[16] <= 12'h000;
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BankAReg[17] <= 12'h000;
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BankAReg[18] <= 12'h000;
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BankAReg[19] <= 12'h000;
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BankAReg[20] <= 12'h000;
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BankAReg[21] <= 12'h000;
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BankAReg[22] <= 12'h000;
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BankAReg[23] <= 12'h000;
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BankAReg[24] <= 12'h000;
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BankAReg[25] <= 12'h000;
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BankAReg[26] <= 12'h000;
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BankAReg[27] <= 12'h000;
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BankAReg[28] <= 12'h000;
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BankAReg[29] <= 12'h000;
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BankAReg[30] <= 12'h000;
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BankAReg[31] <= 12'h000;
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BankAReg[32] <= 12'h000;
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BankAReg[33] <= 12'h000;
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BankAReg[34] <= 12'h000;
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BankAReg[35] <= 12'h000;
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BankAReg[36] <= 12'h000;
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BankAReg[37] <= 12'h000;
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BankAReg[38] <= 12'h000;
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BankAReg[39] <= 12'h000;
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BankAReg[40] <= 12'h000;
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BankAReg[41] <= 12'h000;
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BankAReg[42] <= 12'h000;
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BankAReg[43] <= 12'h000;
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BankAReg[44] <= 12'h000;
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| 275 |
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BankAReg[45] <= 12'h000;
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| 276 |
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BankAReg[46] <= 12'h000;
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| 277 |
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BankAReg[47] <= 12'h000;
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| 278 |
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BankAReg[48] <= 12'h000;
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| 279 |
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BankAReg[49] <= 12'h000;
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| 280 |
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BankAReg[50] <= 12'h000;
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| 281 |
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BankAReg[51] <= 12'h000;
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| 282 |
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BankAReg[52] <= 12'h000;
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| 283 |
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BankAReg[53] <= 12'h000;
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| 284 |
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BankAReg[54] <= 12'h000;
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| 285 |
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BankAReg[55] <= 12'h000;
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| 286 |
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BankAReg[56] <= 12'h000;
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| 287 |
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BankAReg[57] <= 12'h000;
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| 288 |
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BankAReg[58] <= 12'h000;
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| 289 |
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BankAReg[59] <= 12'h000;
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| 290 |
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BankAReg[60] <= 12'h000;
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| 291 |
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BankAReg[61] <= 12'h000;
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| 292 |
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BankAReg[62] <= 12'h000;
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| 293 |
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BankAReg[63] <= 12'h000;
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| 294 |
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end else begin // if (!rst)
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| 295 |
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if(DataInEnable == 1'b1 & DataInBank == 1'b0) begin
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| 296 |
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case(DataInPage)
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| 297 |
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3'd0: begin
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| 298 |
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case(DataInCount)
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| 299 |
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2'd0: begin
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| 300 |
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BankAReg[0] <= Data0In;
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| 301 |
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BankAReg[7] <= Data1In;
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| 302 |
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end
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| 303 |
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2'd1: begin
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| 304 |
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BankAReg[1] <= Data0In;
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| 305 |
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BankAReg[6] <= Data1In;
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| 306 |
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end
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| 307 |
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2'd2: begin
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| 308 |
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BankAReg[2] <= Data0In;
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| 309 |
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BankAReg[5] <= Data1In;
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| 310 |
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end
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| 311 |
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2'd3: begin
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| 312 |
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BankAReg[3] <= Data0In;
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| 313 |
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BankAReg[4] <= Data1In;
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| 314 |
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end
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| 315 |
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endcase // case(DataInCount)
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| 316 |
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end // case: 3'd0
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| 317 |
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3'd1: begin
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| 318 |
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case(DataInCount)
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| 319 |
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2'd0: begin
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| 320 |
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BankAReg[8] <= Data0In;
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| 321 |
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BankAReg[15] <= Data1In;
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| 322 |
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end
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| 323 |
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2'd1: begin
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| 324 |
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BankAReg[9] <= Data0In;
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| 325 |
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BankAReg[14] <= Data1In;
|
| 326 |
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end
|
| 327 |
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2'd2: begin
|
| 328 |
|
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BankAReg[10] <= Data0In;
|
| 329 |
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BankAReg[13] <= Data1In;
|
| 330 |
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end
|
| 331 |
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2'd3: begin
|
| 332 |
|
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BankAReg[11] <= Data0In;
|
| 333 |
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BankAReg[12] <= Data1In;
|
| 334 |
|
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end
|
| 335 |
|
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endcase // case(DataInCount)
|
| 336 |
|
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end // case: 3'd1
|
| 337 |
|
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3'd2: begin
|
| 338 |
|
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case(DataInCount)
|
| 339 |
|
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2'd0: begin
|
| 340 |
|
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BankAReg[16] <= Data0In;
|
| 341 |
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BankAReg[23] <= Data1In;
|
| 342 |
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end
|
| 343 |
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2'd1: begin
|
| 344 |
|
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BankAReg[17] <= Data0In;
|
| 345 |
|
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BankAReg[22] <= Data1In;
|
| 346 |
|
|
end
|
| 347 |
|
|
2'd2: begin
|
| 348 |
|
|
BankAReg[18] <= Data0In;
|
| 349 |
|
|
BankAReg[21] <= Data1In;
|
| 350 |
|
|
end
|
| 351 |
|
|
2'd3: begin
|
| 352 |
|
|
BankAReg[19] <= Data0In;
|
| 353 |
|
|
BankAReg[20] <= Data1In;
|
| 354 |
|
|
end
|
| 355 |
|
|
endcase // case(DataInCount)
|
| 356 |
|
|
end // case: 3'd2
|
| 357 |
|
|
3'd3: begin
|
| 358 |
|
|
case(DataInCount)
|
| 359 |
|
|
2'd0: begin
|
| 360 |
|
|
BankAReg[24] <= Data0In;
|
| 361 |
|
|
BankAReg[31] <= Data1In;
|
| 362 |
|
|
end
|
| 363 |
|
|
2'd1: begin
|
| 364 |
|
|
BankAReg[25] <= Data0In;
|
| 365 |
|
|
BankAReg[30] <= Data1In;
|
| 366 |
|
|
end
|
| 367 |
|
|
2'd2: begin
|
| 368 |
|
|
BankAReg[26] <= Data0In;
|
| 369 |
|
|
BankAReg[29] <= Data1In;
|
| 370 |
|
|
end
|
| 371 |
|
|
2'd3: begin
|
| 372 |
|
|
BankAReg[27] <= Data0In;
|
| 373 |
|
|
BankAReg[28] <= Data1In;
|
| 374 |
|
|
end
|
| 375 |
|
|
endcase // case(DataInCount)
|
| 376 |
|
|
end // case: 3'd3
|
| 377 |
|
|
3'd4: begin
|
| 378 |
|
|
case(DataInCount)
|
| 379 |
|
|
2'd0: begin
|
| 380 |
|
|
BankAReg[32] <= Data0In;
|
| 381 |
|
|
BankAReg[39] <= Data1In;
|
| 382 |
|
|
end
|
| 383 |
|
|
2'd1: begin
|
| 384 |
|
|
BankAReg[33] <= Data0In;
|
| 385 |
|
|
BankAReg[38] <= Data1In;
|
| 386 |
|
|
end
|
| 387 |
|
|
2'd2: begin
|
| 388 |
|
|
BankAReg[34] <= Data0In;
|
| 389 |
|
|
BankAReg[37] <= Data1In;
|
| 390 |
|
|
end
|
| 391 |
|
|
2'd3: begin
|
| 392 |
|
|
BankAReg[35] <= Data0In;
|
| 393 |
|
|
BankAReg[36] <= Data1In;
|
| 394 |
|
|
end
|
| 395 |
|
|
endcase // case(DataInCount)
|
| 396 |
|
|
end // case: 3'd4
|
| 397 |
|
|
3'd5: begin
|
| 398 |
|
|
case(DataInCount)
|
| 399 |
|
|
2'd0: begin
|
| 400 |
|
|
BankAReg[40] <= Data0In;
|
| 401 |
|
|
BankAReg[47] <= Data1In;
|
| 402 |
|
|
end
|
| 403 |
|
|
2'd1: begin
|
| 404 |
|
|
BankAReg[41] <= Data0In;
|
| 405 |
|
|
BankAReg[46] <= Data1In;
|
| 406 |
|
|
end
|
| 407 |
|
|
2'd2: begin
|
| 408 |
|
|
BankAReg[42] <= Data0In;
|
| 409 |
|
|
BankAReg[45] <= Data1In;
|
| 410 |
|
|
end
|
| 411 |
|
|
2'd3: begin
|
| 412 |
|
|
BankAReg[43] <= Data0In;
|
| 413 |
|
|
BankAReg[44] <= Data1In;
|
| 414 |
|
|
end
|
| 415 |
|
|
endcase // case(DataInCount)
|
| 416 |
|
|
end // case: 3'd5
|
| 417 |
|
|
3'd6: begin
|
| 418 |
|
|
case(DataInCount)
|
| 419 |
|
|
2'd0: begin
|
| 420 |
|
|
BankAReg[48] <= Data0In;
|
| 421 |
|
|
BankAReg[55] <= Data1In;
|
| 422 |
|
|
end
|
| 423 |
|
|
2'd1: begin
|
| 424 |
|
|
BankAReg[49] <= Data0In;
|
| 425 |
|
|
BankAReg[54] <= Data1In;
|
| 426 |
|
|
end
|
| 427 |
|
|
2'd2: begin
|
| 428 |
|
|
BankAReg[50] <= Data0In;
|
| 429 |
|
|
BankAReg[53] <= Data1In;
|
| 430 |
|
|
end
|
| 431 |
|
|
2'd3: begin
|
| 432 |
|
|
BankAReg[51] <= Data0In;
|
| 433 |
|
|
BankAReg[52] <= Data1In;
|
| 434 |
|
|
end
|
| 435 |
|
|
endcase // case(DataInCount)
|
| 436 |
|
|
end // case: 3'd6
|
| 437 |
|
|
3'd7: begin
|
| 438 |
|
|
case(DataInCount)
|
| 439 |
|
|
2'd0: begin
|
| 440 |
|
|
BankAReg[56] <= Data0In;
|
| 441 |
|
|
BankAReg[63] <= Data1In;
|
| 442 |
|
|
end
|
| 443 |
|
|
2'd1: begin
|
| 444 |
|
|
BankAReg[57] <= Data0In;
|
| 445 |
|
|
BankAReg[62] <= Data1In;
|
| 446 |
|
|
end
|
| 447 |
|
|
2'd2: begin
|
| 448 |
|
|
BankAReg[58] <= Data0In;
|
| 449 |
|
|
BankAReg[61] <= Data1In;
|
| 450 |
|
|
end
|
| 451 |
|
|
2'd3: begin
|
| 452 |
|
|
BankAReg[59] <= Data0In;
|
| 453 |
|
|
BankAReg[60] <= Data1In;
|
| 454 |
|
|
end
|
| 455 |
|
|
endcase // case(DataInCount)
|
| 456 |
|
|
end // case: 3'd7
|
| 457 |
|
|
endcase // case(DataInPage)
|
| 458 |
|
|
end // if (DataInEnable == 1'b1 & DataInBank == 1'b0)
|
| 459 |
|
|
end // else: !if(!rst)
|
| 460 |
|
|
end // always @ (posedge clk or negedge rst)
|
| 461 |
|
|
|
| 462 |
|
|
reg [15:0] BankBReg [0:63];
|
| 463 |
|
|
|
| 464 |
|
|
always @(posedge clk or negedge rst) begin
|
| 465 |
|
|
if(!rst) begin
|
| 466 |
|
|
BankBReg[0] <= 12'h000;
|
| 467 |
|
|
BankBReg[1] <= 12'h000;
|
| 468 |
|
|
BankBReg[2] <= 12'h000;
|
| 469 |
|
|
BankBReg[3] <= 12'h000;
|
| 470 |
|
|
BankBReg[4] <= 12'h000;
|
| 471 |
|
|
BankBReg[5] <= 12'h000;
|
| 472 |
|
|
BankBReg[6] <= 12'h000;
|
| 473 |
|
|
BankBReg[7] <= 12'h000;
|
| 474 |
|
|
BankBReg[8] <= 12'h000;
|
| 475 |
|
|
BankBReg[9] <= 12'h000;
|
| 476 |
|
|
BankBReg[10] <= 12'h000;
|
| 477 |
|
|
BankBReg[11] <= 12'h000;
|
| 478 |
|
|
BankBReg[12] <= 12'h000;
|
| 479 |
|
|
BankBReg[13] <= 12'h000;
|
| 480 |
|
|
BankBReg[14] <= 12'h000;
|
| 481 |
|
|
BankBReg[15] <= 12'h000;
|
| 482 |
|
|
BankBReg[16] <= 12'h000;
|
| 483 |
|
|
BankBReg[17] <= 12'h000;
|
| 484 |
|
|
BankBReg[18] <= 12'h000;
|
| 485 |
|
|
BankBReg[19] <= 12'h000;
|
| 486 |
|
|
BankBReg[20] <= 12'h000;
|
| 487 |
|
|
BankBReg[21] <= 12'h000;
|
| 488 |
|
|
BankBReg[22] <= 12'h000;
|
| 489 |
|
|
BankBReg[23] <= 12'h000;
|
| 490 |
|
|
BankBReg[24] <= 12'h000;
|
| 491 |
|
|
BankBReg[25] <= 12'h000;
|
| 492 |
|
|
BankBReg[26] <= 12'h000;
|
| 493 |
|
|
BankBReg[27] <= 12'h000;
|
| 494 |
|
|
BankBReg[28] <= 12'h000;
|
| 495 |
|
|
BankBReg[29] <= 12'h000;
|
| 496 |
|
|
BankBReg[30] <= 12'h000;
|
| 497 |
|
|
BankBReg[31] <= 12'h000;
|
| 498 |
|
|
BankBReg[32] <= 12'h000;
|
| 499 |
|
|
BankBReg[33] <= 12'h000;
|
| 500 |
|
|
BankBReg[34] <= 12'h000;
|
| 501 |
|
|
BankBReg[35] <= 12'h000;
|
| 502 |
|
|
BankBReg[36] <= 12'h000;
|
| 503 |
|
|
BankBReg[37] <= 12'h000;
|
| 504 |
|
|
BankBReg[38] <= 12'h000;
|
| 505 |
|
|
BankBReg[39] <= 12'h000;
|
| 506 |
|
|
BankBReg[40] <= 12'h000;
|
| 507 |
|
|
BankBReg[41] <= 12'h000;
|
| 508 |
|
|
BankBReg[42] <= 12'h000;
|
| 509 |
|
|
BankBReg[43] <= 12'h000;
|
| 510 |
|
|
BankBReg[44] <= 12'h000;
|
| 511 |
|
|
BankBReg[45] <= 12'h000;
|
| 512 |
|
|
BankBReg[46] <= 12'h000;
|
| 513 |
|
|
BankBReg[47] <= 12'h000;
|
| 514 |
|
|
BankBReg[48] <= 12'h000;
|
| 515 |
|
|
BankBReg[49] <= 12'h000;
|
| 516 |
|
|
BankBReg[50] <= 12'h000;
|
| 517 |
|
|
BankBReg[51] <= 12'h000;
|
| 518 |
|
|
BankBReg[52] <= 12'h000;
|
| 519 |
|
|
BankBReg[53] <= 12'h000;
|
| 520 |
|
|
BankBReg[54] <= 12'h000;
|
| 521 |
|
|
BankBReg[55] <= 12'h000;
|
| 522 |
|
|
BankBReg[56] <= 12'h000;
|
| 523 |
|
|
BankBReg[57] <= 12'h000;
|
| 524 |
|
|
BankBReg[58] <= 12'h000;
|
| 525 |
|
|
BankBReg[59] <= 12'h000;
|
| 526 |
|
|
BankBReg[60] <= 12'h000;
|
| 527 |
|
|
BankBReg[61] <= 12'h000;
|
| 528 |
|
|
BankBReg[62] <= 12'h000;
|
| 529 |
|
|
BankBReg[63] <= 12'h000;
|
| 530 |
|
|
end else begin // if (!rst)
|
| 531 |
|
|
if(DataInEnable == 1'b1 & DataInBank == 1'b1) begin
|
| 532 |
|
|
case(DataInPage)
|
| 533 |
|
|
3'd0: begin
|
| 534 |
|
|
case(DataInCount)
|
| 535 |
|
|
2'd0: begin
|
| 536 |
|
|
BankBReg[0] <= Data0In;
|
| 537 |
|
|
BankBReg[7] <= Data1In;
|
| 538 |
|
|
end
|
| 539 |
|
|
2'd1: begin
|
| 540 |
|
|
BankBReg[1] <= Data0In;
|
| 541 |
|
|
BankBReg[6] <= Data1In;
|
| 542 |
|
|
end
|
| 543 |
|
|
2'd2: begin
|
| 544 |
|
|
BankBReg[2] <= Data0In;
|
| 545 |
|
|
BankBReg[5] <= Data1In;
|
| 546 |
|
|
end
|
| 547 |
|
|
2'd3: begin
|
| 548 |
|
|
BankBReg[3] <= Data0In;
|
| 549 |
|
|
BankBReg[4] <= Data1In;
|
| 550 |
|
|
end
|
| 551 |
|
|
endcase // case(DataInCount)
|
| 552 |
|
|
end // case: 3'd0
|
| 553 |
|
|
3'd1: begin
|
| 554 |
|
|
case(DataInCount)
|
| 555 |
|
|
2'd0: begin
|
| 556 |
|
|
BankBReg[8] <= Data0In;
|
| 557 |
|
|
BankBReg[15] <= Data1In;
|
| 558 |
|
|
end
|
| 559 |
|
|
2'd1: begin
|
| 560 |
|
|
BankBReg[9] <= Data0In;
|
| 561 |
|
|
BankBReg[14] <= Data1In;
|
| 562 |
|
|
end
|
| 563 |
|
|
2'd2: begin
|
| 564 |
|
|
BankBReg[10] <= Data0In;
|
| 565 |
|
|
BankBReg[13] <= Data1In;
|
| 566 |
|
|
end
|
| 567 |
|
|
2'd3: begin
|
| 568 |
|
|
BankBReg[11] <= Data0In;
|
| 569 |
|
|
BankBReg[12] <= Data1In;
|
| 570 |
|
|
end
|
| 571 |
|
|
endcase // case(DataInCount)
|
| 572 |
|
|
end // case: 3'd1
|
| 573 |
|
|
3'd2: begin
|
| 574 |
|
|
case(DataInCount)
|
| 575 |
|
|
2'd0: begin
|
| 576 |
|
|
BankBReg[16] <= Data0In;
|
| 577 |
|
|
BankBReg[23] <= Data1In;
|
| 578 |
|
|
end
|
| 579 |
|
|
2'd1: begin
|
| 580 |
|
|
BankBReg[17] <= Data0In;
|
| 581 |
|
|
BankBReg[22] <= Data1In;
|
| 582 |
|
|
end
|
| 583 |
|
|
2'd2: begin
|
| 584 |
|
|
BankBReg[18] <= Data0In;
|
| 585 |
|
|
BankBReg[21] <= Data1In;
|
| 586 |
|
|
end
|
| 587 |
|
|
2'd3: begin
|
| 588 |
|
|
BankBReg[19] <= Data0In;
|
| 589 |
|
|
BankBReg[20] <= Data1In;
|
| 590 |
|
|
end
|
| 591 |
|
|
endcase // case(DataInCount)
|
| 592 |
|
|
end // case: 3'd2
|
| 593 |
|
|
3'd3: begin
|
| 594 |
|
|
case(DataInCount)
|
| 595 |
|
|
2'd0: begin
|
| 596 |
|
|
BankBReg[24] <= Data0In;
|
| 597 |
|
|
BankBReg[31] <= Data1In;
|
| 598 |
|
|
end
|
| 599 |
|
|
2'd1: begin
|
| 600 |
|
|
BankBReg[25] <= Data0In;
|
| 601 |
|
|
BankBReg[30] <= Data1In;
|
| 602 |
|
|
end
|
| 603 |
|
|
2'd2: begin
|
| 604 |
|
|
BankBReg[26] <= Data0In;
|
| 605 |
|
|
BankBReg[29] <= Data1In;
|
| 606 |
|
|
end
|
| 607 |
|
|
2'd3: begin
|
| 608 |
|
|
BankBReg[27] <= Data0In;
|
| 609 |
|
|
BankBReg[28] <= Data1In;
|
| 610 |
|
|
end
|
| 611 |
|
|
endcase // case(DataInCount)
|
| 612 |
|
|
end // case: 3'd3
|
| 613 |
|
|
3'd4: begin
|
| 614 |
|
|
case(DataInCount)
|
| 615 |
|
|
2'd0: begin
|
| 616 |
|
|
BankBReg[32] <= Data0In;
|
| 617 |
|
|
BankBReg[39] <= Data1In;
|
| 618 |
|
|
end
|
| 619 |
|
|
2'd1: begin
|
| 620 |
|
|
BankBReg[33] <= Data0In;
|
| 621 |
|
|
BankBReg[38] <= Data1In;
|
| 622 |
|
|
end
|
| 623 |
|
|
2'd2: begin
|
| 624 |
|
|
BankBReg[34] <= Data0In;
|
| 625 |
|
|
BankBReg[37] <= Data1In;
|
| 626 |
|
|
end
|
| 627 |
|
|
2'd3: begin
|
| 628 |
|
|
BankBReg[35] <= Data0In;
|
| 629 |
|
|
BankBReg[36] <= Data1In;
|
| 630 |
|
|
end
|
| 631 |
|
|
endcase // case(DataInCount)
|
| 632 |
|
|
end // case: 3'd4
|
| 633 |
|
|
3'd5: begin
|
| 634 |
|
|
case(DataInCount)
|
| 635 |
|
|
2'd0: begin
|
| 636 |
|
|
BankBReg[40] <= Data0In;
|
| 637 |
|
|
BankBReg[47] <= Data1In;
|
| 638 |
|
|
end
|
| 639 |
|
|
2'd1: begin
|
| 640 |
|
|
BankBReg[41] <= Data0In;
|
| 641 |
|
|
BankBReg[46] <= Data1In;
|
| 642 |
|
|
end
|
| 643 |
|
|
2'd2: begin
|
| 644 |
|
|
BankBReg[42] <= Data0In;
|
| 645 |
|
|
BankBReg[45] <= Data1In;
|
| 646 |
|
|
end
|
| 647 |
|
|
2'd3: begin
|
| 648 |
|
|
BankBReg[43] <= Data0In;
|
| 649 |
|
|
BankBReg[44] <= Data1In;
|
| 650 |
|
|
end
|
| 651 |
|
|
endcase // case(DataInCount)
|
| 652 |
|
|
end // case: 3'd5
|
| 653 |
|
|
3'd6: begin
|
| 654 |
|
|
case(DataInCount)
|
| 655 |
|
|
2'd0: begin
|
| 656 |
|
|
BankBReg[48] <= Data0In;
|
| 657 |
|
|
BankBReg[55] <= Data1In;
|
| 658 |
|
|
end
|
| 659 |
|
|
2'd1: begin
|
| 660 |
|
|
BankBReg[49] <= Data0In;
|
| 661 |
|
|
BankBReg[54] <= Data1In;
|
| 662 |
|
|
end
|
| 663 |
|
|
2'd2: begin
|
| 664 |
|
|
BankBReg[50] <= Data0In;
|
| 665 |
|
|
BankBReg[53] <= Data1In;
|
| 666 |
|
|
end
|
| 667 |
|
|
2'd3: begin
|
| 668 |
|
|
BankBReg[51] <= Data0In;
|
| 669 |
|
|
BankBReg[52] <= Data1In;
|
| 670 |
|
|
end
|
| 671 |
|
|
endcase // case(DataInCount)
|
| 672 |
|
|
end // case: 3'd6
|
| 673 |
|
|
3'd7: begin
|
| 674 |
|
|
case(DataInCount)
|
| 675 |
|
|
2'd0: begin
|
| 676 |
|
|
BankBReg[56] <= Data0In;
|
| 677 |
|
|
BankBReg[63] <= Data1In;
|
| 678 |
|
|
end
|
| 679 |
|
|
2'd1: begin
|
| 680 |
|
|
BankBReg[57] <= Data0In;
|
| 681 |
|
|
BankBReg[62] <= Data1In;
|
| 682 |
|
|
end
|
| 683 |
|
|
2'd2: begin
|
| 684 |
|
|
BankBReg[58] <= Data0In;
|
| 685 |
|
|
BankBReg[61] <= Data1In;
|
| 686 |
|
|
end
|
| 687 |
|
|
2'd3: begin
|
| 688 |
|
|
BankBReg[59] <= Data0In;
|
| 689 |
|
|
BankBReg[60] <= Data1In;
|
| 690 |
|
|
end
|
| 691 |
|
|
endcase // case(DataInCount)
|
| 692 |
|
|
end // case: 3'd7
|
| 693 |
|
|
endcase // case(DataInPage)
|
| 694 |
|
|
end // if (DataInEnable == 1'b1 & DataInBank == 1'b1)
|
| 695 |
|
|
end // else: !if(!rst)
|
| 696 |
|
|
end // always @ (posedge clk or negedge rst)
|
| 697 |
|
|
|
| 698 |
|
|
assign Data00Out = (DataOutSel)?BankBReg[00]:BankAReg[00];
|
| 699 |
|
|
assign Data01Out = (DataOutSel)?BankBReg[08]:BankAReg[08];
|
| 700 |
|
|
assign Data02Out = (DataOutSel)?BankBReg[16]:BankAReg[16];
|
| 701 |
|
|
assign Data03Out = (DataOutSel)?BankBReg[24]:BankAReg[24];
|
| 702 |
|
|
assign Data04Out = (DataOutSel)?BankBReg[32]:BankAReg[32];
|
| 703 |
|
|
assign Data05Out = (DataOutSel)?BankBReg[40]:BankAReg[40];
|
| 704 |
|
|
assign Data06Out = (DataOutSel)?BankBReg[48]:BankAReg[48];
|
| 705 |
|
|
assign Data07Out = (DataOutSel)?BankBReg[56]:BankAReg[56];
|
| 706 |
|
|
assign Data08Out = (DataOutSel)?BankBReg[01]:BankAReg[01];
|
| 707 |
|
|
assign Data09Out = (DataOutSel)?BankBReg[09]:BankAReg[09];
|
| 708 |
|
|
assign Data10Out = (DataOutSel)?BankBReg[17]:BankAReg[17];
|
| 709 |
|
|
assign Data11Out = (DataOutSel)?BankBReg[25]:BankAReg[25];
|
| 710 |
|
|
assign Data12Out = (DataOutSel)?BankBReg[33]:BankAReg[33];
|
| 711 |
|
|
assign Data13Out = (DataOutSel)?BankBReg[41]:BankAReg[41];
|
| 712 |
|
|
assign Data14Out = (DataOutSel)?BankBReg[49]:BankAReg[49];
|
| 713 |
|
|
assign Data15Out = (DataOutSel)?BankBReg[57]:BankAReg[57];
|
| 714 |
|
|
assign Data16Out = (DataOutSel)?BankBReg[02]:BankAReg[02];
|
| 715 |
|
|
assign Data17Out = (DataOutSel)?BankBReg[10]:BankAReg[10];
|
| 716 |
|
|
assign Data18Out = (DataOutSel)?BankBReg[18]:BankAReg[18];
|
| 717 |
|
|
assign Data19Out = (DataOutSel)?BankBReg[26]:BankAReg[26];
|
| 718 |
|
|
assign Data20Out = (DataOutSel)?BankBReg[34]:BankAReg[34];
|
| 719 |
|
|
assign Data21Out = (DataOutSel)?BankBReg[42]:BankAReg[42];
|
| 720 |
|
|
assign Data22Out = (DataOutSel)?BankBReg[50]:BankAReg[50];
|
| 721 |
|
|
assign Data23Out = (DataOutSel)?BankBReg[58]:BankAReg[58];
|
| 722 |
|
|
assign Data24Out = (DataOutSel)?BankBReg[03]:BankAReg[03];
|
| 723 |
|
|
assign Data25Out = (DataOutSel)?BankBReg[11]:BankAReg[11];
|
| 724 |
|
|
assign Data26Out = (DataOutSel)?BankBReg[19]:BankAReg[19];
|
| 725 |
|
|
assign Data27Out = (DataOutSel)?BankBReg[27]:BankAReg[27];
|
| 726 |
|
|
assign Data28Out = (DataOutSel)?BankBReg[35]:BankAReg[35];
|
| 727 |
|
|
assign Data29Out = (DataOutSel)?BankBReg[43]:BankAReg[43];
|
| 728 |
|
|
assign Data30Out = (DataOutSel)?BankBReg[51]:BankAReg[51];
|
| 729 |
|
|
assign Data31Out = (DataOutSel)?BankBReg[59]:BankAReg[59];
|
| 730 |
|
|
assign Data32Out = (DataOutSel)?BankBReg[04]:BankAReg[04];
|
| 731 |
|
|
assign Data33Out = (DataOutSel)?BankBReg[12]:BankAReg[12];
|
| 732 |
|
|
assign Data34Out = (DataOutSel)?BankBReg[20]:BankAReg[20];
|
| 733 |
|
|
assign Data35Out = (DataOutSel)?BankBReg[28]:BankAReg[28];
|
| 734 |
|
|
assign Data36Out = (DataOutSel)?BankBReg[36]:BankAReg[36];
|
| 735 |
|
|
assign Data37Out = (DataOutSel)?BankBReg[44]:BankAReg[44];
|
| 736 |
|
|
assign Data38Out = (DataOutSel)?BankBReg[52]:BankAReg[52];
|
| 737 |
|
|
assign Data39Out = (DataOutSel)?BankBReg[60]:BankAReg[60];
|
| 738 |
|
|
assign Data40Out = (DataOutSel)?BankBReg[05]:BankAReg[05];
|
| 739 |
|
|
assign Data41Out = (DataOutSel)?BankBReg[13]:BankAReg[13];
|
| 740 |
|
|
assign Data42Out = (DataOutSel)?BankBReg[21]:BankAReg[21];
|
| 741 |
|
|
assign Data43Out = (DataOutSel)?BankBReg[29]:BankAReg[29];
|
| 742 |
|
|
assign Data44Out = (DataOutSel)?BankBReg[37]:BankAReg[37];
|
| 743 |
|
|
assign Data45Out = (DataOutSel)?BankBReg[45]:BankAReg[45];
|
| 744 |
|
|
assign Data46Out = (DataOutSel)?BankBReg[53]:BankAReg[53];
|
| 745 |
|
|
assign Data47Out = (DataOutSel)?BankBReg[61]:BankAReg[61];
|
| 746 |
|
|
assign Data48Out = (DataOutSel)?BankBReg[06]:BankAReg[06];
|
| 747 |
|
|
assign Data49Out = (DataOutSel)?BankBReg[14]:BankAReg[14];
|
| 748 |
|
|
assign Data50Out = (DataOutSel)?BankBReg[22]:BankAReg[22];
|
| 749 |
|
|
assign Data51Out = (DataOutSel)?BankBReg[30]:BankAReg[30];
|
| 750 |
|
|
assign Data52Out = (DataOutSel)?BankBReg[38]:BankAReg[38];
|
| 751 |
|
|
assign Data53Out = (DataOutSel)?BankBReg[46]:BankAReg[46];
|
| 752 |
|
|
assign Data54Out = (DataOutSel)?BankBReg[54]:BankAReg[54];
|
| 753 |
|
|
assign Data55Out = (DataOutSel)?BankBReg[62]:BankAReg[62];
|
| 754 |
|
|
assign Data56Out = (DataOutSel)?BankBReg[07]:BankAReg[07];
|
| 755 |
|
|
assign Data57Out = (DataOutSel)?BankBReg[15]:BankAReg[15];
|
| 756 |
|
|
assign Data58Out = (DataOutSel)?BankBReg[23]:BankAReg[23];
|
| 757 |
|
|
assign Data59Out = (DataOutSel)?BankBReg[31]:BankAReg[31];
|
| 758 |
|
|
assign Data60Out = (DataOutSel)?BankBReg[39]:BankAReg[39];
|
| 759 |
|
|
assign Data61Out = (DataOutSel)?BankBReg[47]:BankAReg[47];
|
| 760 |
|
|
assign Data62Out = (DataOutSel)?BankBReg[55]:BankAReg[55];
|
| 761 |
|
|
assign Data63Out = (DataOutSel)?BankBReg[63]:BankAReg[63];
|
| 762 |
|
|
|
| 763 |
|
|
endmodule // jpeg_idctb
|
